tree 15ee2d5e876e90346557da6e7ff52f57083bf3c2
parent 45c9d966688e7fad7f24bfc450547d91e4304d0b
parent f891b7cdbdcda116fd26bbd706f91bd58567aa17
author David S. Miller <davem@davemloft.net> 1633430558 +0100
committer David S. Miller <davem@davemloft.net> 1633430558 +0100
mergetag object f891b7cdbdcda116fd26bbd706f91bd58567aa17
 type commit
 tag mlx5-updates-2021-10-04
 tagger Saeed Mahameed <saeedm@nvidia.com> 1633396257 -0700
 
 mlx5-updates-2021-10-04
 
 Misc updates for mlx5 driver
 
 1) Add TX max rate support for MQPRIO channel mode
 2) Trivial TC action and modify header refactoring
 3) TC support for accept action in fdb offloads
 4) Allow single IRQ for PCI functions
 
 5) Bridge offload: Pop PVID VLAN header on egress miss
 
 Vlad Buslov says:
 =================
 
 With current architecture of mlx5 bridge offload it is possible for a
 packet to match in ingress table by source MAC (resulting VLAN header push
 in case of port with configured PVID) and then miss in egress table when
 destination MAC is not in FDB. Due to the lack of hardware learning in
 NICs, this, in turn, results packet going to software data path with PVID
 VLAN already added by hardware. This doesn't break software bridge since it
 accepts either untagged packets or packets with any provisioned VLAN on
 ports with PVID, but can break ingress TC, if affected part of Ethernet
 header is matched by classifier.
 
 Improve compatibility with software TC by restoring the packet header on
 egress miss. Effectively, this change implements atomicity of mlx5 bridge
 offload implementation - packet is either modified and redirected to
 destination port or appears unmodified in software.
 
 =================
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Merge tag 'mlx5-updates-2021-10-04' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says:

====================
mlx5-updates-2021-10-04

Misc updates for mlx5 driver

1) Add TX max rate support for MQPRIO channel mode
2) Trivial TC action and modify header refactoring
3) TC support for accept action in fdb offloads
4) Allow single IRQ for PCI functions

5) Bridge offload: Pop PVID VLAN header on egress miss

Vlad Buslov says:
=================

With current architecture of mlx5 bridge offload it is possible for a
packet to match in ingress table by source MAC (resulting VLAN header push
in case of port with configured PVID) and then miss in egress table when
destination MAC is not in FDB. Due to the lack of hardware learning in
NICs, this, in turn, results packet going to software data path with PVID
VLAN already added by hardware. This doesn't break software bridge since it
accepts either untagged packets or packets with any provisioned VLAN on
ports with PVID, but can break ingress TC, if affected part of Ethernet
header is matched by classifier.

Improve compatibility with software TC by restoring the packet header on
egress miss. Effectively, this change implements atomicity of mlx5 bridge
offload implementation - packet is either modified and redirected to
destination port or appears unmodified in software.

=================

=================

Signed-off-by: David S. Miller <davem@davemloft.net>