arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts

// SPDX-License-Identifier: (GPL-2.0 OR MIT)

#include "armada-385-clearfog-gtr.dtsi"

/ {
	model = "SolidRun Clearfog GTR L8";
};

&mdio {
	switch0: switch0@4 {
		compatible = "marvell,mv88e6190";
		reg = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&cf_gtr_switch_reset_pins>;
		reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;
				label = "lan8";
				phy-handle = <&switch0phy0>;
			};

			port@2 {
				reg = <2>;
				label = "lan7";
				phy-handle = <&switch0phy1>;
			};

			port@3 {
				reg = <3>;
				label = "lan6";
				phy-handle = <&switch0phy2>;
			};

			port@4 {
				reg = <4>;
				label = "lan5";
				phy-handle = <&switch0phy3>;
			};

			port@5 {
				reg = <5>;
				label = "lan4";
				phy-handle = <&switch0phy4>;
			};

			port@6 {
				reg = <6>;
				label = "lan3";
				phy-handle = <&switch0phy5>;
			};

			port@7 {
				reg = <7>;
				label = "lan2";
				phy-handle = <&switch0phy6>;
			};

			port@8 {
				reg = <8>;
				label = "lan1";
				phy-handle = <&switch0phy7>;
			};

			port@10 {
				reg = <10>;
				label = "cpu";
				ethernet = <&eth1>;
			};

		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0phy0: switch0phy0@1 {
				reg = <0x1>;
			};

			switch0phy1: switch0phy1@2 {
				reg = <0x2>;
			};

			switch0phy2: switch0phy2@3 {
				reg = <0x3>;
			};

			switch0phy3: switch0phy3@4 {
				reg = <0x4>;
			};

			switch0phy4: switch0phy4@5 {
				reg = <0x5>;
			};

			switch0phy5: switch0phy5@6 {
				reg = <0x6>;
			};

			switch0phy6: switch0phy6@7 {
				reg = <0x7>;
			};

			switch0phy7: switch0phy7@8 {
				reg = <0x8>;
			};
		};

	};
};