blob: 27bb8c1ab85876bed4ad23bfc6df7648eaa8a851 [file] [log] [blame]
/*
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _dce_12_0_OFFSET_HEADER
#define _dce_12_0_OFFSET_HEADER
// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
// base address: 0x48
#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
// base address: 0x4c
#define mmdispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
// addressBlock: dce_dc_dc_perfmon0_dispdec
// base address: 0x0
#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0020
#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0022
#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL 0x0023
#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL2 0x0024
#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0025
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0026
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_HI 0x0027
#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_LOW 0x0028
#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon13_dispdec
// base address: 0x30
#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x002c
#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x002d
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x002e
#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CNTL 0x002f
#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CNTL2 0x0030
#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0031
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0032
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_HI 0x0033
#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_LOW 0x0034
#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dc_displaypllregs_dispdec
// base address: 0x0
#define mmPPLL_VREG_CFG 0x0038
#define mmPPLL_VREG_CFG_BASE_IDX 2
#define mmPPLL_MODE_CNTL 0x0039
#define mmPPLL_MODE_CNTL_BASE_IDX 2
#define mmPPLL_FREQ_CTRL0 0x003a
#define mmPPLL_FREQ_CTRL0_BASE_IDX 2
#define mmPPLL_FREQ_CTRL1 0x003b
#define mmPPLL_FREQ_CTRL1_BASE_IDX 2
#define mmPPLL_FREQ_CTRL2 0x003c
#define mmPPLL_FREQ_CTRL2_BASE_IDX 2
#define mmPPLL_FREQ_CTRL3 0x003d
#define mmPPLL_FREQ_CTRL3_BASE_IDX 2
#define mmPPLL_BW_CTRL_COARSE 0x003e
#define mmPPLL_BW_CTRL_COARSE_BASE_IDX 2
#define mmPPLL_BW_CTRL_FINE 0x0040
#define mmPPLL_BW_CTRL_FINE_BASE_IDX 2
#define mmPPLL_CAL_CTRL 0x0041
#define mmPPLL_CAL_CTRL_BASE_IDX 2
#define mmPPLL_LOOP_CTRL 0x0042
#define mmPPLL_LOOP_CTRL_BASE_IDX 2
#define mmPPLL_REFCLK_CNTL 0x0050
#define mmPPLL_REFCLK_CNTL_BASE_IDX 2
#define mmPPLL_CLKOUT_CNTL 0x0051
#define mmPPLL_CLKOUT_CNTL_BASE_IDX 2
#define mmPPLL_DFT_CNTL 0x0052
#define mmPPLL_DFT_CNTL_BASE_IDX 2
#define mmPPLL_ANALOG_CNTL 0x0053
#define mmPPLL_ANALOG_CNTL_BASE_IDX 2
#define mmPPLL_POSTDIV 0x0054
#define mmPPLL_POSTDIV_BASE_IDX 2
#define mmPPLL_OBSERVE0 0x0059
#define mmPPLL_OBSERVE0_BASE_IDX 2
#define mmPPLL_OBSERVE1 0x005a
#define mmPPLL_OBSERVE1_BASE_IDX 2
#define mmPPLL_UPDATE_CNTL 0x005c
#define mmPPLL_UPDATE_CNTL_BASE_IDX 2
#define mmPPLL_OBSERVE0_OUT 0x005d
#define mmPPLL_OBSERVE0_OUT_BASE_IDX 2
// addressBlock: dce_dc_dccg_pll0_dispdec
// base address: 0x0
#define mmPLL_MACRO_CNTL_RESERVED0 0x0038
#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED1 0x0039
#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED2 0x003a
#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED3 0x003b
#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED4 0x003c
#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED5 0x003d
#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED6 0x003e
#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED7 0x003f
#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED8 0x0040
#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED9 0x0041
#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED10 0x0042
#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED11 0x0043
#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED12 0x0044
#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED13 0x0045
#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED14 0x0046
#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED15 0x0047
#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED16 0x0048
#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED17 0x0049
#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED18 0x004a
#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED19 0x004b
#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED20 0x004c
#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED21 0x004d
#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED22 0x004e
#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED23 0x004f
#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED24 0x0050
#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED25 0x0051
#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED26 0x0052
#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED27 0x0053
#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED28 0x0054
#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED29 0x0055
#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED30 0x0056
#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED31 0x0057
#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED32 0x0058
#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED33 0x0059
#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED34 0x005a
#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED35 0x005b
#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED36 0x005c
#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED37 0x005d
#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED38 0x005e
#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED39 0x005f
#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED40 0x0060
#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED41 0x0061
#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon1_dispdec
// base address: 0x598
#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x0186
#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x0187
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x0188
#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CNTL 0x0189
#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CNTL2 0x018a
#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x018b
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x018c
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_HI 0x018d
#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_LOW 0x018e
#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_mcif_wb0_dispdec
// base address: 0x0
#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x0272
#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x0273
#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x0274
#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x0275
#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x0276
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x0277
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x0278
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x0279
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x027a
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x027b
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x027c
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x027d
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x027e
#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x027f
#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x0282
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0283
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x0284
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0285
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x0286
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0287
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x0288
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0289
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x028a
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x028b
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x028c
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x028d
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x028e
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x028f
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x0290
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0291
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x0292
#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0293
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x0294
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x0295
#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x0296
#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x0297
#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x0298
#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x0299
#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x029b
#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x029c
#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
// addressBlock: dce_dc_mcif_wb1_dispdec
// base address: 0x100
#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02b4
#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02b5
#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02b6
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02b7
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02b8
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02b9
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02ba
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02bb
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02bc
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02bd
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02be
#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02bf
#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x02c2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x02c4
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x02c6
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x02c8
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x02ca
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x02cc
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x02ce
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x02d0
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x02d5
#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x02d7
#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x02d9
#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x02db
#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
// addressBlock: dce_dc_mcif_wb2_dispdec
// base address: 0x200
#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x02f4
#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x02f5
#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x02f6
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x02f7
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x02f8
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x02f9
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x02fa
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x02fb
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x02fc
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x02fd
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x02fe
#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x02ff
#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x0302
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x0304
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x0306
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x0308
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x030a
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x030c
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x030e
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x0310
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x0314
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x0315
#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x0317
#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x0319
#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x031b
#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x031c
#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
// addressBlock: dce_dc_cwb0_dispdec
// base address: 0x0
#define mmCWB0_CWB_CTRL 0x0332
#define mmCWB0_CWB_CTRL_BASE_IDX 2
#define mmCWB0_CWB_FENCE_PAR0 0x0334
#define mmCWB0_CWB_FENCE_PAR0_BASE_IDX 2
#define mmCWB0_CWB_FENCE_PAR1 0x0335
#define mmCWB0_CWB_FENCE_PAR1_BASE_IDX 2
#define mmCWB0_CWB_CRC_CTRL 0x0339
#define mmCWB0_CWB_CRC_CTRL_BASE_IDX 2
#define mmCWB0_CWB_CRC_RED_GREEN_MASK 0x033a
#define mmCWB0_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
#define mmCWB0_CWB_CRC_BLUE_MASK 0x033b
#define mmCWB0_CWB_CRC_BLUE_MASK_BASE_IDX 2
#define mmCWB0_CWB_CRC_RED_GREEN_RESULT 0x033c
#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
#define mmCWB0_CWB_CRC_BLUE_RESULT 0x033d
#define mmCWB0_CWB_CRC_BLUE_RESULT_BASE_IDX 2
// addressBlock: dce_dc_cwb1_dispdec
// base address: 0x60
#define mmCWB1_CWB_CTRL 0x034a
#define mmCWB1_CWB_CTRL_BASE_IDX 2
#define mmCWB1_CWB_FENCE_PAR0 0x034c
#define mmCWB1_CWB_FENCE_PAR0_BASE_IDX 2
#define mmCWB1_CWB_FENCE_PAR1 0x034d
#define mmCWB1_CWB_FENCE_PAR1_BASE_IDX 2
#define mmCWB1_CWB_CRC_CTRL 0x0351
#define mmCWB1_CWB_CRC_CTRL_BASE_IDX 2
#define mmCWB1_CWB_CRC_RED_GREEN_MASK 0x0352
#define mmCWB1_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
#define mmCWB1_CWB_CRC_BLUE_MASK 0x0353
#define mmCWB1_CWB_CRC_BLUE_MASK_BASE_IDX 2
#define mmCWB1_CWB_CRC_RED_GREEN_RESULT 0x0354
#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
#define mmCWB1_CWB_CRC_BLUE_RESULT 0x0355
#define mmCWB1_CWB_CRC_BLUE_RESULT_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon9_dispdec
// base address: 0xd08
#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0362
#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0363
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0364
#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CNTL 0x0365
#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CNTL2 0x0366
#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0367
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0368
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_HI 0x0369
#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_LOW 0x036a
#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dispdec
// base address: 0x0
#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
#define mmVGA_RENDER_CONTROL 0x0000
#define mmVGA_RENDER_CONTROL_BASE_IDX 1
#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
#define mmVGA_MODE_CONTROL 0x0002
#define mmVGA_MODE_CONTROL_BASE_IDX 1
#define mmVGA_SURFACE_PITCH_SELECT 0x0003
#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
#define mmVGA_HDP_CONTROL 0x000a
#define mmVGA_HDP_CONTROL_BASE_IDX 1
#define mmVGA_CACHE_CONTROL 0x000b
#define mmVGA_CACHE_CONTROL_BASE_IDX 1
#define mmD1VGA_CONTROL 0x000c
#define mmD1VGA_CONTROL_BASE_IDX 1
#define mmD2VGA_CONTROL 0x000e
#define mmD2VGA_CONTROL_BASE_IDX 1
#define mmVGA_STATUS 0x0010
#define mmVGA_STATUS_BASE_IDX 1
#define mmVGA_INTERRUPT_CONTROL 0x0011
#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
#define mmVGA_STATUS_CLEAR 0x0012
#define mmVGA_STATUS_CLEAR_BASE_IDX 1
#define mmVGA_INTERRUPT_STATUS 0x0013
#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
#define mmVGA_MAIN_CONTROL 0x0014
#define mmVGA_MAIN_CONTROL_BASE_IDX 1
#define mmVGA_TEST_CONTROL 0x0015
#define mmVGA_TEST_CONTROL_BASE_IDX 1
#define mmVGA_QOS_CTRL 0x0018
#define mmVGA_QOS_CTRL_BASE_IDX 1
#define mmCRTC8_IDX 0x002d
#define mmCRTC8_IDX_BASE_IDX 1
#define mmCRTC8_DATA 0x002d
#define mmCRTC8_DATA_BASE_IDX 1
#define mmGENFC_WT 0x002e
#define mmGENFC_WT_BASE_IDX 1
#define mmGENS1 0x002e
#define mmGENS1_BASE_IDX 1
#define mmATTRDW 0x0030
#define mmATTRDW_BASE_IDX 1
#define mmATTRX 0x0030
#define mmATTRX_BASE_IDX 1
#define mmATTRDR 0x0030
#define mmATTRDR_BASE_IDX 1
#define mmGENMO_WT 0x0030
#define mmGENMO_WT_BASE_IDX 1
#define mmGENS0 0x0030
#define mmGENS0_BASE_IDX 1
#define mmGENENB 0x0030
#define mmGENENB_BASE_IDX 1
#define mmSEQ8_IDX 0x0031
#define mmSEQ8_IDX_BASE_IDX 1
#define mmSEQ8_DATA 0x0031
#define mmSEQ8_DATA_BASE_IDX 1
#define mmDAC_MASK 0x0031
#define mmDAC_MASK_BASE_IDX 1
#define mmDAC_R_INDEX 0x0031
#define mmDAC_R_INDEX_BASE_IDX 1
#define mmDAC_W_INDEX 0x0032
#define mmDAC_W_INDEX_BASE_IDX 1
#define mmDAC_DATA 0x0032
#define mmDAC_DATA_BASE_IDX 1
#define mmGENFC_RD 0x0032
#define mmGENFC_RD_BASE_IDX 1
#define mmGENMO_RD 0x0033
#define mmGENMO_RD_BASE_IDX 1
#define mmGRPH8_IDX 0x0033
#define mmGRPH8_IDX_BASE_IDX 1
#define mmGRPH8_DATA 0x0033
#define mmGRPH8_DATA_BASE_IDX 1
#define mmCRTC8_IDX_1 0x0035
#define mmCRTC8_IDX_1_BASE_IDX 1
#define mmCRTC8_DATA_1 0x0035
#define mmCRTC8_DATA_1_BASE_IDX 1
#define mmGENFC_WT_1 0x0036
#define mmGENFC_WT_1_BASE_IDX 1
#define mmGENS1_1 0x0036
#define mmGENS1_1_BASE_IDX 1
#define mmD3VGA_CONTROL 0x0038
#define mmD3VGA_CONTROL_BASE_IDX 1
#define mmD4VGA_CONTROL 0x0039
#define mmD4VGA_CONTROL_BASE_IDX 1
#define mmD5VGA_CONTROL 0x003a
#define mmD5VGA_CONTROL_BASE_IDX 1
#define mmD6VGA_CONTROL 0x003b
#define mmD6VGA_CONTROL_BASE_IDX 1
#define mmVGA_SOURCE_SELECT 0x003c
#define mmVGA_SOURCE_SELECT_BASE_IDX 1
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x0044
#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL 0x0045
#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmSYMCLKLPA_CLOCK_ENABLE 0x0046
#define mmSYMCLKLPA_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKLPB_CLOCK_ENABLE 0x0047
#define mmSYMCLKLPB_CLOCK_ENABLE_BASE_IDX 1
#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmREFCLK_CNTL 0x0049
#define mmREFCLK_CNTL_BASE_IDX 1
#define mmMIPI_CLK_CNTL 0x004a
#define mmMIPI_CLK_CNTL_BASE_IDX 1
#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL2 0x004e
#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f
#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_CBUS_WRCMD_DELAY 0x0050
#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1
#define mmDCCG_DS_DTO_INCR 0x0053
#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
#define mmDCCG_DS_DTO_MODULO 0x0054
#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
#define mmDCCG_DS_CNTL 0x0055
#define mmDCCG_DS_CNTL_BASE_IDX 1
#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
#define mmSYMCLKG_CLOCK_ENABLE 0x0057
#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1
#define mmDPREFCLK_CNTL 0x0058
#define mmDPREFCLK_CNTL_BASE_IDX 1
#define mmAOMCLK0_CNTL 0x0059
#define mmAOMCLK0_CNTL_BASE_IDX 1
#define mmAOMCLK1_CNTL 0x005a
#define mmAOMCLK1_CNTL_BASE_IDX 1
#define mmAOMCLK2_CNTL 0x005b
#define mmAOMCLK2_CNTL_BASE_IDX 1
#define mmDCCG_AUDIO_DTO2_PHASE 0x005c
#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO2_MODULO 0x005d
#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1
#define mmDCE_VERSION 0x005e
#define mmDCE_VERSION_BASE_IDX 1
#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCCG_GTC_CNTL 0x0060
#define mmDCCG_GTC_CNTL_BASE_IDX 1
#define mmDCCG_GTC_DTO_INCR 0x0061
#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
#define mmDCCG_GTC_DTO_MODULO 0x0062
#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
#define mmDCCG_GTC_CURRENT 0x0063
#define mmDCCG_GTC_CURRENT_BASE_IDX 1
#define mmDENTIST_DISPCLK_CNTL 0x0064
#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
#define mmMIPI_DTO_CNTL 0x0065
#define mmMIPI_DTO_CNTL_BASE_IDX 1
#define mmMIPI_DTO_PHASE 0x0066
#define mmMIPI_DTO_PHASE_BASE_IDX 1
#define mmMIPI_DTO_MODULO 0x0067
#define mmMIPI_DTO_MODULO_BASE_IDX 1
#define mmDAC_CLK_ENABLE 0x0068
#define mmDAC_CLK_ENABLE_BASE_IDX 1
#define mmDVO_CLK_ENABLE 0x0069
#define mmDVO_CLK_ENABLE_BASE_IDX 1
#define mmAVSYNC_COUNTER_WRITE 0x006a
#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1
#define mmAVSYNC_COUNTER_CONTROL 0x006b
#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1
#define mmDMCU_SMU_INTERRUPT_CNTL 0x006c
#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 1
#define mmSMU_CONTROL 0x006d
#define mmSMU_CONTROL_BASE_IDX 1
#define mmSMU_INTERRUPT_CONTROL 0x006e
#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 1
#define mmAVSYNC_COUNTER_READ 0x006f
#define mmAVSYNC_COUNTER_READ_BASE_IDX 1
#define mmMILLISECOND_TIME_BASE_DIV 0x0070
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL 0x0073
#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL 0x0074
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmSCLK_CGTT_BLK_CTRL_REG 0x0076
#define mmSCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_CAC_STATUS 0x0077
#define mmDCCG_CAC_STATUS_BASE_IDX 1
#define mmPIXCLK1_RESYNC_CNTL 0x0078
#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1
#define mmPIXCLK2_RESYNC_CNTL 0x0079
#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1
#define mmPIXCLK0_RESYNC_CNTL 0x007a
#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1
#define mmMICROSECOND_TIME_BASE_DIV 0x007b
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCCG_DISP_CNTL_REG 0x007f
#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
#define mmCRTC0_PIXEL_RATE_CNTL 0x0080
#define mmCRTC0_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO0_PHASE 0x0081
#define mmDP_DTO0_PHASE_BASE_IDX 1
#define mmDP_DTO0_MODULO 0x0082
#define mmDP_DTO0_MODULO_BASE_IDX 1
#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0x0083
#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmCRTC1_PIXEL_RATE_CNTL 0x0084
#define mmCRTC1_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO1_PHASE 0x0085
#define mmDP_DTO1_PHASE_BASE_IDX 1
#define mmDP_DTO1_MODULO 0x0086
#define mmDP_DTO1_MODULO_BASE_IDX 1
#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0x0087
#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmCRTC2_PIXEL_RATE_CNTL 0x0088
#define mmCRTC2_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO2_PHASE 0x0089
#define mmDP_DTO2_PHASE_BASE_IDX 1
#define mmDP_DTO2_MODULO 0x008a
#define mmDP_DTO2_MODULO_BASE_IDX 1
#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0x008b
#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmCRTC3_PIXEL_RATE_CNTL 0x008c
#define mmCRTC3_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO3_PHASE 0x008d
#define mmDP_DTO3_PHASE_BASE_IDX 1
#define mmDP_DTO3_MODULO 0x008e
#define mmDP_DTO3_MODULO_BASE_IDX 1
#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0x008f
#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmCRTC4_PIXEL_RATE_CNTL 0x0090
#define mmCRTC4_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO4_PHASE 0x0091
#define mmDP_DTO4_PHASE_BASE_IDX 1
#define mmDP_DTO4_MODULO 0x0092
#define mmDP_DTO4_MODULO_BASE_IDX 1
#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0x0093
#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmCRTC5_PIXEL_RATE_CNTL 0x0094
#define mmCRTC5_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO5_PHASE 0x0095
#define mmDP_DTO5_PHASE_BASE_IDX 1
#define mmDP_DTO5_MODULO 0x0096
#define mmDP_DTO5_MODULO_BASE_IDX 1
#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0x0097
#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDCCG_SOFT_RESET 0x009f
#define mmDCCG_SOFT_RESET_BASE_IDX 1
#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
#define mmDVOACLKD_CNTL 0x00a8
#define mmDVOACLKD_CNTL_BASE_IDX 1
#define mmDVOACLKC_MVP_CNTL 0x00a9
#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1
#define mmDVOACLKC_CNTL 0x00aa
#define mmDVOACLKC_CNTL_BASE_IDX 1
#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
#define mmDCCG_TEST_CLK_SEL 0x00be
#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
#define mmFBC_CNTL 0x0062
#define mmFBC_CNTL_BASE_IDX 2
#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x0064
#define mmFBC_IDLE_FORCE_CLEAR_MASK_BASE_IDX 2
#define mmFBC_START_STOP_DELAY 0x0065
#define mmFBC_START_STOP_DELAY_BASE_IDX 2
#define mmFBC_COMP_CNTL 0x0066
#define mmFBC_COMP_CNTL_BASE_IDX 2
#define mmFBC_COMP_MODE 0x0067
#define mmFBC_COMP_MODE_BASE_IDX 2
#define mmFBC_IND_LUT0 0x006b
#define mmFBC_IND_LUT0_BASE_IDX 2
#define mmFBC_IND_LUT1 0x006c
#define mmFBC_IND_LUT1_BASE_IDX 2
#define mmFBC_IND_LUT2 0x006d
#define mmFBC_IND_LUT2_BASE_IDX 2
#define mmFBC_IND_LUT3 0x006e
#define mmFBC_IND_LUT3_BASE_IDX 2
#define mmFBC_IND_LUT4 0x006f
#define mmFBC_IND_LUT4_BASE_IDX 2
#define mmFBC_IND_LUT5 0x0070
#define mmFBC_IND_LUT5_BASE_IDX 2
#define mmFBC_IND_LUT6 0x0071
#define mmFBC_IND_LUT6_BASE_IDX 2
#define mmFBC_IND_LUT7 0x0072
#define mmFBC_IND_LUT7_BASE_IDX 2
#define mmFBC_IND_LUT8 0x0073
#define mmFBC_IND_LUT8_BASE_IDX 2
#define mmFBC_IND_LUT9 0x0074
#define mmFBC_IND_LUT9_BASE_IDX 2
#define mmFBC_IND_LUT10 0x0075
#define mmFBC_IND_LUT10_BASE_IDX 2
#define mmFBC_IND_LUT11 0x0076
#define mmFBC_IND_LUT11_BASE_IDX 2
#define mmFBC_IND_LUT12 0x0077
#define mmFBC_IND_LUT12_BASE_IDX 2
#define mmFBC_IND_LUT13 0x0078
#define mmFBC_IND_LUT13_BASE_IDX 2
#define mmFBC_IND_LUT14 0x0079
#define mmFBC_IND_LUT14_BASE_IDX 2
#define mmFBC_IND_LUT15 0x007a
#define mmFBC_IND_LUT15_BASE_IDX 2
#define mmFBC_CSM_REGION_OFFSET_01 0x007b
#define mmFBC_CSM_REGION_OFFSET_01_BASE_IDX 2
#define mmFBC_CSM_REGION_OFFSET_23 0x007c
#define mmFBC_CSM_REGION_OFFSET_23_BASE_IDX 2
#define mmFBC_CLIENT_REGION_MASK 0x007d
#define mmFBC_CLIENT_REGION_MASK_BASE_IDX 2
#define mmFBC_DEBUG_COMP 0x007e
#define mmFBC_DEBUG_COMP_BASE_IDX 2
#define mmFBC_MISC 0x0084
#define mmFBC_MISC_BASE_IDX 2
#define mmFBC_STATUS 0x0085
#define mmFBC_STATUS_BASE_IDX 2
#define mmFBC_ALPHA_CNTL 0x0088
#define mmFBC_ALPHA_CNTL_BASE_IDX 2
#define mmFBC_ALPHA_RGB_OVERRIDE 0x0089
#define mmFBC_ALPHA_RGB_OVERRIDE_BASE_IDX 2
#define mmPIPE0_PG_CONFIG 0x008e
#define mmPIPE0_PG_CONFIG_BASE_IDX 2
#define mmPIPE0_PG_ENABLE 0x008f
#define mmPIPE0_PG_ENABLE_BASE_IDX 2
#define mmPIPE0_PG_STATUS 0x0090
#define mmPIPE0_PG_STATUS_BASE_IDX 2
#define mmPIPE1_PG_CONFIG 0x0091
#define mmPIPE1_PG_CONFIG_BASE_IDX 2
#define mmPIPE1_PG_ENABLE 0x0092
#define mmPIPE1_PG_ENABLE_BASE_IDX 2
#define mmPIPE1_PG_STATUS 0x0093
#define mmPIPE1_PG_STATUS_BASE_IDX 2
#define mmPIPE2_PG_CONFIG 0x0094
#define mmPIPE2_PG_CONFIG_BASE_IDX 2
#define mmPIPE2_PG_ENABLE 0x0095
#define mmPIPE2_PG_ENABLE_BASE_IDX 2
#define mmPIPE2_PG_STATUS 0x0096
#define mmPIPE2_PG_STATUS_BASE_IDX 2
#define mmPIPE3_PG_CONFIG 0x0097
#define mmPIPE3_PG_CONFIG_BASE_IDX 2
#define mmPIPE3_PG_ENABLE 0x0098
#define mmPIPE3_PG_ENABLE_BASE_IDX 2
#define mmPIPE3_PG_STATUS 0x0099
#define mmPIPE3_PG_STATUS_BASE_IDX 2
#define mmPIPE4_PG_CONFIG 0x009a
#define mmPIPE4_PG_CONFIG_BASE_IDX 2
#define mmPIPE4_PG_ENABLE 0x009b
#define mmPIPE4_PG_ENABLE_BASE_IDX 2
#define mmPIPE4_PG_STATUS 0x009c
#define mmPIPE4_PG_STATUS_BASE_IDX 2
#define mmPIPE5_PG_CONFIG 0x009d
#define mmPIPE5_PG_CONFIG_BASE_IDX 2
#define mmPIPE5_PG_ENABLE 0x009e
#define mmPIPE5_PG_ENABLE_BASE_IDX 2
#define mmPIPE5_PG_STATUS 0x009f
#define mmPIPE5_PG_STATUS_BASE_IDX 2
#define mmDSI_PG_CONFIG 0x00a0
#define mmDSI_PG_CONFIG_BASE_IDX 2
#define mmDSI_PG_ENABLE 0x00a1
#define mmDSI_PG_ENABLE_BASE_IDX 2
#define mmDSI_PG_STATUS 0x00a2
#define mmDSI_PG_STATUS_BASE_IDX 2
#define mmDCFEV0_PG_CONFIG 0x00a3
#define mmDCFEV0_PG_CONFIG_BASE_IDX 2
#define mmDCFEV0_PG_ENABLE 0x00a4
#define mmDCFEV0_PG_ENABLE_BASE_IDX 2
#define mmDCFEV0_PG_STATUS 0x00a5
#define mmDCFEV0_PG_STATUS_BASE_IDX 2
#define mmDCPG_INTERRUPT_STATUS 0x00a6
#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL 0x00a7
#define mmDCPG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL2 0x00a8
#define mmDCPG_INTERRUPT_CONTROL2_BASE_IDX 2
#define mmDCFEV1_PG_CONFIG 0x00a9
#define mmDCFEV1_PG_CONFIG_BASE_IDX 2
#define mmDCFEV1_PG_ENABLE 0x00aa
#define mmDCFEV1_PG_ENABLE_BASE_IDX 2
#define mmDCFEV1_PG_STATUS 0x00ab
#define mmDCFEV1_PG_STATUS_BASE_IDX 2
#define mmDC_IP_REQUEST_CNTL 0x00ac
#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
#define mmDC_PGCNTL_STATUS_REG 0x00ad
#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2
#define mmDMIFV_STATUS 0x00c3
#define mmDMIFV_STATUS_BASE_IDX 2
#define mmDMIF_CONTROL 0x00c4
#define mmDMIF_CONTROL_BASE_IDX 2
#define mmDMIF_STATUS 0x00c5
#define mmDMIF_STATUS_BASE_IDX 2
#define mmDMIF_ARBITRATION_CONTROL 0x00c7
#define mmDMIF_ARBITRATION_CONTROL_BASE_IDX 2
#define mmPIPE0_ARBITRATION_CONTROL3 0x00c8
#define mmPIPE0_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE1_ARBITRATION_CONTROL3 0x00c9
#define mmPIPE1_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE2_ARBITRATION_CONTROL3 0x00ca
#define mmPIPE2_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE3_ARBITRATION_CONTROL3 0x00cb
#define mmPIPE3_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE4_ARBITRATION_CONTROL3 0x00cc
#define mmPIPE4_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE5_ARBITRATION_CONTROL3 0x00cd
#define mmPIPE5_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmDMIF_P_VMID 0x00ce
#define mmDMIF_P_VMID_BASE_IDX 2
#define mmDMIF_ADDR_CALC 0x00d1
#define mmDMIF_ADDR_CALC_BASE_IDX 2
#define mmDMIF_STATUS2 0x00d2
#define mmDMIF_STATUS2_BASE_IDX 2
#define mmPIPE0_MAX_REQUESTS 0x00d3
#define mmPIPE0_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE1_MAX_REQUESTS 0x00d4
#define mmPIPE1_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE2_MAX_REQUESTS 0x00d5
#define mmPIPE2_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE3_MAX_REQUESTS 0x00d6
#define mmPIPE3_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE4_MAX_REQUESTS 0x00d7
#define mmPIPE4_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE5_MAX_REQUESTS 0x00d8
#define mmPIPE5_MAX_REQUESTS_BASE_IDX 2
#define mmLOW_POWER_TILING_CONTROL 0x00d9
#define mmLOW_POWER_TILING_CONTROL_BASE_IDX 2
#define mmMCIF_CONTROL 0x00da
#define mmMCIF_CONTROL_BASE_IDX 2
#define mmMCIF_WRITE_COMBINE_CONTROL 0x00db
#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x00de
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmCC_DC_PIPE_DIS 0x00e0
#define mmCC_DC_PIPE_DIS_BASE_IDX 2
#define mmSMU_WM_CONTROL 0x00e1
#define mmSMU_WM_CONTROL_BASE_IDX 2
#define mmRBBMIF_TIMEOUT 0x00e2
#define mmRBBMIF_TIMEOUT_BASE_IDX 2
#define mmRBBMIF_STATUS 0x00e3
#define mmRBBMIF_STATUS_BASE_IDX 2
#define mmRBBMIF_TIMEOUT_DIS 0x00e4
#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
#define mmDCI_MEM_PWR_STATUS 0x00e5
#define mmDCI_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCI_MEM_PWR_STATUS2 0x00e6
#define mmDCI_MEM_PWR_STATUS2_BASE_IDX 2
#define mmDCI_CLK_CNTL 0x00e7
#define mmDCI_CLK_CNTL_BASE_IDX 2
#define mmDCI_CLK_CNTL2 0x00e8
#define mmDCI_CLK_CNTL2_BASE_IDX 2
#define mmDCI_MEM_PWR_CNTL 0x00e9
#define mmDCI_MEM_PWR_CNTL_BASE_IDX 2
#define mmDCI_MEM_PWR_CNTL2 0x00ea
#define mmDCI_MEM_PWR_CNTL2_BASE_IDX 2
#define mmDCI_MEM_PWR_CNTL3 0x00eb
#define mmDCI_MEM_PWR_CNTL3_BASE_IDX 2
#define mmPIPE0_DMIF_BUFFER_CONTROL 0x00ef
#define mmPIPE0_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmPIPE1_DMIF_BUFFER_CONTROL 0x00f0
#define mmPIPE1_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmPIPE2_DMIF_BUFFER_CONTROL 0x00f1
#define mmPIPE2_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmPIPE3_DMIF_BUFFER_CONTROL 0x00f2
#define mmPIPE3_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmPIPE4_DMIF_BUFFER_CONTROL 0x00f3
#define mmPIPE4_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmPIPE5_DMIF_BUFFER_CONTROL 0x00f4
#define mmPIPE5_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmRBBMIF_STATUS_FLAG 0x00f5
#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
#define mmDCI_SOFT_RESET 0x00f6
#define mmDCI_SOFT_RESET_BASE_IDX 2
#define mmDMIF_URG_OVERRIDE 0x00f7
#define mmDMIF_URG_OVERRIDE_BASE_IDX 2
#define mmPIPE6_ARBITRATION_CONTROL3 0x00f8
#define mmPIPE6_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE7_ARBITRATION_CONTROL3 0x00f9
#define mmPIPE7_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE6_MAX_REQUESTS 0x00fa
#define mmPIPE6_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE7_MAX_REQUESTS 0x00fb
#define mmPIPE7_MAX_REQUESTS_BASE_IDX 2
#define mmDVMM_REG_RD_STATUS 0x00fc
#define mmDVMM_REG_RD_STATUS_BASE_IDX 2
#define mmDVMM_REG_RD_DATA 0x00fd
#define mmDVMM_REG_RD_DATA_BASE_IDX 2
#define mmDVMM_PTE_REQ 0x00fe
#define mmDVMM_PTE_REQ_BASE_IDX 2
#define mmDVMM_CNTL 0x00ff
#define mmDVMM_CNTL_BASE_IDX 2
#define mmDVMM_FAULT_STATUS 0x0100
#define mmDVMM_FAULT_STATUS_BASE_IDX 2
#define mmDVMM_FAULT_ADDR 0x0101
#define mmDVMM_FAULT_ADDR_BASE_IDX 2
#define mmFMON_CTRL 0x0102
#define mmFMON_CTRL_BASE_IDX 2
#define mmDVMM_PTE_PGMEM_CONTROL 0x0103
#define mmDVMM_PTE_PGMEM_CONTROL_BASE_IDX 2
#define mmDVMM_PTE_PGMEM_STATE 0x0104
#define mmDVMM_PTE_PGMEM_STATE_BASE_IDX 2
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x0105
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0106
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER 0x0107
#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER 0x0108
#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmDCI_MEM_PWR_CNTL4 0x0109
#define mmDCI_MEM_PWR_CNTL4_BASE_IDX 2
#define mmMCIF_WB_MISC_CTRL 0x010a
#define mmMCIF_WB_MISC_CTRL_BASE_IDX 2
#define mmDCI_MEM_PWR_STATUS3 0x010b
#define mmDCI_MEM_PWR_STATUS3_BASE_IDX 2
#define mmDMIF_CURSOR_CONTROL 0x010c
#define mmDMIF_CURSOR_CONTROL_BASE_IDX 2
#define mmDMIF_CURSOR_MEM_CONTROL 0x010d
#define mmDMIF_CURSOR_MEM_CONTROL_BASE_IDX 2
#define mmDCHUB_FB_LOCATION 0x0126
#define mmDCHUB_FB_LOCATION_BASE_IDX 2
#define mmDCHUB_FB_OFFSET 0x0127
#define mmDCHUB_FB_OFFSET_BASE_IDX 2
#define mmDCHUB_AGP_BASE 0x0128
#define mmDCHUB_AGP_BASE_BASE_IDX 2
#define mmDCHUB_AGP_BOT 0x0129
#define mmDCHUB_AGP_BOT_BASE_IDX 2
#define mmDCHUB_AGP_TOP 0x012a
#define mmDCHUB_AGP_TOP_BASE_IDX 2
#define mmDCHUB_DRAM_APER_BASE 0x012b
#define mmDCHUB_DRAM_APER_BASE_BASE_IDX 2
#define mmDCHUB_DRAM_APER_DEF 0x012c
#define mmDCHUB_DRAM_APER_DEF_BASE_IDX 2
#define mmDCHUB_DRAM_APER_TOP 0x012d
#define mmDCHUB_DRAM_APER_TOP_BASE_IDX 2
#define mmDCHUB_CONTROL_STATUS 0x012e
#define mmDCHUB_CONTROL_STATUS_BASE_IDX 2
#define mmWB_ENABLE 0x0212
#define mmWB_ENABLE_BASE_IDX 2
#define mmWB_EC_CONFIG 0x0213
#define mmWB_EC_CONFIG_BASE_IDX 2
#define mmCNV_MODE 0x0214
#define mmCNV_MODE_BASE_IDX 2
#define mmCNV_WINDOW_START 0x0215
#define mmCNV_WINDOW_START_BASE_IDX 2
#define mmCNV_WINDOW_SIZE 0x0216
#define mmCNV_WINDOW_SIZE_BASE_IDX 2
#define mmCNV_UPDATE 0x0217
#define mmCNV_UPDATE_BASE_IDX 2
#define mmCNV_SOURCE_SIZE 0x0218
#define mmCNV_SOURCE_SIZE_BASE_IDX 2
#define mmCNV_CSC_CONTROL 0x0219
#define mmCNV_CSC_CONTROL_BASE_IDX 2
#define mmCNV_CSC_C11_C12 0x021a
#define mmCNV_CSC_C11_C12_BASE_IDX 2
#define mmCNV_CSC_C13_C14 0x021b
#define mmCNV_CSC_C13_C14_BASE_IDX 2
#define mmCNV_CSC_C21_C22 0x021c
#define mmCNV_CSC_C21_C22_BASE_IDX 2
#define mmCNV_CSC_C23_C24 0x021d
#define mmCNV_CSC_C23_C24_BASE_IDX 2
#define mmCNV_CSC_C31_C32 0x021e
#define mmCNV_CSC_C31_C32_BASE_IDX 2
#define mmCNV_CSC_C33_C34 0x021f
#define mmCNV_CSC_C33_C34_BASE_IDX 2
#define mmCNV_CSC_ROUND_OFFSET_R 0x0220
#define mmCNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
#define mmCNV_CSC_ROUND_OFFSET_G 0x0221
#define mmCNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
#define mmCNV_CSC_ROUND_OFFSET_B 0x0222
#define mmCNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
#define mmCNV_CSC_CLAMP_R 0x0223
#define mmCNV_CSC_CLAMP_R_BASE_IDX 2
#define mmCNV_CSC_CLAMP_G 0x0224
#define mmCNV_CSC_CLAMP_G_BASE_IDX 2
#define mmCNV_CSC_CLAMP_B 0x0225
#define mmCNV_CSC_CLAMP_B_BASE_IDX 2
#define mmCNV_TEST_CNTL 0x0226
#define mmCNV_TEST_CNTL_BASE_IDX 2
#define mmCNV_TEST_CRC_RED 0x0227
#define mmCNV_TEST_CRC_RED_BASE_IDX 2
#define mmCNV_TEST_CRC_GREEN 0x0228
#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2
#define mmCNV_TEST_CRC_BLUE 0x0229
#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2
#define mmCNV_INPUT_SELECT 0x022d
#define mmCNV_INPUT_SELECT_BASE_IDX 2
#define mmWB_SOFT_RESET 0x0230
#define mmWB_SOFT_RESET_BASE_IDX 2
#define mmWB_WARM_UP_MODE_CTL1 0x0231
#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2
#define mmWB_WARM_UP_MODE_CTL2 0x0232
#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2
#define mmWBSCL_COEF_RAM_SELECT 0x0242
#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2
#define mmWBSCL_COEF_RAM_TAP_DATA 0x0243
#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmWBSCL_MODE 0x0244
#define mmWBSCL_MODE_BASE_IDX 2
#define mmWBSCL_TAP_CONTROL 0x0245
#define mmWBSCL_TAP_CONTROL_BASE_IDX 2
#define mmWBSCL_DEST_SIZE 0x0246
#define mmWBSCL_DEST_SIZE_BASE_IDX 2
#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x0247
#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0248
#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0249
#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x024a
#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x024b
#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x024c
#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
#define mmWBSCL_ROUND_OFFSET 0x024d
#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2
#define mmWBSCL_CLAMP 0x024e
#define mmWBSCL_CLAMP_BASE_IDX 2
#define mmWBSCL_OVERFLOW_STATUS 0x024f
#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2
#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0250
#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0251
#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
#define mmWBSCL_TEST_CNTL 0x0252
#define mmWBSCL_TEST_CNTL_BASE_IDX 2
#define mmWBSCL_TEST_CRC_RED 0x0253
#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2
#define mmWBSCL_TEST_CRC_GREEN 0x0254
#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2
#define mmWBSCL_TEST_CRC_BLUE 0x0255
#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2
#define mmWBSCL_BACKPRESSURE_CNT_EN 0x0256
#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
#define mmWB_MCIF_BACKPRESSURE_CNT 0x0257
#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
#define mmWBSCL_RAM_SHUTDOWN 0x025a
#define mmWBSCL_RAM_SHUTDOWN_BASE_IDX 2
#define mmDMCU_CTRL 0x03b6
#define mmDMCU_CTRL_BASE_IDX 2
#define mmDMCU_STATUS 0x03b7
#define mmDMCU_STATUS_BASE_IDX 2
#define mmDMCU_PC_START_ADDR 0x03b8
#define mmDMCU_PC_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_START_ADDR 0x03b9
#define mmDMCU_FW_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_END_ADDR 0x03ba
#define mmDMCU_FW_END_ADDR_BASE_IDX 2
#define mmDMCU_FW_ISR_START_ADDR 0x03bb
#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_CS_HI 0x03bc
#define mmDMCU_FW_CS_HI_BASE_IDX 2
#define mmDMCU_FW_CS_LO 0x03bd
#define mmDMCU_FW_CS_LO_BASE_IDX 2
#define mmDMCU_RAM_ACCESS_CTRL 0x03be
#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_WR_CTRL 0x03bf
#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_WR_DATA 0x03c0
#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
#define mmDMCU_ERAM_RD_CTRL 0x03c1
#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_RD_DATA 0x03c2
#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
#define mmDMCU_IRAM_WR_CTRL 0x03c3
#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
#define mmDMCU_IRAM_WR_DATA 0x03c4
#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
#define mmDMCU_IRAM_RD_CTRL 0x03c5
#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
#define mmDMCU_IRAM_RD_DATA 0x03c6
#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
#define mmDMCU_EVENT_TRIGGER 0x03c7
#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
#define mmDMCU_UC_INTERNAL_INT_STATUS 0x03c8
#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x03c9
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS 0x03ca
#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x03cb
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x03cc
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x03cd
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
#define mmDC_DMCU_SCRATCH 0x03ce
#define mmDC_DMCU_SCRATCH_BASE_IDX 2
#define mmDMCU_INT_CNT 0x03cf
#define mmDMCU_INT_CNT_BASE_IDX 2
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x03d0
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
#define mmDMCU_UC_CLK_GATING_CNTL 0x03d1
#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG1 0x03d2
#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG2 0x03d3
#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG3 0x03d4
#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
#define mmMASTER_COMM_CMD_REG 0x03d5
#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
#define mmMASTER_COMM_CNTL_REG 0x03d6
#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG1 0x03d7
#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG2 0x03d8
#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG3 0x03d9
#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
#define mmSLAVE_COMM_CMD_REG 0x03da
#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
#define mmSLAVE_COMM_CNTL_REG 0x03db
#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x03de
#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
#define mmBL1_PWM_USER_LEVEL 0x03df
#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2
#define mmBL1_PWM_TARGET_ABM_LEVEL 0x03e0
#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x03e1
#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x03e2
#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x03e3
#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
#define mmBL1_PWM_ABM_CNTL 0x03e4
#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2
#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x03e5
#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
#define mmBL1_PWM_GRP2_REG_LOCK 0x03e6
#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x03e7
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x03e8
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS_1 0x03e9
#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x03ea
#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x03eb
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x03ec
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
#define mmDC_ABM1_CNTL 0x03ee
#define mmDC_ABM1_CNTL_BASE_IDX 2
#define mmDC_ABM1_IPCSC_COEFF_SEL 0x03ef
#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x03f0
#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x03f1
#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x03f2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x03f3
#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x03f4
#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
#define mmDC_ABM1_ACE_THRES_12 0x03f5
#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2
#define mmDC_ABM1_ACE_THRES_34 0x03f6
#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2
#define mmDC_ABM1_ACE_CNTL_MISC 0x03f7
#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x03f8
#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x03f9
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x03fa
#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x03fb
#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x03fc
#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x03fd
#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x0400
#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
#define mmDC_ABM1_HG_MISC_CTRL 0x0401
#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2
#define mmDC_ABM1_LS_SUM_OF_LUMA 0x0402
#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x0403
#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0404
#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
#define mmDC_ABM1_LS_PIXEL_COUNT 0x0405
#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x0406
#define mmDC_ABM1_LS_OVR_SCAN_BIN_BASE_IDX 2
#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0407
#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0408
#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0409
#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
#define mmDC_ABM1_HG_SAMPLE_RATE 0x040a
#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
#define mmDC_ABM1_LS_SAMPLE_RATE 0x040b
#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x040c
#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x040d
#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x040e
#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x040f
#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0410
#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_1 0x0411
#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_2 0x0412
#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_3 0x0413
#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_4 0x0414
#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_5 0x0415
#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_6 0x0416
#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_7 0x0417
#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_8 0x0418
#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_9 0x0419
#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_10 0x041a
#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_11 0x041b
#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_12 0x041c
#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_13 0x041d
#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_14 0x041e
#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_15 0x041f
#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_16 0x0420
#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_17 0x0421
#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_18 0x0422
#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_19 0x0423
#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_20 0x0424
#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_21 0x0425
#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_22 0x0426
#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_23 0x0427
#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_24 0x0428
#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0429
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x042a
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x042b
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x042c
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x042d
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x042e
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x042f
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0430
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0431
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x0451
#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_BASE_IDX 2
#define mmDC_ABM1_BL_MASTER_LOCK 0x0452
#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x04bc
#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO 0x04bd
#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO_CONTROL 0x04be
#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
#define mmAZALIA_SOCCLK_CONTROL 0x04bf
#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x04c0
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
#define mmAZALIA_DATA_DMA_CONTROL 0x04c1
#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_BDL_DMA_CONTROL 0x04c2
#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_RIRB_AND_DP_CONTROL 0x04c3
#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
#define mmAZALIA_CORB_DMA_CONTROL 0x04c4
#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x04cb
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x04cc
#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
#define mmAZALIA_GLOBAL_CAPABILITIES 0x04cd
#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x04ce
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x04cf
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x04d0
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL0 0x04d3
#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL1 0x04d4
#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL2 0x04d5
#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL3 0x04d6
#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_RESULT 0x04d7
#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL0 0x04d8
#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL1 0x04d9
#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL2 0x04da
#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL3 0x04db
#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_RESULT 0x04dc
#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL0 0x04dd
#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL1 0x04de
#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL2 0x04df
#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL3 0x04e0
#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_CRC0_RESULT 0x04e1
#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL0 0x04e2
#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL1 0x04e3
#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL2 0x04e4
#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL3 0x04e5
#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_CRC1_RESULT 0x04e6
#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_MEM_PWR_CTRL 0x04e8
#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
#define mmAZALIA_MEM_PWR_STATUS 0x04e9
#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0500
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0501
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0502
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0503
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x0504
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x0505
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x0506
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x0507
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x0508
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x0509
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x050a
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x050b
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x050c
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x050d
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x050f
#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0510
#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0511
#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0512
#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0513
#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x0514
#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x0515
#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x0516
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0517
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
#define mmDAC_ENABLE 0x155a
#define mmDAC_ENABLE_BASE_IDX 2
#define mmDAC_SOURCE_SELECT 0x155b
#define mmDAC_SOURCE_SELECT_BASE_IDX 2
#define mmDAC_CRC_EN 0x155c
#define mmDAC_CRC_EN_BASE_IDX 2
#define mmDAC_CRC_CONTROL 0x155d
#define mmDAC_CRC_CONTROL_BASE_IDX 2
#define mmDAC_CRC_SIG_RGB_MASK 0x155e
#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2
#define mmDAC_CRC_SIG_CONTROL_MASK 0x155f
#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2
#define mmDAC_CRC_SIG_RGB 0x1560
#define mmDAC_CRC_SIG_RGB_BASE_IDX 2
#define mmDAC_CRC_SIG_CONTROL 0x1561
#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2
#define mmDAC_SYNC_TRISTATE_CONTROL 0x1562
#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2
#define mmDAC_STEREOSYNC_SELECT 0x1563
#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2
#define mmDAC_AUTODETECT_CONTROL 0x1564
#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2
#define mmDAC_AUTODETECT_CONTROL2 0x1565
#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2
#define mmDAC_AUTODETECT_CONTROL3 0x1566
#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2
#define mmDAC_AUTODETECT_STATUS 0x1567
#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2
#define mmDAC_AUTODETECT_INT_CONTROL 0x1568
#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2
#define mmDAC_FORCE_OUTPUT_CNTL 0x1569
#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2
#define mmDAC_FORCE_DATA 0x156a
#define mmDAC_FORCE_DATA_BASE_IDX 2
#define mmDAC_POWERDOWN 0x156b
#define mmDAC_POWERDOWN_BASE_IDX 2
#define mmDAC_CONTROL 0x156c
#define mmDAC_CONTROL_BASE_IDX 2
#define mmDAC_COMPARATOR_ENABLE 0x156d
#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2
#define mmDAC_COMPARATOR_OUTPUT 0x156e
#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2
#define mmDAC_PWR_CNTL 0x156f
#define mmDAC_PWR_CNTL_BASE_IDX 2
#define mmDAC_DFT_CONFIG 0x1570
#define mmDAC_DFT_CONFIG_BASE_IDX 2
#define mmDAC_FIFO_STATUS 0x1571
#define mmDAC_FIFO_STATUS_BASE_IDX 2
#define mmDC_I2C_CONTROL 0x1584
#define mmDC_I2C_CONTROL_BASE_IDX 2
#define mmDC_I2C_ARBITRATION 0x1585
#define mmDC_I2C_ARBITRATION_BASE_IDX 2
#define mmDC_I2C_INTERRUPT_CONTROL 0x1586
#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDC_I2C_SW_STATUS 0x1587
#define mmDC_I2C_SW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC1_HW_STATUS 0x1588
#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC2_HW_STATUS 0x1589
#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC3_HW_STATUS 0x158a
#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC4_HW_STATUS 0x158b
#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC5_HW_STATUS 0x158c
#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC6_HW_STATUS 0x158d
#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC1_SPEED 0x158e
#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC1_SETUP 0x158f
#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC2_SPEED 0x1590
#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC2_SETUP 0x1591
#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC3_SPEED 0x1592
#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC3_SETUP 0x1593
#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC4_SPEED 0x1594
#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC4_SETUP 0x1595
#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC5_SPEED 0x1596
#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC5_SETUP 0x1597
#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC6_SPEED 0x1598
#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC6_SETUP 0x1599
#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
#define mmDC_I2C_TRANSACTION0 0x159a
#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
#define mmDC_I2C_TRANSACTION1 0x159b
#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
#define mmDC_I2C_TRANSACTION2 0x159c
#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
#define mmDC_I2C_TRANSACTION3 0x159d
#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
#define mmDC_I2C_DATA 0x159e
#define mmDC_I2C_DATA_BASE_IDX 2
#define mmDC_I2C_DDCVGA_HW_STATUS 0x159f
#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDCVGA_SPEED 0x15a0
#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2
#define mmDC_I2C_DDCVGA_SETUP 0x15a1
#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
#define mmDC_I2C_EDID_DETECT_CTRL 0x15a2
#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x15a3
#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
#define mmGENERIC_I2C_CONTROL 0x15a4
#define mmGENERIC_I2C_CONTROL_BASE_IDX 2
#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x15a5
#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
#define mmGENERIC_I2C_STATUS 0x15a6
#define mmGENERIC_I2C_STATUS_BASE_IDX 2
#define mmGENERIC_I2C_SPEED 0x15a7
#define mmGENERIC_I2C_SPEED_BASE_IDX 2
#define mmGENERIC_I2C_SETUP 0x15a8
#define mmGENERIC_I2C_SETUP_BASE_IDX 2
#define mmGENERIC_I2C_TRANSACTION 0x15a9
#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2
#define mmGENERIC_I2C_DATA 0x15aa
#define mmGENERIC_I2C_DATA_BASE_IDX 2
#define mmGENERIC_I2C_PIN_SELECTION 0x15ab
#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2
#define mmDCO_SCRATCH0 0x15b6
#define mmDCO_SCRATCH0_BASE_IDX 2
#define mmDCO_SCRATCH1 0x15b7
#define mmDCO_SCRATCH1_BASE_IDX 2
#define mmDCO_SCRATCH2 0x15b8
#define mmDCO_SCRATCH2_BASE_IDX 2
#define mmDCO_SCRATCH3 0x15b9
#define mmDCO_SCRATCH3_BASE_IDX 2
#define mmDCO_SCRATCH4 0x15ba
#define mmDCO_SCRATCH4_BASE_IDX 2
#define mmDCO_SCRATCH5 0x15bb
#define mmDCO_SCRATCH5_BASE_IDX 2
#define mmDCO_SCRATCH6 0x15bc
#define mmDCO_SCRATCH6_BASE_IDX 2
#define mmDCO_SCRATCH7 0x15bd
#define mmDCO_SCRATCH7_BASE_IDX 2
#define mmDCE_VCE_CONTROL 0x15be
#define mmDCE_VCE_CONTROL_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS 0x15bf
#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x15c0
#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x15c1
#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x15c2
#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x15c3
#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x15c4
#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x15c5
#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x15c6
#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x15c7
#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x15c8
#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
#define mmDCO_MEM_PWR_STATUS 0x15c9
#define mmDCO_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCO_MEM_PWR_CTRL 0x15ca
#define mmDCO_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCO_MEM_PWR_CTRL2 0x15cb
#define mmDCO_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDCO_CLK_CNTL 0x15cc
#define mmDCO_CLK_CNTL_BASE_IDX 2
#define mmDCO_POWER_MANAGEMENT_CNTL 0x15d0
#define mmDCO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
#define mmDIG_SOFT_RESET_2 0x15d2
#define mmDIG_SOFT_RESET_2_BASE_IDX 2
#define mmDCO_STEREOSYNC_SEL 0x15d6
#define mmDCO_STEREOSYNC_SEL_BASE_IDX 2
#define mmDCO_SOFT_RESET 0x15d9
#define mmDCO_SOFT_RESET_BASE_IDX 2
#define mmDIG_SOFT_RESET 0x15da
#define mmDIG_SOFT_RESET_BASE_IDX 2
#define mmDCO_MEM_PWR_STATUS1 0x15dc
#define mmDCO_MEM_PWR_STATUS1_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x15dd
#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
#define mmDCO_CLK_CNTL2 0x15de
#define mmDCO_CLK_CNTL2_BASE_IDX 2
#define mmDCO_CLK_CNTL3 0x15df
#define mmDCO_CLK_CNTL3_BASE_IDX 2
#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0x15eb
#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
#define mmDCO_PSP_INTERRUPT_STATUS 0x15ec
#define mmDCO_PSP_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCO_PSP_INTERRUPT_CLEAR 0x15ed
#define mmDCO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
#define mmDCO_GENERIC_INTERRUPT_MESSAGE 0x15ee
#define mmDCO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
#define mmDCO_GENERIC_INTERRUPT_CLEAR 0x15ef
#define mmDCO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
#define mmFMT_MEMORY0_CONTROL 0x15f0
#define mmFMT_MEMORY0_CONTROL_BASE_IDX 2
#define mmFMT_MEMORY1_CONTROL 0x15f1
#define mmFMT_MEMORY1_CONTROL_BASE_IDX 2
#define mmFMT_MEMORY2_CONTROL 0x15f2
#define mmFMT_MEMORY2_CONTROL_BASE_IDX 2
#define mmFMT_MEMORY3_CONTROL 0x15f3
#define mmFMT_MEMORY3_CONTROL_BASE_IDX 2
#define mmFMT_MEMORY4_CONTROL 0x15f4
#define mmFMT_MEMORY4_CONTROL_BASE_IDX 2
#define mmFMT_MEMORY5_CONTROL 0x15f5
#define mmFMT_MEMORY5_CONTROL_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x15f6
#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
#define mmDC_GENERICA 0x207e
#define mmDC_GENERICA_BASE_IDX 2
#define mmDC_GENERICB 0x207f
#define mmDC_GENERICB_BASE_IDX 2
#define mmDC_PAD_EXTERN_SIG 0x2080
#define mmDC_PAD_EXTERN_SIG_BASE_IDX 2
#define mmDC_REF_CLK_CNTL 0x2081
#define mmDC_REF_CLK_CNTL_BASE_IDX 2
#define mmDC_GPIO_DEBUG 0x2082
#define mmDC_GPIO_DEBUG_BASE_IDX 2
#define mmUNIPHYA_LINK_CNTL 0x2083
#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x2084
#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYB_LINK_CNTL 0x2085
#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2086
#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYC_LINK_CNTL 0x2087
#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2088
#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYD_LINK_CNTL 0x2089
#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x208a
#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYE_LINK_CNTL 0x208b
#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x208c
#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYF_LINK_CNTL 0x208d
#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x208e
#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYG_LINK_CNTL 0x208f
#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x2090
#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmDCIO_WRCMD_DELAY 0x2094
#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
#define mmDC_PINSTRAPS 0x2096
#define mmDC_PINSTRAPS_BASE_IDX 2
#define mmCC_DC_MISC_STRAPS 0x2097
#define mmCC_DC_MISC_STRAPS_BASE_IDX 2
#define mmDC_DVODATA_CONFIG 0x2098
#define mmDC_DVODATA_CONFIG_BASE_IDX 2
#define mmLVTMA_PWRSEQ_CNTL 0x2099
#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
#define mmLVTMA_PWRSEQ_STATE 0x209a
#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
#define mmLVTMA_PWRSEQ_REF_DIV 0x209b
#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
#define mmLVTMA_PWRSEQ_DELAY1 0x209c
#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
#define mmLVTMA_PWRSEQ_DELAY2 0x209d
#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
#define mmBL_PWM_CNTL 0x209e
#define mmBL_PWM_CNTL_BASE_IDX 2
#define mmBL_PWM_CNTL2 0x209f
#define mmBL_PWM_CNTL2_BASE_IDX 2
#define mmBL_PWM_PERIOD_CNTL 0x20a0
#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
#define mmBL_PWM_GRP1_REG_LOCK 0x20a1
#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
#define mmDCIO_GSL_GENLK_PAD_CNTL 0x20a2
#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x20a3
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
#define mmDCIO_GSL0_CNTL 0x20a4
#define mmDCIO_GSL0_CNTL_BASE_IDX 2
#define mmDCIO_GSL1_CNTL 0x20a5
#define mmDCIO_GSL1_CNTL_BASE_IDX 2
#define mmDCIO_GSL2_CNTL 0x20a6
#define mmDCIO_GSL2_CNTL_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x20a7
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x20a8
#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_BASE_IDX 2
#define mmDC_GPU_TIMER_READ 0x20a9
#define mmDC_GPU_TIMER_READ_BASE_IDX 2
#define mmDC_GPU_TIMER_READ_CNTL 0x20aa
#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
#define mmDCIO_CLOCK_CNTL 0x20ab
#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x20ae
#define mmDCO_DCFE_EXT_VSYNC_CNTL_BASE_IDX 2
#define mmDCIO_SOFT_RESET 0x20b4
#define mmDCIO_SOFT_RESET_BASE_IDX 2
#define mmDCIO_DPHY_SEL 0x20b5
#define mmDCIO_DPHY_SEL_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKA 0x20b6
#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKB 0x20b7
#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PERIOD 0x20b8
#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2
#define mmAUXP_IMPCAL 0x20b9
#define mmAUXP_IMPCAL_BASE_IDX 2
#define mmAUXN_IMPCAL 0x20ba
#define mmAUXN_IMPCAL_BASE_IDX 2
#define mmDCIO_IMPCAL_CNTL 0x20bb
#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PSW_AB 0x20bc
#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKC 0x20bd
#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKD 0x20be
#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2
#define mmDCIO_IMPCAL_CNTL_CD 0x20bf
#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PSW_CD 0x20c0
#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKE 0x20c1
#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKF 0x20c2
#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2
#define mmDCIO_IMPCAL_CNTL_EF 0x20c3
#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PSW_EF 0x20c4
#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2
#define mmUNIPHYLPA_LINK_CNTL 0x20c5
#define mmUNIPHYLPA_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYLPB_LINK_CNTL 0x20c6
#define mmUNIPHYLPB_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x20c7
#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x20c8
#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmDCIO_DPCS_TX_INTERRUPT 0x20c9
#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2
#define mmDCIO_DPCS_RX_INTERRUPT 0x20ca
#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2
#define mmDCIO_SEMAPHORE0 0x20cb
#define mmDCIO_SEMAPHORE0_BASE_IDX 2
#define mmDCIO_SEMAPHORE1 0x20cc
#define mmDCIO_SEMAPHORE1_BASE_IDX 2
#define mmDCIO_SEMAPHORE2 0x20cd
#define mmDCIO_SEMAPHORE2_BASE_IDX 2
#define mmDCIO_SEMAPHORE3 0x20ce
#define mmDCIO_SEMAPHORE3_BASE_IDX 2
#define mmDCIO_SEMAPHORE4 0x20cf
#define mmDCIO_SEMAPHORE4_BASE_IDX 2
#define mmDCIO_SEMAPHORE5 0x20d0
#define mmDCIO_SEMAPHORE5_BASE_IDX 2
#define mmDCIO_SEMAPHORE6 0x20d1
#define mmDCIO_SEMAPHORE6_BASE_IDX 2
#define mmDCIO_SEMAPHORE7 0x20d2
#define mmDCIO_SEMAPHORE7_BASE_IDX 2
#define mmDC_GPIO_GENERIC_MASK 0x20de
#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
#define mmDC_GPIO_GENERIC_A 0x20df
#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
#define mmDC_GPIO_GENERIC_EN 0x20e0
#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
#define mmDC_GPIO_GENERIC_Y 0x20e1
#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
#define mmDC_GPIO_DVODATA_MASK 0x20e2
#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2
#define mmDC_GPIO_DVODATA_A 0x20e3
#define mmDC_GPIO_DVODATA_A_BASE_IDX 2
#define mmDC_GPIO_DVODATA_EN 0x20e4
#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2
#define mmDC_GPIO_DVODATA_Y 0x20e5
#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2
#define mmDC_GPIO_DDC1_MASK 0x20e6
#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC1_A 0x20e7
#define mmDC_GPIO_DDC1_A_BASE_IDX 2
#define mmDC_GPIO_DDC1_EN 0x20e8
#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
#define mmDC_GPIO_DDC1_Y 0x20e9
#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
#define mmDC_GPIO_DDC2_MASK 0x20ea
#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC2_A 0x20eb
#define mmDC_GPIO_DDC2_A_BASE_IDX 2
#define mmDC_GPIO_DDC2_EN 0x20ec
#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
#define mmDC_GPIO_DDC2_Y 0x20ed
#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
#define mmDC_GPIO_DDC3_MASK 0x20ee
#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC3_A 0x20ef
#define mmDC_GPIO_DDC3_A_BASE_IDX 2
#define mmDC_GPIO_DDC3_EN 0x20f0
#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
#define mmDC_GPIO_DDC3_Y 0x20f1
#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
#define mmDC_GPIO_DDC4_MASK 0x20f2
#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC4_A 0x20f3
#define mmDC_GPIO_DDC4_A_BASE_IDX 2
#define mmDC_GPIO_DDC4_EN 0x20f4
#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
#define mmDC_GPIO_DDC4_Y 0x20f5
#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
#define mmDC_GPIO_DDC5_MASK 0x20f6
#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC5_A 0x20f7
#define mmDC_GPIO_DDC5_A_BASE_IDX 2
#define mmDC_GPIO_DDC5_EN 0x20f8
#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
#define mmDC_GPIO_DDC5_Y 0x20f9
#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
#define mmDC_GPIO_DDC6_MASK 0x20fa
#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC6_A 0x20fb
#define mmDC_GPIO_DDC6_A_BASE_IDX 2
#define mmDC_GPIO_DDC6_EN 0x20fc
#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
#define mmDC_GPIO_DDC6_Y 0x20fd
#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_MASK 0x20fe
#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_A 0x20ff
#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_EN 0x2100
#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_Y 0x2101
#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
#define mmDC_GPIO_SYNCA_MASK 0x2102
#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2
#define mmDC_GPIO_SYNCA_A 0x2103
#define mmDC_GPIO_SYNCA_A_BASE_IDX 2
#define mmDC_GPIO_SYNCA_EN 0x2104
#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2
#define mmDC_GPIO_SYNCA_Y 0x2105
#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2
#define mmDC_GPIO_GENLK_MASK 0x2106
#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
#define mmDC_GPIO_GENLK_A 0x2107
#define mmDC_GPIO_GENLK_A_BASE_IDX 2
#define mmDC_GPIO_GENLK_EN 0x2108
#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
#define mmDC_GPIO_GENLK_Y 0x2109
#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
#define mmDC_GPIO_HPD_MASK 0x210a
#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
#define mmDC_GPIO_HPD_A 0x210b
#define mmDC_GPIO_HPD_A_BASE_IDX 2
#define mmDC_GPIO_HPD_EN 0x210c
#define mmDC_GPIO_HPD_EN_BASE_IDX 2
#define mmDC_GPIO_HPD_Y 0x210d
#define mmDC_GPIO_HPD_Y_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_MASK 0x210e
#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_A 0x210f
#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_EN 0x2110
#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_Y 0x2111
#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
#define mmDC_GPIO_PAD_STRENGTH_1 0x2112
#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
#define mmDC_GPIO_PAD_STRENGTH_2 0x2113
#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
#define mmPHY_AUX_CNTL 0x2115
#define mmPHY_AUX_CNTL_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_MASK 0x2116
#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_A 0x2117
#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_EN 0x2118
#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_Y 0x2119
#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_STRENGTH 0x211a
#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2
#define mmDVO_STRENGTH_CONTROL 0x211b
#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2
#define mmDVO_VREF_CONTROL 0x211c
#define mmDVO_VREF_CONTROL_BASE_IDX 2
#define mmDVO_SKEW_ADJUST 0x211d
#define mmDVO_SKEW_ADJUST_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_MASK 0x2126
#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_A 0x2127
#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_EN 0x2128
#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_Y 0x2129
#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x212a
#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2
#define mmDC_GPIO_TX12_EN 0x212b
#define mmDC_GPIO_TX12_EN_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_0 0x212c
#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_1 0x212d
#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_2 0x212e
#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
#define mmDC_GPIO_RXEN 0x212f
#define mmDC_GPIO_RXEN_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_3 0x2130
#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_4 0x2131
#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_5 0x2132
#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2
#define mmAUXI2C_PAD_ALL_PWR_OK 0x2133
#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
#define mmDC_GPIO_PULLUPEN 0x2134
#define mmDC_GPIO_PULLUPEN_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_6 0x2135
#define mmDC_GPIO_AUX_CTRL_6_BASE_IDX 2
#define mmBPHYC_DAC_MACRO_CNTL 0x2136
#define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED0 0x2136
#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x2137
#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED1 0x2137
#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED2 0x2138
#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED3 0x2139
#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDISP_DSI_DUAL_CTRL 0x277e
#define mmDISP_DSI_DUAL_CTRL_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED0 0x283e
#define mmDPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED1 0x283f
#define mmDPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED2 0x2840
#define mmDPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED3 0x2841
#define mmDPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED4 0x2842
#define mmDPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED5 0x2843
#define mmDPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED6 0x2844
#define mmDPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED7 0x2845
#define mmDPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED8 0x2846
#define mmDPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED9 0x2847
#define mmDPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED10 0x2848
#define mmDPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED11 0x2849
#define mmDPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED12 0x284a
#define mmDPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED13 0x284b
#define mmDPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED14 0x284c
#define mmDPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED15 0x284d
#define mmDPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED16 0x284e
#define mmDPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED17 0x284f
#define mmDPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED18 0x2850
#define mmDPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED19 0x2851
#define mmDPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED20 0x2852
#define mmDPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED21 0x2853
#define mmDPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED22 0x2854
#define mmDPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED23 0x2855
#define mmDPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED24 0x2856
#define mmDPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED25 0x2857
#define mmDPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED26 0x2858
#define mmDPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED27 0x2859
#define mmDPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED28 0x285a
#define mmDPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED29 0x285b
#define mmDPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED30 0x285c
#define mmDPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED31 0x285d
#define mmDPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED32 0x285e
#define mmDPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED33 0x285f
#define mmDPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED34 0x2860
#define mmDPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED35 0x2861
#define mmDPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED36 0x2862
#define mmDPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED37 0x2863
#define mmDPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED38 0x2864
#define mmDPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED39 0x2865
#define mmDPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED40 0x2866
#define mmDPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED41 0x2867
#define mmDPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED42 0x2868
#define mmDPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED43 0x2869
#define mmDPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED44 0x286a
#define mmDPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED45 0x286b
#define mmDPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED46 0x286c
#define mmDPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED47 0x286d
#define mmDPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED48 0x286e
#define mmDPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED49 0x286f
#define mmDPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED50 0x2870
#define mmDPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED51 0x2871
#define mmDPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED52 0x2872
#define mmDPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED53 0x2873
#define mmDPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED54 0x2874
#define mmDPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED55 0x2875
#define mmDPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED56 0x2876
#define mmDPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED57 0x2877
#define mmDPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED58 0x2878
#define mmDPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED59 0x2879
#define mmDPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED60 0x287a
#define mmDPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED61 0x287b
#define mmDPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED62 0x287c
#define mmDPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED63 0x287d
#define mmDPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDPRX_AUX_REFERENCE_PULSE_DIV 0x2a7e
#define mmDPRX_AUX_REFERENCE_PULSE_DIV_BASE_IDX 2
#define mmDPRX_AUX_CONTROL 0x2a7f
#define mmDPRX_AUX_CONTROL_BASE_IDX 2
#define mmDPRX_AUX_HPD_CONTROL1 0x2a80
#define mmDPRX_AUX_HPD_CONTROL1_BASE_IDX 2
#define mmDPRX_AUX_HPD_CONTROL2 0x2a81
#define mmDPRX_AUX_HPD_CONTROL2_BASE_IDX 2
#define mmDPRX_AUX_RX_STATUS 0x2a82
#define mmDPRX_AUX_RX_STATUS_BASE_IDX 2
#define mmDPRX_AUX_RX_ERROR_MASK 0x2a83
#define mmDPRX_AUX_RX_ERROR_MASK_BASE_IDX 2
#define mmDPRX_AUX_DPHY_TX_REF_CONTROL 0x2a84
#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDPRX_AUX_DPHY_TX_CONTROL 0x2a85
#define mmDPRX_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDPRX_AUX_DPHY_RX_CONTROL0 0x2a86
#define mmDPRX_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDPRX_AUX_DPHY_RX_CONTROL1 0x2a87
#define mmDPRX_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDPRX_AUX_DPHY_TX_STATUS 0x2a88
#define mmDPRX_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDPRX_AUX_DPHY_RX_STATUS 0x2a89
#define mmDPRX_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDPRX_AUX_DMCU_HW_INT_STATUS 0x2a8a
#define mmDPRX_AUX_DMCU_HW_INT_STATUS_BASE_IDX 2
#define mmDPRX_AUX_DMCU_HW_INT_ACK 0x2a8b
#define mmDPRX_AUX_DMCU_HW_INT_ACK_BASE_IDX 2
#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1 0x2a8c
#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_BASE_IDX 2
#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2 0x2a8d
#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_BASE_IDX 2
#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1 0x2a8e
#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_BASE_IDX 2
#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2 0x2a8f
#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_BASE_IDX 2
#define mmDPRX_AUX_AUX_BUF_INDEX 0x2a90
#define mmDPRX_AUX_AUX_BUF_INDEX_BASE_IDX 2
#define mmDPRX_AUX_AUX_BUF_DATA 0x2a91
#define mmDPRX_AUX_AUX_BUF_DATA_BASE_IDX 2
#define mmDPRX_AUX_EDID_INDEX 0x2a92
#define mmDPRX_AUX_EDID_INDEX_BASE_IDX 2
#define mmDPRX_AUX_EDID_DATA 0x2a93
#define mmDPRX_AUX_EDID_DATA_BASE_IDX 2
#define mmDPRX_AUX_DPCD_INDEX1 0x2a94
#define mmDPRX_AUX_DPCD_INDEX1_BASE_IDX 2
#define mmDPRX_AUX_DPCD_DATA1 0x2a95
#define mmDPRX_AUX_DPCD_DATA1_BASE_IDX 2
#define mmDPRX_AUX_DPCD_INDEX2 0x2a96
#define mmDPRX_AUX_DPCD_INDEX2_BASE_IDX 2
#define mmDPRX_AUX_DPCD_DATA2 0x2a97
#define mmDPRX_AUX_DPCD_DATA2_BASE_IDX 2
#define mmDPRX_AUX_MSG_INDEX1 0x2a98
#define mmDPRX_AUX_MSG_INDEX1_BASE_IDX 2
#define mmDPRX_AUX_MSG_DATA1 0x2a99
#define mmDPRX_AUX_MSG_DATA1_BASE_IDX 2
#define mmDPRX_AUX_MSG_INDEX2 0x2a9a
#define mmDPRX_AUX_MSG_INDEX2_BASE_IDX 2
#define mmDPRX_AUX_MSG_DATA2 0x2a9b
#define mmDPRX_AUX_MSG_DATA2_BASE_IDX 2
#define mmDPRX_AUX_KSV_INDEX1 0x2a9c
#define mmDPRX_AUX_KSV_INDEX1_BASE_IDX 2
#define mmDPRX_AUX_KSV_DATA1 0x2a9d
#define mmDPRX_AUX_KSV_DATA1_BASE_IDX 2
#define mmDPRX_AUX_KSV_INDEX2 0x2a9e
#define mmDPRX_AUX_KSV_INDEX2_BASE_IDX 2
#define mmDPRX_AUX_KSV_DATA2 0x2a9f
#define mmDPRX_AUX_KSV_DATA2_BASE_IDX 2
#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL 0x2aa0
#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_BASE_IDX 2
#define mmDPRX_AUX_MSG_BUF_CONTROL1 0x2aa1
#define mmDPRX_AUX_MSG_BUF_CONTROL1_BASE_IDX 2
#define mmDPRX_AUX_MSG_BUF_CONTROL2 0x2aa2
#define mmDPRX_AUX_MSG_BUF_CONTROL2_BASE_IDX 2
#define mmDPRX_AUX_SCRATCH1 0x2aa3
#define mmDPRX_AUX_SCRATCH1_BASE_IDX 2
#define mmDPRX_AUX_SCRATCH2 0x2aa4
#define mmDPRX_AUX_SCRATCH2_BASE_IDX 2
#define mmDPRX_AUX_MSG1_PENDING 0x2aa5
#define mmDPRX_AUX_MSG1_PENDING_BASE_IDX 2
#define mmDPRX_AUX_MSG2_PENDING 0x2aa6
#define mmDPRX_AUX_MSG2_PENDING_BASE_IDX 2
#define mmDPRX_AUX_MSG3_PENDING 0x2aa7
#define mmDPRX_AUX_MSG3_PENDING_BASE_IDX 2
#define mmDPRX_AUX_MSG4_PENDING 0x2aa8
#define mmDPRX_AUX_MSG4_PENDING_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET 0x2afe
#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET 0x2aff
#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_MSTM_CTRL 0x2b00
#define mmDPRX_DPHY_DPCD_MSTM_CTRL_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET 0x2b01
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS 0x2b02
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET 0x2b03
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS 0x2b04
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET 0x2b05
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS 0x2b06
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET 0x2b07
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS 0x2b08
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_READY 0x2b09
#define mmDPRX_DPHY_READY_BASE_IDX 2
#define mmDPRX_DPHY_COMMA_STATUS 0x2b0b
#define mmDPRX_DPHY_COMMA_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED 0x2b0c
#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_BASE_IDX 2
#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED 0x2b0d
#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0 0x2b0f
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0 0x2b11
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0 0x2b12
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0 0x2b13
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1 0x2b14
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1 0x2b16
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1 0x2b17
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1 0x2b18
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2 0x2b19
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2 0x2b1b
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2 0x2b1c
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2 0x2b1d
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3 0x2b1e
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3 0x2b20
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3 0x2b21
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3 0x2b22
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_BASE_IDX 2
#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL 0x2b24
#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_BASE_IDX 2
#define mmDPRX_DPHY_SR_ERROR_COUNT_A 0x2b25
#define mmDPRX_DPHY_SR_ERROR_COUNT_A_BASE_IDX 2
#define mmDPRX_DPHY_BS_ERROR_COUNT_A 0x2b27
#define mmDPRX_DPHY_BS_ERROR_COUNT_A_BASE_IDX 2
#define mmDPRX_DPHY_BS_ERROR_COUNT_B 0x2b28
#define mmDPRX_DPHY_BS_ERROR_COUNT_B_BASE_IDX 2
#define mmDPRX_DPHY_LANESETUP0 0x2b2d
#define mmDPRX_DPHY_LANESETUP0_BASE_IDX 2
#define mmDPRX_DPHY_LANESETUP1 0x2b2e
#define mmDPRX_DPHY_LANESETUP1_BASE_IDX 2
#define mmDPRX_DPHY_LFSRADV 0x2b31
#define mmDPRX_DPHY_LFSRADV_BASE_IDX 2
#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT 0x2b32
#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_BASE_IDX 2
#define mmDPRX_DPHY_SET_ENABLE 0x2b33
#define mmDPRX_DPHY_SET_ENABLE_BASE_IDX 2
#define mmDPRX_DPHY_ECF_LSB 0x2b34
#define mmDPRX_DPHY_ECF_LSB_BASE_IDX 2
#define mmDPRX_DPHY_ECF_MSB 0x2b35
#define mmDPRX_DPHY_ECF_MSB_BASE_IDX 2
#define mmDPRX_DPHY_ENHANCED_FRAME_EN 0x2b36
#define mmDPRX_DPHY_ENHANCED_FRAME_EN_BASE_IDX 2
#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE 0x2b3c
#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_BASE_IDX 2
#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA 0x2b3d
#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_BASE_IDX 2
#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL 0x2b3e
#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_BASE_IDX 2
#define mmDPRX_DPHY_BYPASS 0x2b3f
#define mmDPRX_DPHY_BYPASS_BASE_IDX 2
#define mmDPRX_DPHY_INT_RESET 0x2b40
#define mmDPRX_DPHY_INT_RESET_BASE_IDX 2
#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS 0x2b41
#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS 0x2b43
#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS 0x2b44
#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS 0x2b46
#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS 0x2b48
#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS 0x2b49
#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS 0x2b4a
#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS 0x2b4b
#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS 0x2b4c
#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_SPARE 0x2b4d
#define mmDPRX_DPHY_SPARE_BASE_IDX 2
#define mmDCRX_GATE_DISABLE_CNTL 0x2b6e
#define mmDCRX_GATE_DISABLE_CNTL_BASE_IDX 2
#define mmDCRX_SOFT_RESET 0x2b6f
#define mmDCRX_SOFT_RESET_BASE_IDX 2
#define mmDCRX_LIGHT_SLEEP_CNTL 0x2b70
#define mmDCRX_LIGHT_SLEEP_CNTL_BASE_IDX 2
#define mmDCRX_DISPCLK_GATE_CNTL 0x2b73
#define mmDCRX_DISPCLK_GATE_CNTL_BASE_IDX 2
#define mmDCRX_CLK_CNTL 0x2b74
#define mmDCRX_CLK_CNTL_BASE_IDX 2
#define mmDCRX_TEST_CLK_CNTL 0x2b75
#define mmDCRX_TEST_CLK_CNTL_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x2c06
#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x2c07
#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x2c08
#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x2c09
#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x2c0a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x2c0b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x2c0c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x2c0d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x2c0e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x2c0f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x2c10
#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x2c11
#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x2c12
#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x2c13
#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x2c14
#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x2c15
#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x2c16
#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x2c17
#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x2c18
#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x2c19
#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x2c1a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x2c1b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x2c1c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x2c1d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x2c1e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x2c1f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x2c20
#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x2c21
#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x2c22
#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x2c23
#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x2c24
#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x2c25
#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x2c26
#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x2c27
#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x2c28
#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x2c29
#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x2c2a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x2c2b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x2c2c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x2c2d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x2c2e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x2c2f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x2c30
#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x2c31
#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x2c32
#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x2c33
#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x2c34
#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x2c35
#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x2c36
#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x2c37
#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x2c38
#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x2c39
#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x2c3a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x2c3b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x2c3c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x2c3d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x2c3e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x2c3f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x2c40
#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x2c41
#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x2c42
#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_BASE_IDX 2