blob: 3f15938dec893b1d945d4b85503590c909588ce0 [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0-only
* Copyright (C) 2017 SiFive
#include <asm/pgtable.h>
#include <asm/cacheflush.h>
#include <asm/sbi.h>
void flush_icache_all(void)
* Performs an icache flush for the given MM context. RISC-V has no direct
* mechanism for instruction cache shoot downs, so instead we send an IPI that
* informs the remote harts they need to flush their local instruction caches.
* To avoid pathologically slow behavior in a common case (a bunch of
* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
* IPIs for harts that are not currently executing a MM context and instead
* schedule a deferred local instruction cache flush to be performed before
* execution resumes on each hart.
void flush_icache_mm(struct mm_struct *mm, bool local)
unsigned int cpu;
cpumask_t others, hmask, *mask;
/* Mark every hart's icache as needing a flush for this MM. */
mask = &mm->context.icache_stale_mask;
/* Flush this hart's I$ now, and mark it as flushed. */
cpu = smp_processor_id();
cpumask_clear_cpu(cpu, mask);
* Flush the I$ of other harts concurrently executing, and mark them as
* flushed.
cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
local |= cpumask_empty(&others);
if (mm != current->active_mm || !local) {
riscv_cpuid_to_hartid_mask(&others, &hmask);
} else {
* It's assumed that at least one strongly ordered operation is
* performed on this hart between setting a hart's cpumask bit
* and scheduling this MM context on that hart. Sending an SBI
* remote message will do this, but in the case where no
* messages are sent we still need to order this hart's writes
* with flush_icache_deferred().
#endif /* CONFIG_SMP */
void flush_icache_pte(pte_t pte)
struct page *page = pte_page(pte);
if (!test_and_set_bit(PG_dcache_clean, &page->flags))