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SiFive L2 Cache Controller
The SiFive Level 2 Cache Controller is used to provide access to fast copies
of memory for masters in a Core Complex. The Level 2 Cache Controller also
acts as directory-based coherency manager.
All the properties in ePAPR/DeviceTree specification applies for this platform
Required Properties:
- compatible: Should be "sifive,fu540-c000-ccache" and "cache"
- cache-block-size: Specifies the block size in bytes of the cache.
Should be 64
- cache-level: Should be set to 2 for a level 2 cache
- cache-sets: Specifies the number of associativity sets of the cache.
Should be 1024
- cache-size: Specifies the size in bytes of the cache. Should be 2097152
- cache-unified: Specifies the cache is a unified cache
- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals)
- reg: Physical base address and size of L2 cache controller registers map
Optional Properties:
- next-level-cache: phandle to the next level cache if present.
- memory-region: reference to the reserved-memory for the L2 Loosely Integrated
Memory region. The reserved memory node should be defined as per the bindings
in reserved-memory.txt
cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
interrupt-parent = <&plic0>;
interrupts = <1 2 3>;
reg = <0x0 0x2010000 0x0 0x1000>;
next-level-cache = <&L25 &L40 &L36>;
memory-region = <&l2_lim>;