commit | dc6fcba72f0435b7884f2e92fd634bb9f78a2c60 | [log] [tgz] |
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author | Guo Ren <ren_guo@c-sky.com> | Sun Jan 05 10:52:14 2020 +0800 |
committer | Paul Walmsley <paul.walmsley@sifive.com> | Sun Jan 12 10:12:44 2020 -0800 |
tree | dedfd6d441a9e9f2854a7bccc11bbaccc8580c40 | |
parent | 13cf4cf030183dd9a8731f3fe32456e83b6c7b68 [diff] |
riscv: Fixup obvious bug for fp-regs reset CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine ISA Register misa. Every bit:1 indicate a feature, so we should beqz reset_done when there is no F/D bit in csr_misa register. Signed-off-by: Guo Ren <ren_guo@c-sky.com> [paul.walmsley@sifive.com: fix typo in commit message] Fixes: 9e80635619b51 ("riscv: clear the instruction cache and all registers when booting") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>