| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| |
| /* |
| * Copyright (C) 2018 Zodiac Inflight Innovations |
| */ |
| |
| /dts-v1/; |
| #include "vf610.dtsi" |
| |
| / { |
| model = "ZII VF610 CFU1 Board"; |
| compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610"; |
| |
| chosen { |
| stdout-path = &uart0; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0x20000000>; |
| }; |
| |
| gpio-leds { |
| compatible = "gpio-leds"; |
| pinctrl-0 = <&pinctrl_leds_debug>; |
| pinctrl-names = "default"; |
| |
| led-debug { |
| label = "zii:green:debug1"; |
| gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; |
| linux,default-trigger = "heartbeat"; |
| }; |
| |
| led-fail { |
| label = "zii:red:fail"; |
| gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; |
| default-state = "off"; |
| }; |
| |
| led-status { |
| label = "zii:green:status"; |
| gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-debug-a { |
| label = "zii:green:debug_a"; |
| gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-debug-b { |
| label = "zii:green:debug_b"; |
| gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| }; |
| |
| reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { |
| compatible = "regulator-fixed"; |
| regulator-name = "vcc_3v3_mcu"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| sff: sfp { |
| compatible = "sff,sff"; |
| pinctrl-0 = <&pinctrl_optical>; |
| pinctrl-names = "default"; |
| i2c-bus = <&i2c0>; |
| los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; |
| tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; |
| }; |
| }; |
| |
| &adc0 { |
| vref-supply = <®_vcc_3v3_mcu>; |
| status = "okay"; |
| }; |
| |
| &adc1 { |
| vref-supply = <®_vcc_3v3_mcu>; |
| status = "okay"; |
| }; |
| |
| &dspi1 { |
| bus-num = <1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_dspi1>; |
| /* |
| * Some CFU1s come with SPI-NOR chip DNPed, so we leave this |
| * node disabled by default and rely on bootloader to enable |
| * it when appropriate. |
| */ |
| status = "disabled"; |
| |
| flash@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "m25p128", "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <50000000>; |
| |
| partition@0 { |
| label = "m25p128-0"; |
| reg = <0x0 0x01000000>; |
| }; |
| }; |
| }; |
| |
| &edma0 { |
| status = "okay"; |
| }; |
| |
| &edma1 { |
| status = "okay"; |
| }; |
| |
| &esdhc0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_esdhc0>; |
| bus-width = <8>; |
| non-removable; |
| no-1-8-v; |
| keep-power-in-suspend; |
| no-sdio; |
| no-sd; |
| status = "okay"; |
| }; |
| |
| &esdhc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_esdhc1>; |
| bus-width = <4>; |
| no-sdio; |
| status = "okay"; |
| }; |
| |
| &fec1 { |
| phy-mode = "rmii"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| status = "okay"; |
| |
| fixed-link { |
| speed = <100>; |
| full-duplex; |
| }; |
| |
| mdio1: mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "okay"; |
| |
| switch0: switch0@0 { |
| compatible = "marvell,mv88e6085"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_switch>; |
| reg = <0>; |
| eeprom-length = <512>; |
| interrupt-parent = <&gpio3>; |
| interrupts = <2 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| label = "eth_cu_1000_1"; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| label = "eth_cu_1000_2"; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| label = "eth_cu_1000_3"; |
| }; |
| |
| port@5 { |
| reg = <5>; |
| label = "eth_fc_1000_1"; |
| phy-mode = "1000base-x"; |
| managed = "in-band-status"; |
| sfp = <&sff>; |
| }; |
| |
| port@6 { |
| reg = <6>; |
| label = "cpu"; |
| ethernet = <&fec1>; |
| |
| fixed-link { |
| speed = <100>; |
| full-duplex; |
| }; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c0 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c0>; |
| status = "okay"; |
| |
| io-expander@22 { |
| compatible = "nxp,pca9554"; |
| reg = <0x22>; |
| gpio-controller; |
| }; |
| |
| lm75@48 { |
| compatible = "national,lm75"; |
| reg = <0x48>; |
| }; |
| |
| eeprom@52 { |
| compatible = "atmel,24c04"; |
| reg = <0x52>; |
| label = "nvm"; |
| }; |
| |
| eeprom@54 { |
| compatible = "atmel,24c04"; |
| reg = <0x54>; |
| label = "nameplate"; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| watchdog@38 { |
| compatible = "zii,rave-wdt"; |
| reg = <0x38>; |
| }; |
| }; |
| |
| &snvsrtc { |
| status = "disabled"; |
| }; |
| |
| &uart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart0>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_dspi1: dspi1grp { |
| fsl,pins = < |
| VF610_PAD_PTD5__DSPI1_CS0 0x1182 |
| VF610_PAD_PTC6__DSPI1_SIN 0x1181 |
| VF610_PAD_PTC7__DSPI1_SOUT 0x1182 |
| VF610_PAD_PTC8__DSPI1_SCK 0x1182 |
| >; |
| }; |
| |
| pinctrl_esdhc0: esdhc0grp { |
| fsl,pins = < |
| VF610_PAD_PTC0__ESDHC0_CLK 0x31ef |
| VF610_PAD_PTC1__ESDHC0_CMD 0x31ef |
| VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef |
| VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef |
| VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef |
| VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef |
| VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef |
| VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef |
| VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef |
| VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef |
| >; |
| }; |
| |
| pinctrl_esdhc1: esdhc1grp { |
| fsl,pins = < |
| VF610_PAD_PTA24__ESDHC1_CLK 0x31ef |
| VF610_PAD_PTA25__ESDHC1_CMD 0x31ef |
| VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef |
| VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef |
| VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef |
| VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef |
| >; |
| }; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| VF610_PAD_PTA6__RMII_CLKIN 0x30d1 |
| VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe |
| VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 |
| VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 |
| VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 |
| VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 |
| VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 |
| VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 |
| VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 |
| VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 |
| >; |
| }; |
| |
| pinctrl_i2c0: i2c0grp { |
| fsl,pins = < |
| VF610_PAD_PTB14__I2C0_SCL 0x37ff |
| VF610_PAD_PTB15__I2C0_SDA 0x37ff |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| VF610_PAD_PTB16__I2C1_SCL 0x37ff |
| VF610_PAD_PTB17__I2C1_SDA 0x37ff |
| >; |
| }; |
| |
| pinctrl_leds_debug: pinctrl-leds-debug { |
| fsl,pins = < |
| VF610_PAD_PTD3__GPIO_82 0x31c2 |
| VF610_PAD_PTE3__GPIO_108 0x31c2 |
| VF610_PAD_PTE4__GPIO_109 0x31c2 |
| VF610_PAD_PTE5__GPIO_110 0x31c2 |
| VF610_PAD_PTE6__GPIO_111 0x31c2 |
| >; |
| }; |
| |
| pinctrl_optical: optical-grp { |
| fsl,pins = < |
| /* SFF SD input */ |
| VF610_PAD_PTE27__GPIO_132 0x3061 |
| |
| /* SFF Transmit disable output */ |
| VF610_PAD_PTE13__GPIO_118 0x3043 |
| >; |
| }; |
| |
| pinctrl_switch: switch-grp { |
| fsl,pins = < |
| VF610_PAD_PTB28__GPIO_98 0x3061 |
| VF610_PAD_PTE2__GPIO_107 0x1042 |
| >; |
| }; |
| |
| pinctrl_uart0: uart0grp { |
| fsl,pins = < |
| VF610_PAD_PTB10__UART0_TX 0x21a2 |
| VF610_PAD_PTB11__UART0_RX 0x21a1 |
| >; |
| }; |
| }; |
