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linux / linux / kernel / git / gregkh / usb / b74b991fb8b9d642b8fea20d6245c6e19125a305 / . / drivers / gpu / drm / amd / include / asic_reg / dce / dce_12_0_offset.h
blob: 27bb8c1ab85876bed4ad23bfc6df7648eaa8a851 [file] [log] [blame]
/*
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _dce_12_0_OFFSET_HEADER
#define _dce_12_0_OFFSET_HEADER
// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
// base address: 0x48
#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
// base address: 0x4c
#define mmdispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
// addressBlock: dce_dc_dc_perfmon0_dispdec
// base address: 0x0
#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0020
#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0022
#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL 0x0023
#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL2 0x0024
#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0025
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0026
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_HI 0x0027
#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_LOW 0x0028
#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon13_dispdec
// base address: 0x30
#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x002c
#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x002d
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x002e
#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CNTL 0x002f
#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CNTL2 0x0030
#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0031
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0032
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_HI 0x0033
#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_LOW 0x0034
#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dc_displaypllregs_dispdec
// base address: 0x0
#define mmPPLL_VREG_CFG 0x0038
#define mmPPLL_VREG_CFG_BASE_IDX 2
#define mmPPLL_MODE_CNTL 0x0039
#define mmPPLL_MODE_CNTL_BASE_IDX 2
#define mmPPLL_FREQ_CTRL0 0x003a
#define mmPPLL_FREQ_CTRL0_BASE_IDX 2
#define mmPPLL_FREQ_CTRL1 0x003b
#define mmPPLL_FREQ_CTRL1_BASE_IDX 2
#define mmPPLL_FREQ_CTRL2 0x003c
#define mmPPLL_FREQ_CTRL2_BASE_IDX 2
#define mmPPLL_FREQ_CTRL3 0x003d
#define mmPPLL_FREQ_CTRL3_BASE_IDX 2
#define mmPPLL_BW_CTRL_COARSE 0x003e
#define mmPPLL_BW_CTRL_COARSE_BASE_IDX 2
#define mmPPLL_BW_CTRL_FINE 0x0040
#define mmPPLL_BW_CTRL_FINE_BASE_IDX 2
#define mmPPLL_CAL_CTRL 0x0041
#define mmPPLL_CAL_CTRL_BASE_IDX 2
#define mmPPLL_LOOP_CTRL 0x0042
#define mmPPLL_LOOP_CTRL_BASE_IDX 2
#define mmPPLL_REFCLK_CNTL 0x0050
#define mmPPLL_REFCLK_CNTL_BASE_IDX 2
#define mmPPLL_CLKOUT_CNTL 0x0051
#define mmPPLL_CLKOUT_CNTL_BASE_IDX 2
#define mmPPLL_DFT_CNTL 0x0052
#define mmPPLL_DFT_CNTL_BASE_IDX 2
#define mmPPLL_ANALOG_CNTL 0x0053
#define mmPPLL_ANALOG_CNTL_BASE_IDX 2
#define mmPPLL_POSTDIV 0x0054
#define mmPPLL_POSTDIV_BASE_IDX 2
#define mmPPLL_OBSERVE0 0x0059
#define mmPPLL_OBSERVE0_BASE_IDX 2
#define mmPPLL_OBSERVE1 0x005a
#define mmPPLL_OBSERVE1_BASE_IDX 2
#define mmPPLL_UPDATE_CNTL 0x005c
#define mmPPLL_UPDATE_CNTL_BASE_IDX 2
#define mmPPLL_OBSERVE0_OUT 0x005d
#define mmPPLL_OBSERVE0_OUT_BASE_IDX 2
// addressBlock: dce_dc_dccg_pll0_dispdec
// base address: 0x0
#define mmPLL_MACRO_CNTL_RESERVED0 0x0038
#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED1 0x0039
#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED2 0x003a
#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED3 0x003b
#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED4 0x003c
#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED5 0x003d
#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED6 0x003e
#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED7 0x003f
#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED8 0x0040
#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED9 0x0041
#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED10 0x0042
#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED11 0x0043
#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED12 0x0044
#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED13 0x0045
#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED14 0x0046
#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED15 0x0047
#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED16 0x0048
#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED17 0x0049
#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED18 0x004a
#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED19 0x004b
#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED20 0x004c
#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED21 0x004d
#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED22 0x004e
#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED23 0x004f
#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED24 0x0050
#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED25 0x0051
#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED26 0x0052
#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED27 0x0053
#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED28 0x0054
#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED29 0x0055
#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED30 0x0056
#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED31 0x0057
#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED32 0x0058
#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED33 0x0059
#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED34 0x005a
#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED35 0x005b
#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED36 0x005c
#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED37 0x005d
#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED38 0x005e
#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED39 0x005f
#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED40 0x0060
#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED41 0x0061
#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon1_dispdec
// base address: 0x598
#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x0186
#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x0187
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x0188
#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CNTL 0x0189
#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CNTL2 0x018a
#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x018b
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x018c
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_HI 0x018d
#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_LOW 0x018e
#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_mcif_wb0_dispdec
// base address: 0x0
#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x0272
#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x0273
#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x0274
#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x0275
#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x0276
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x0277
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x0278
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x0279
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x027a
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x027b
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x027c
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x027d
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x027e
#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x027f
#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x0282
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0283
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x0284
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0285
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x0286
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0287
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x0288
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0289
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x028a
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x028b
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x028c
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x028d
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x028e
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x028f
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x0290
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0291
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x0292
#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0293
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x0294
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x0295
#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x0296
#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x0297
#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x0298
#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x0299
#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x029b
#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x029c
#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
// addressBlock: dce_dc_mcif_wb1_dispdec
// base address: 0x100
#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02b4
#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02b5
#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02b6
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02b7
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02b8
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02b9
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02ba
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02bb
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02bc
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02bd
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02be
#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02bf
#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x02c2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x02c4
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x02c6
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x02c8
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x02ca
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x02cc
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x02ce
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x02d0
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x02d5
#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x02d7
#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x02d9
#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x02db
#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
// addressBlock: dce_dc_mcif_wb2_dispdec
// base address: 0x200
#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x02f4
#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x02f5
#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x02f6
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x02f7
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x02f8
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x02f9
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x02fa
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x02fb
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x02fc
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x02fd
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x02fe
#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x02ff
#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x0302
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x0304
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x0306
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x0308
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x030a
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x030c
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x030e
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x0310
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x0314
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x0315
#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x0317
#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x0319
#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x031b
#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x031c
#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
// addressBlock: dce_dc_cwb0_dispdec
// base address: 0x0
#define mmCWB0_CWB_CTRL 0x0332
#define mmCWB0_CWB_CTRL_BASE_IDX 2
#define mmCWB0_CWB_FENCE_PAR0 0x0334
#define mmCWB0_CWB_FENCE_PAR0_BASE_IDX 2
#define mmCWB0_CWB_FENCE_PAR1 0x0335
#define mmCWB0_CWB_FENCE_PAR1_BASE_IDX 2
#define mmCWB0_CWB_CRC_CTRL 0x0339
#define mmCWB0_CWB_CRC_CTRL_BASE_IDX 2
#define mmCWB0_CWB_CRC_RED_GREEN_MASK 0x033a
#define mmCWB0_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
#define mmCWB0_CWB_CRC_BLUE_MASK 0x033b
#define mmCWB0_CWB_CRC_BLUE_MASK_BASE_IDX 2
#define mmCWB0_CWB_CRC_RED_GREEN_RESULT 0x033c
#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
#define mmCWB0_CWB_CRC_BLUE_RESULT 0x033d
#define mmCWB0_CWB_CRC_BLUE_RESULT_BASE_IDX 2
// addressBlock: dce_dc_cwb1_dispdec
// base address: 0x60
#define mmCWB1_CWB_CTRL 0x034a
#define mmCWB1_CWB_CTRL_BASE_IDX 2
#define mmCWB1_CWB_FENCE_PAR0 0x034c
#define mmCWB1_CWB_FENCE_PAR0_BASE_IDX 2
#define mmCWB1_CWB_FENCE_PAR1 0x034d
#define mmCWB1_CWB_FENCE_PAR1_BASE_IDX 2
#define mmCWB1_CWB_CRC_CTRL 0x0351
#define mmCWB1_CWB_CRC_CTRL_BASE_IDX 2
#define mmCWB1_CWB_CRC_RED_GREEN_MASK 0x0352
#define mmCWB1_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
#define mmCWB1_CWB_CRC_BLUE_MASK 0x0353
#define mmCWB1_CWB_CRC_BLUE_MASK_BASE_IDX 2
#define mmCWB1_CWB_CRC_RED_GREEN_RESULT 0x0354
#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
#define mmCWB1_CWB_CRC_BLUE_RESULT 0x0355
#define mmCWB1_CWB_CRC_BLUE_RESULT_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon9_dispdec
// base address: 0xd08
#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0362
#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0363
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0364
#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CNTL 0x0365
#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CNTL2 0x0366
#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0367
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0368
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_HI 0x0369
#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_LOW 0x036a
#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dispdec
// base address: 0x0
#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
#define mmVGA_RENDER_CONTROL 0x0000
#define mmVGA_RENDER_CONTROL_BASE_IDX 1
#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
#define mmVGA_MODE_CONTROL 0x0002
#define mmVGA_MODE_CONTROL_BASE_IDX 1
#define mmVGA_SURFACE_PITCH_SELECT 0x0003
#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
#define mmVGA_HDP_CONTROL 0x000a
#define mmVGA_HDP_CONTROL_BASE_IDX 1
#define mmVGA_CACHE_CONTROL 0x000b
#define mmVGA_CACHE_CONTROL_BASE_IDX 1
#define mmD1VGA_CONTROL 0x000c
#define mmD1VGA_CONTROL_BASE_IDX 1
#define mmD2VGA_CONTROL 0x000e
#define mmD2VGA_CONTROL_BASE_IDX 1
#define mmVGA_STATUS 0x0010
#define mmVGA_STATUS_BASE_IDX 1
#define mmVGA_INTERRUPT_CONTROL 0x0011
#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
#define mmVGA_STATUS_CLEAR 0x0012
#define mmVGA_STATUS_CLEAR_BASE_IDX 1
#define mmVGA_INTERRUPT_STATUS 0x0013
#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
#define mmVGA_MAIN_CONTROL 0x0014
#define mmVGA_MAIN_CONTROL_BASE_IDX 1
#define mmVGA_TEST_CONTROL 0x0015
#define mmVGA_TEST_CONTROL_BASE_IDX 1
#define mmVGA_QOS_CTRL 0x0018
#define mmVGA_QOS_CTRL_BASE_IDX 1
#define mmCRTC8_IDX 0x002d
#define mmCRTC8_IDX_BASE_IDX 1
#define mmCRTC8_DATA 0x002d
#define mmCRTC8_DATA_BASE_IDX 1
#define mmGENFC_WT 0x002e
#define mmGENFC_WT_BASE_IDX 1
#define mmGENS1 0x002e
#define mmGENS1_BASE_IDX 1
#define mmATTRDW 0x0030
#define mmATTRDW_BASE_IDX 1
#define mmATTRX 0x0030
#define mmATTRX_BASE_IDX 1
#define mmATTRDR 0x0030
#define mmATTRDR_BASE_IDX 1
#define mmGENMO_WT 0x0030
#define mmGENMO_WT_BASE_IDX 1
#define mmGENS0 0x0030
#define mmGENS0_BASE_IDX 1
#define mmGENENB 0x0030
#define mmGENENB_BASE_IDX 1
#define mmSEQ8_IDX 0x0031
#define mmSEQ8_IDX_BASE_IDX 1
#define mmSEQ8_DATA 0x0031
#define mmSEQ8_DATA_BASE_IDX 1
#define mmDAC_MASK 0x0031
#define mmDAC_MASK_BASE_IDX 1
#define mmDAC_R_INDEX 0x0031
#define mmDAC_R_INDEX_BASE_IDX 1
#define mmDAC_W_INDEX 0x0032
#define mmDAC_W_INDEX_BASE_IDX 1
#define mmDAC_DATA 0x0032
#define mmDAC_DATA_BASE_IDX 1
#define mmGENFC_RD 0x0032
#define mmGENFC_RD_BASE_IDX 1
#define mmGENMO_RD 0x0033
#define mmGENMO_RD_BASE_IDX 1
#define mmGRPH8_IDX 0x0033
#define mmGRPH8_IDX_BASE_IDX 1
#define mmGRPH8_DATA 0x0033
#define mmGRPH8_DATA_BASE_IDX 1
#define mmCRTC8_IDX_1 0x0035
#define mmCRTC8_IDX_1_BASE_IDX 1
#define mmCRTC8_DATA_1 0x0035
#define mmCRTC8_DATA_1_BASE_IDX 1
#define mmGENFC_WT_1 0x0036
#define mmGENFC_WT_1_BASE_IDX 1
#define mmGENS1_1 0x0036
#define mmGENS1_1_BASE_IDX 1
#define mmD3VGA_CONTROL 0x0038
#define mmD3VGA_CONTROL_BASE_IDX 1
#define mmD4VGA_CONTROL 0x0039
#define mmD4VGA_CONTROL_BASE_IDX 1
#define mmD5VGA_CONTROL 0x003a
#define mmD5VGA_CONTROL_BASE_IDX 1
#define mmD6VGA_CONTROL 0x003b
#define mmD6VGA_CONTROL_BASE_IDX 1
#define mmVGA_SOURCE_SELECT 0x003c
#define mmVGA_SOURCE_SELECT_BASE_IDX 1
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x0044
#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL 0x0045
#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmSYMCLKLPA_CLOCK_ENABLE 0x0046
#define mmSYMCLKLPA_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKLPB_CLOCK_ENABLE 0x0047
#define mmSYMCLKLPB_CLOCK_ENABLE_BASE_IDX 1
#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmREFCLK_CNTL 0x0049
#define mmREFCLK_CNTL_BASE_IDX 1
#define mmMIPI_CLK_CNTL 0x004a
#define mmMIPI_CLK_CNTL_BASE_IDX 1
#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL2 0x004e
#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f
#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_CBUS_WRCMD_DELAY 0x0050
#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1
#define mmDCCG_DS_DTO_INCR 0x0053
#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
#define mmDCCG_DS_DTO_MODULO 0x0054
#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
#define mmDCCG_DS_CNTL 0x0055
#define mmDCCG_DS_CNTL_BASE_IDX 1
#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
#define mmSYMCLKG_CLOCK_ENABLE 0x0057
#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1
#define mmDPREFCLK_CNTL 0x0058
#define mmDPREFCLK_CNTL_BASE_IDX 1
#define mmAOMCLK0_CNTL 0x0059
#define mmAOMCLK0_CNTL_BASE_IDX 1
#define mmAOMCLK1_CNTL 0x005a
#define mmAOMCLK1_CNTL_BASE_IDX 1
#define mmAOMCLK2_CNTL 0x005b
#define mmAOMCLK2_CNTL_BASE_IDX 1
#define mmDCCG_AUDIO_DTO2_PHASE 0x005c
#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO2_MODULO 0x005d
#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1
#define mmDCE_VERSION 0x005e
#define mmDCE_VERSION_BASE_IDX 1
#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCCG_GTC_CNTL 0x0060
#define mmDCCG_GTC_CNTL_BASE_IDX 1
#define mmDCCG_GTC_DTO_INCR 0x0061
#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
#define mmDCCG_GTC_DTO_MODULO 0x0062
#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
#define mmDCCG_GTC_CURRENT 0x0063
#define mmDCCG_GTC_CURRENT_BASE_IDX 1
#define mmDENTIST_DISPCLK_CNTL 0x0064
#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
#define mmMIPI_DTO_CNTL 0x0065
#define mmMIPI_DTO_CNTL_BASE_IDX 1
#define mmMIPI_DTO_PHASE 0x0066
#define mmMIPI_DTO_PHASE_BASE_IDX 1
#define mmMIPI_DTO_MODULO 0x0067
#define mmMIPI_DTO_MODULO_BASE_IDX 1
#define mmDAC_CLK_ENABLE 0x0068
#define mmDAC_CLK_ENABLE_BASE_IDX 1
#define mmDVO_CLK_ENABLE 0x0069
#define mmDVO_CLK_ENABLE_BASE_IDX 1
#define mmAVSYNC_COUNTER_WRITE 0x006a
#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1
#define mmAVSYNC_COUNTER_CONTROL 0x006b
#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1
#define mmDMCU_SMU_INTERRUPT_CNTL 0x006c
#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 1
#define mmSMU_CONTROL 0x006d
#define mmSMU_CONTROL_BASE_IDX 1
#define mmSMU_INTERRUPT_CONTROL 0x006e
#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 1
#define mmAVSYNC_COUNTER_READ 0x006f
#define mmAVSYNC_COUNTER_READ_BASE_IDX 1
#define mmMILLISECOND_TIME_BASE_DIV 0x0070
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL 0x0073
#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL 0x0074
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmSCLK_CGTT_BLK_CTRL_REG 0x0076
#define mmSCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_CAC_STATUS 0x0077
#define mmDCCG_CAC_STATUS_BASE_IDX 1
#define mmPIXCLK1_RESYNC_CNTL 0x0078
#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1
#define mmPIXCLK2_RESYNC_CNTL 0x0079
#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1
#define mmPIXCLK0_RESYNC_CNTL 0x007a
#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1
#define mmMICROSECOND_TIME_BASE_DIV 0x007b
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCCG_DISP_CNTL_REG 0x007f
#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
#define mmCRTC0_PIXEL_RATE_CNTL 0x0080
#define mmCRTC0_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO0_PHASE 0x0081
#define mmDP_DTO0_PHASE_BASE_IDX 1
#define mmDP_DTO0_MODULO 0x0082
#define mmDP_DTO0_MODULO_BASE_IDX 1
#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0x0083
#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmCRTC1_PIXEL_RATE_CNTL 0x0084
#define mmCRTC1_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO1_PHASE 0x0085
#define mmDP_DTO1_PHASE_BASE_IDX 1
#define mmDP_DTO1_MODULO 0x0086
#define mmDP_DTO1_MODULO_BASE_IDX 1
#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0x0087
#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmCRTC2_PIXEL_RATE_CNTL 0x0088
#define mmCRTC2_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO2_PHASE 0x0089
#define mmDP_DTO2_PHASE_BASE_IDX 1
#define mmDP_DTO2_MODULO 0x008a
#define mmDP_DTO2_MODULO_BASE_IDX 1
#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0x008b
#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmCRTC3_PIXEL_RATE_CNTL 0x008c
#define mmCRTC3_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO3_PHASE 0x008d
#define mmDP_DTO3_PHASE_BASE_IDX 1
#define mmDP_DTO3_MODULO 0x008e
#define mmDP_DTO3_MODULO_BASE_IDX 1
#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0x008f
#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmCRTC4_PIXEL_RATE_CNTL 0x0090
#define mmCRTC4_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO4_PHASE 0x0091
#define mmDP_DTO4_PHASE_BASE_IDX 1
#define mmDP_DTO4_MODULO 0x0092
#define mmDP_DTO4_MODULO_BASE_IDX 1
#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0x0093
#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmCRTC5_PIXEL_RATE_CNTL 0x0094
#define mmCRTC5_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO5_PHASE 0x0095
#define mmDP_DTO5_PHASE_BASE_IDX 1
#define mmDP_DTO5_MODULO 0x0096
#define mmDP_DTO5_MODULO_BASE_IDX 1
#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0x0097
#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDCCG_SOFT_RESET 0x009f
#define mmDCCG_SOFT_RESET_BASE_IDX 1
#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
#define mmDVOACLKD_CNTL 0x00a8
#define mmDVOACLKD_CNTL_BASE_IDX 1
#define mmDVOACLKC_MVP_CNTL 0x00a9
#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1
#define mmDVOACLKC_CNTL 0x00aa
#define mmDVOACLKC_CNTL_BASE_IDX 1
#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
#define mmDCCG_TEST_CLK_SEL 0x00be
#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
#define mmFBC_CNTL 0x0062
#define mmFBC_CNTL_BASE_IDX 2
#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x0064
#define mmFBC_IDLE_FORCE_CLEAR_MASK_BASE_IDX 2
#define mmFBC_START_STOP_DELAY 0x0065
#define mmFBC_START_STOP_DELAY_BASE_IDX 2
#define mmFBC_COMP_CNTL 0x0066
#define mmFBC_COMP_CNTL_BASE_IDX 2
#define mmFBC_COMP_MODE 0x0067
#define mmFBC_COMP_MODE_BASE_IDX 2
#define mmFBC_IND_LUT0 0x006b
#define mmFBC_IND_LUT0_BASE_IDX 2
#define mmFBC_IND_LUT1 0x006c
#define mmFBC_IND_LUT1_BASE_IDX 2
#define mmFBC_IND_LUT2 0x006d
#define mmFBC_IND_LUT2_BASE_IDX 2
#define mmFBC_IND_LUT3 0x006e
#define mmFBC_IND_LUT3_BASE_IDX 2
#define mmFBC_IND_LUT4 0x006f
#define mmFBC_IND_LUT4_BASE_IDX 2
#define mmFBC_IND_LUT5 0x0070
#define mmFBC_IND_LUT5_BASE_IDX 2
#define mmFBC_IND_LUT6 0x0071
#define mmFBC_IND_LUT6_BASE_IDX 2
#define mmFBC_IND_LUT7 0x0072
#define mmFBC_IND_LUT7_BASE_IDX 2
#define mmFBC_IND_LUT8 0x0073
#define mmFBC_IND_LUT8_BASE_IDX 2
#define mmFBC_IND_LUT9 0x0074
#define mmFBC_IND_LUT9_BASE_IDX 2
#define mmFBC_IND_LUT10 0x0075
#define mmFBC_IND_LUT10_BASE_IDX 2
#define mmFBC_IND_LUT11 0x0076
#define mmFBC_IND_LUT11_BASE_IDX 2
#define mmFBC_IND_LUT12 0x0077
#define mmFBC_IND_LUT12_BASE_IDX 2
#define mmFBC_IND_LUT13 0x0078
#define mmFBC_IND_LUT13_BASE_IDX 2
#define mmFBC_IND_LUT14 0x0079
#define mmFBC_IND_LUT14_BASE_IDX 2
#define mmFBC_IND_LUT15 0x007a
#define mmFBC_IND_LUT15_BASE_IDX 2
#define mmFBC_CSM_REGION_OFFSET_01 0x007b
#define mmFBC_CSM_REGION_OFFSET_01_BASE_IDX 2
#define mmFBC_CSM_REGION_OFFSET_23 0x007c
#define mmFBC_CSM_REGION_OFFSET_23_BASE_IDX 2
#define mmFBC_CLIENT_REGION_MASK 0x007d
#define mmFBC_CLIENT_REGION_MASK_BASE_IDX 2
#define mmFBC_DEBUG_COMP 0x007e
#define mmFBC_DEBUG_COMP_BASE_IDX 2
#define mmFBC_MISC 0x0084
#define mmFBC_MISC_BASE_IDX 2
#define mmFBC_STATUS 0x0085
#define mmFBC_STATUS_BASE_IDX 2
#define mmFBC_ALPHA_CNTL 0x0088
#define mmFBC_ALPHA_CNTL_BASE_IDX 2
#define mmFBC_ALPHA_RGB_OVERRIDE 0x0089
#define mmFBC_ALPHA_RGB_OVERRIDE_BASE_IDX 2
#define mmPIPE0_PG_CONFIG 0x008e
#define mmPIPE0_PG_CONFIG_BASE_IDX 2
#define mmPIPE0_PG_ENABLE 0x008f
#define mmPIPE0_PG_ENABLE_BASE_IDX 2
#define mmPIPE0_PG_STATUS 0x0090
#define mmPIPE0_PG_STATUS_BASE_IDX 2
#define mmPIPE1_PG_CONFIG 0x0091
#define mmPIPE1_PG_CONFIG_BASE_IDX 2
#define mmPIPE1_PG_ENABLE 0x0092
#define mmPIPE1_PG_ENABLE_BASE_IDX 2
#define mmPIPE1_PG_STATUS 0x0093
#define mmPIPE1_PG_STATUS_BASE_IDX 2
#define mmPIPE2_PG_CONFIG 0x0094
#define mmPIPE2_PG_CONFIG_BASE_IDX 2
#define mmPIPE2_PG_ENABLE 0x0095
#define mmPIPE2_PG_ENABLE_BASE_IDX 2
#define mmPIPE2_PG_STATUS 0x0096
#define mmPIPE2_PG_STATUS_BASE_IDX 2
#define mmPIPE3_PG_CONFIG 0x0097
#define mmPIPE3_PG_CONFIG_BASE_IDX 2
#define mmPIPE3_PG_ENABLE 0x0098
#define mmPIPE3_PG_ENABLE_BASE_IDX 2
#define mmPIPE3_PG_STATUS 0x0099
#define mmPIPE3_PG_STATUS_BASE_IDX 2
#define mmPIPE4_PG_CONFIG 0x009a
#define mmPIPE4_PG_CONFIG_BASE_IDX 2
#define mmPIPE4_PG_ENABLE 0x009b
#define mmPIPE4_PG_ENABLE_BASE_IDX 2
#define mmPIPE4_PG_STATUS 0x009c
#define mmPIPE4_PG_STATUS_BASE_IDX 2
#define mmPIPE5_PG_CONFIG 0x009d
#define mmPIPE5_PG_CONFIG_BASE_IDX 2
#define mmPIPE5_PG_ENABLE 0x009e
#define mmPIPE5_PG_ENABLE_BASE_IDX 2
#define mmPIPE5_PG_STATUS 0x009f
#define mmPIPE5_PG_STATUS_BASE_IDX 2
#define mmDSI_PG_CONFIG 0x00a0
#define mmDSI_PG_CONFIG_BASE_IDX 2
#define mmDSI_PG_ENABLE 0x00a1
#define mmDSI_PG_ENABLE_BASE_IDX 2
#define mmDSI_PG_STATUS 0x00a2
#define mmDSI_PG_STATUS_BASE_IDX 2
#define mmDCFEV0_PG_CONFIG 0x00a3
#define mmDCFEV0_PG_CONFIG_BASE_IDX 2
#define mmDCFEV0_PG_ENABLE 0x00a4
#define mmDCFEV0_PG_ENABLE_BASE_IDX 2
#define mmDCFEV0_PG_STATUS 0x00a5
#define mmDCFEV0_PG_STATUS_BASE_IDX 2
#define mmDCPG_INTERRUPT_STATUS 0x00a6
#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL 0x00a7
#define mmDCPG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL2 0x00a8
#define mmDCPG_INTERRUPT_CONTROL2_BASE_IDX 2
#define mmDCFEV1_PG_CONFIG 0x00a9
#define mmDCFEV1_PG_CONFIG_BASE_IDX 2
#define mmDCFEV1_PG_ENABLE 0x00aa
#define mmDCFEV1_PG_ENABLE_BASE_IDX 2
#define mmDCFEV1_PG_STATUS 0x00ab
#define mmDCFEV1_PG_STATUS_BASE_IDX 2
#define mmDC_IP_REQUEST_CNTL 0x00ac
#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
#define mmDC_PGCNTL_STATUS_REG 0x00ad
#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2
#define mmDMIFV_STATUS 0x00c3
#define mmDMIFV_STATUS_BASE_IDX 2
#define mmDMIF_CONTROL 0x00c4
#define mmDMIF_CONTROL_BASE_IDX 2
#define mmDMIF_STATUS 0x00c5
#define mmDMIF_STATUS_BASE_IDX 2
#define mmDMIF_ARBITRATION_CONTROL 0x00c7
#define mmDMIF_ARBITRATION_CONTROL_BASE_IDX 2
#define mmPIPE0_ARBITRATION_CONTROL3 0x00c8
#define mmPIPE0_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE1_ARBITRATION_CONTROL3 0x00c9
#define mmPIPE1_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE2_ARBITRATION_CONTROL3 0x00ca
#define mmPIPE2_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE3_ARBITRATION_CONTROL3 0x00cb
#define mmPIPE3_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE4_ARBITRATION_CONTROL3 0x00cc
#define mmPIPE4_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE5_ARBITRATION_CONTROL3 0x00cd
#define mmPIPE5_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmDMIF_P_VMID 0x00ce
#define mmDMIF_P_VMID_BASE_IDX 2
#define mmDMIF_ADDR_CALC 0x00d1
#define mmDMIF_ADDR_CALC_BASE_IDX 2
#define mmDMIF_STATUS2 0x00d2
#define mmDMIF_STATUS2_BASE_IDX 2
#define mmPIPE0_MAX_REQUESTS 0x00d3
#define mmPIPE0_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE1_MAX_REQUESTS 0x00d4
#define mmPIPE1_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE2_MAX_REQUESTS 0x00d5
#define mmPIPE2_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE3_MAX_REQUESTS 0x00d6
#define mmPIPE3_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE4_MAX_REQUESTS 0x00d7
#define mmPIPE4_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE5_MAX_REQUESTS 0x00d8
#define mmPIPE5_MAX_REQUESTS_BASE_IDX 2
#define mmLOW_POWER_TILING_CONTROL 0x00d9
#define mmLOW_POWER_TILING_CONTROL_BASE_IDX 2
#define mmMCIF_CONTROL 0x00da
#define mmMCIF_CONTROL_BASE_IDX 2
#define mmMCIF_WRITE_COMBINE_CONTROL 0x00db
#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x00de
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmCC_DC_PIPE_DIS 0x00e0
#define mmCC_DC_PIPE_DIS_BASE_IDX 2
#define mmSMU_WM_CONTROL 0x00e1
#define mmSMU_WM_CONTROL_BASE_IDX 2
#define mmRBBMIF_TIMEOUT 0x00e2
#define mmRBBMIF_TIMEOUT_BASE_IDX 2
#define mmRBBMIF_STATUS 0x00e3
#define mmRBBMIF_STATUS_BASE_IDX 2
#define mmRBBMIF_TIMEOUT_DIS 0x00e4
#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
#define mmDCI_MEM_PWR_STATUS 0x00e5
#define mmDCI_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCI_MEM_PWR_STATUS2 0x00e6
#define mmDCI_MEM_PWR_STATUS2_BASE_IDX 2
#define mmDCI_CLK_CNTL 0x00e7
#define mmDCI_CLK_CNTL_BASE_IDX 2
#define mmDCI_CLK_CNTL2 0x00e8
#define mmDCI_CLK_CNTL2_BASE_IDX 2
#define mmDCI_MEM_PWR_CNTL 0x00e9
#define mmDCI_MEM_PWR_CNTL_BASE_IDX 2
#define mmDCI_MEM_PWR_CNTL2 0x00ea
#define mmDCI_MEM_PWR_CNTL2_BASE_IDX 2
#define mmDCI_MEM_PWR_CNTL3 0x00eb
#define mmDCI_MEM_PWR_CNTL3_BASE_IDX 2
#define mmPIPE0_DMIF_BUFFER_CONTROL 0x00ef
#define mmPIPE0_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmPIPE1_DMIF_BUFFER_CONTROL 0x00f0
#define mmPIPE1_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmPIPE2_DMIF_BUFFER_CONTROL 0x00f1
#define mmPIPE2_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmPIPE3_DMIF_BUFFER_CONTROL 0x00f2
#define mmPIPE3_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmPIPE4_DMIF_BUFFER_CONTROL 0x00f3
#define mmPIPE4_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmPIPE5_DMIF_BUFFER_CONTROL 0x00f4
#define mmPIPE5_DMIF_BUFFER_CONTROL_BASE_IDX 2
#define mmRBBMIF_STATUS_FLAG 0x00f5
#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
#define mmDCI_SOFT_RESET 0x00f6
#define mmDCI_SOFT_RESET_BASE_IDX 2
#define mmDMIF_URG_OVERRIDE 0x00f7
#define mmDMIF_URG_OVERRIDE_BASE_IDX 2
#define mmPIPE6_ARBITRATION_CONTROL3 0x00f8
#define mmPIPE6_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE7_ARBITRATION_CONTROL3 0x00f9
#define mmPIPE7_ARBITRATION_CONTROL3_BASE_IDX 2
#define mmPIPE6_MAX_REQUESTS 0x00fa
#define mmPIPE6_MAX_REQUESTS_BASE_IDX 2
#define mmPIPE7_MAX_REQUESTS 0x00fb
#define mmPIPE7_MAX_REQUESTS_BASE_IDX 2
#define mmDVMM_REG_RD_STATUS 0x00fc
#define mmDVMM_REG_RD_STATUS_BASE_IDX 2
#define mmDVMM_REG_RD_DATA 0x00fd
#define mmDVMM_REG_RD_DATA_BASE_IDX 2
#define mmDVMM_PTE_REQ 0x00fe
#define mmDVMM_PTE_REQ_BASE_IDX 2
#define mmDVMM_CNTL 0x00ff
#define mmDVMM_CNTL_BASE_IDX 2
#define mmDVMM_FAULT_STATUS 0x0100
#define mmDVMM_FAULT_STATUS_BASE_IDX 2
#define mmDVMM_FAULT_ADDR 0x0101
#define mmDVMM_FAULT_ADDR_BASE_IDX 2
#define mmFMON_CTRL 0x0102
#define mmFMON_CTRL_BASE_IDX 2
#define mmDVMM_PTE_PGMEM_CONTROL 0x0103
#define mmDVMM_PTE_PGMEM_CONTROL_BASE_IDX 2
#define mmDVMM_PTE_PGMEM_STATE 0x0104
#define mmDVMM_PTE_PGMEM_STATE_BASE_IDX 2
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x0105
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0106
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER 0x0107
#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER 0x0108
#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmDCI_MEM_PWR_CNTL4 0x0109
#define mmDCI_MEM_PWR_CNTL4_BASE_IDX 2
#define mmMCIF_WB_MISC_CTRL 0x010a
#define mmMCIF_WB_MISC_CTRL_BASE_IDX 2
#define mmDCI_MEM_PWR_STATUS3 0x010b
#define mmDCI_MEM_PWR_STATUS3_BASE_IDX 2
#define mmDMIF_CURSOR_CONTROL 0x010c
#define mmDMIF_CURSOR_CONTROL_BASE_IDX 2
#define mmDMIF_CURSOR_MEM_CONTROL 0x010d
#define mmDMIF_CURSOR_MEM_CONTROL_BASE_IDX 2
#define mmDCHUB_FB_LOCATION 0x0126
#define mmDCHUB_FB_LOCATION_BASE_IDX 2
#define mmDCHUB_FB_OFFSET 0x0127
#define mmDCHUB_FB_OFFSET_BASE_IDX 2
#define mmDCHUB_AGP_BASE 0x0128
#define mmDCHUB_AGP_BASE_BASE_IDX 2
#define mmDCHUB_AGP_BOT 0x0129
#define mmDCHUB_AGP_BOT_BASE_IDX 2
#define mmDCHUB_AGP_TOP 0x012a
#define mmDCHUB_AGP_TOP_BASE_IDX 2
#define mmDCHUB_DRAM_APER_BASE 0x012b
#define mmDCHUB_DRAM_APER_BASE_BASE_IDX 2
#define mmDCHUB_DRAM_APER_DEF 0x012c
#define mmDCHUB_DRAM_APER_DEF_BASE_IDX 2
#define mmDCHUB_DRAM_APER_TOP 0x012d
#define mmDCHUB_DRAM_APER_TOP_BASE_IDX 2
#define mmDCHUB_CONTROL_STATUS 0x012e
#define mmDCHUB_CONTROL_STATUS_BASE_IDX 2
#define mmWB_ENABLE 0x0212
#define mmWB_ENABLE_BASE_IDX 2
#define mmWB_EC_CONFIG 0x0213
#define mmWB_EC_CONFIG_BASE_IDX 2
#define mmCNV_MODE 0x0214
#define mmCNV_MODE_BASE_IDX 2
#define mmCNV_WINDOW_START 0x0215
#define mmCNV_WINDOW_START_BASE_IDX 2
#define mmCNV_WINDOW_SIZE 0x0216
#define mmCNV_WINDOW_SIZE_BASE_IDX 2
#define mmCNV_UPDATE 0x0217
#define mmCNV_UPDATE_BASE_IDX 2
#define mmCNV_SOURCE_SIZE 0x0218
#define mmCNV_SOURCE_SIZE_BASE_IDX 2
#define mmCNV_CSC_CONTROL 0x0219
#define mmCNV_CSC_CONTROL_BASE_IDX 2
#define mmCNV_CSC_C11_C12 0x021a
#define mmCNV_CSC_C11_C12_BASE_IDX 2
#define mmCNV_CSC_C13_C14 0x021b
#define mmCNV_CSC_C13_C14_BASE_IDX 2
#define mmCNV_CSC_C21_C22 0x021c
#define mmCNV_CSC_C21_C22_BASE_IDX 2
#define mmCNV_CSC_C23_C24 0x021d
#define mmCNV_CSC_C23_C24_BASE_IDX 2
#define mmCNV_CSC_C31_C32 0x021e
#define mmCNV_CSC_C31_C32_BASE_IDX 2
#define mmCNV_CSC_C33_C34 0x021f
#define mmCNV_CSC_C33_C34_BASE_IDX 2
#define mmCNV_CSC_ROUND_OFFSET_R 0x0220
#define mmCNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
#define mmCNV_CSC_ROUND_OFFSET_G 0x0221
#define mmCNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
#define mmCNV_CSC_ROUND_OFFSET_B 0x0222
#define mmCNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
#define mmCNV_CSC_CLAMP_R 0x0223
#define mmCNV_CSC_CLAMP_R_BASE_IDX 2
#define mmCNV_CSC_CLAMP_G 0x0224
#define mmCNV_CSC_CLAMP_G_BASE_IDX 2
#define mmCNV_CSC_CLAMP_B 0x0225
#define mmCNV_CSC_CLAMP_B_BASE_IDX 2
#define mmCNV_TEST_CNTL 0x0226
#define mmCNV_TEST_CNTL_BASE_IDX 2
#define mmCNV_TEST_CRC_RED 0x0227
#define mmCNV_TEST_CRC_RED_BASE_IDX 2
#define mmCNV_TEST_CRC_GREEN 0x0228
#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2
#define mmCNV_TEST_CRC_BLUE 0x0229
#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2
#define mmCNV_INPUT_SELECT 0x022d
#define mmCNV_INPUT_SELECT_BASE_IDX 2
#define mmWB_SOFT_RESET 0x0230
#define mmWB_SOFT_RESET_BASE_IDX 2
#define mmWB_WARM_UP_MODE_CTL1 0x0231
#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2
#define mmWB_WARM_UP_MODE_CTL2 0x0232
#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2
#define mmWBSCL_COEF_RAM_SELECT 0x0242
#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2
#define mmWBSCL_COEF_RAM_TAP_DATA 0x0243
#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmWBSCL_MODE 0x0244
#define mmWBSCL_MODE_BASE_IDX 2
#define mmWBSCL_TAP_CONTROL 0x0245
#define mmWBSCL_TAP_CONTROL_BASE_IDX 2
#define mmWBSCL_DEST_SIZE 0x0246
#define mmWBSCL_DEST_SIZE_BASE_IDX 2
#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x0247
#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0248
#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0249
#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x024a
#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x024b
#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x024c
#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
#define mmWBSCL_ROUND_OFFSET 0x024d
#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2
#define mmWBSCL_CLAMP 0x024e
#define mmWBSCL_CLAMP_BASE_IDX 2
#define mmWBSCL_OVERFLOW_STATUS 0x024f
#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2
#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0250
#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0251
#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
#define mmWBSCL_TEST_CNTL 0x0252
#define mmWBSCL_TEST_CNTL_BASE_IDX 2
#define mmWBSCL_TEST_CRC_RED 0x0253
#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2
#define mmWBSCL_TEST_CRC_GREEN 0x0254
#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2
#define mmWBSCL_TEST_CRC_BLUE 0x0255
#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2
#define mmWBSCL_BACKPRESSURE_CNT_EN 0x0256
#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
#define mmWB_MCIF_BACKPRESSURE_CNT 0x0257
#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
#define mmWBSCL_RAM_SHUTDOWN 0x025a
#define mmWBSCL_RAM_SHUTDOWN_BASE_IDX 2
#define mmDMCU_CTRL 0x03b6
#define mmDMCU_CTRL_BASE_IDX 2
#define mmDMCU_STATUS 0x03b7
#define mmDMCU_STATUS_BASE_IDX 2
#define mmDMCU_PC_START_ADDR 0x03b8
#define mmDMCU_PC_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_START_ADDR 0x03b9
#define mmDMCU_FW_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_END_ADDR 0x03ba
#define mmDMCU_FW_END_ADDR_BASE_IDX 2
#define mmDMCU_FW_ISR_START_ADDR 0x03bb
#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_CS_HI 0x03bc
#define mmDMCU_FW_CS_HI_BASE_IDX 2
#define mmDMCU_FW_CS_LO 0x03bd
#define mmDMCU_FW_CS_LO_BASE_IDX 2
#define mmDMCU_RAM_ACCESS_CTRL 0x03be
#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_WR_CTRL 0x03bf
#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_WR_DATA 0x03c0
#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
#define mmDMCU_ERAM_RD_CTRL 0x03c1
#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_RD_DATA 0x03c2
#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
#define mmDMCU_IRAM_WR_CTRL 0x03c3
#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
#define mmDMCU_IRAM_WR_DATA 0x03c4
#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
#define mmDMCU_IRAM_RD_CTRL 0x03c5
#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
#define mmDMCU_IRAM_RD_DATA 0x03c6
#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
#define mmDMCU_EVENT_TRIGGER 0x03c7
#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
#define mmDMCU_UC_INTERNAL_INT_STATUS 0x03c8
#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x03c9
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS 0x03ca
#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x03cb
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x03cc
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x03cd
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
#define mmDC_DMCU_SCRATCH 0x03ce
#define mmDC_DMCU_SCRATCH_BASE_IDX 2
#define mmDMCU_INT_CNT 0x03cf
#define mmDMCU_INT_CNT_BASE_IDX 2
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x03d0
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
#define mmDMCU_UC_CLK_GATING_CNTL 0x03d1
#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG1 0x03d2
#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG2 0x03d3
#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG3 0x03d4
#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
#define mmMASTER_COMM_CMD_REG 0x03d5
#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
#define mmMASTER_COMM_CNTL_REG 0x03d6
#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG1 0x03d7
#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG2 0x03d8
#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG3 0x03d9
#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
#define mmSLAVE_COMM_CMD_REG 0x03da
#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
#define mmSLAVE_COMM_CNTL_REG 0x03db
#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x03de
#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
#define mmBL1_PWM_USER_LEVEL 0x03df
#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2
#define mmBL1_PWM_TARGET_ABM_LEVEL 0x03e0
#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x03e1
#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x03e2
#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x03e3
#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
#define mmBL1_PWM_ABM_CNTL 0x03e4
#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2
#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x03e5
#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
#define mmBL1_PWM_GRP2_REG_LOCK 0x03e6
#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x03e7
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x03e8
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS_1 0x03e9
#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x03ea
#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x03eb
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x03ec
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
#define mmDC_ABM1_CNTL 0x03ee
#define mmDC_ABM1_CNTL_BASE_IDX 2
#define mmDC_ABM1_IPCSC_COEFF_SEL 0x03ef
#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x03f0
#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x03f1
#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x03f2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x03f3
#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x03f4
#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
#define mmDC_ABM1_ACE_THRES_12 0x03f5
#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2
#define mmDC_ABM1_ACE_THRES_34 0x03f6
#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2
#define mmDC_ABM1_ACE_CNTL_MISC 0x03f7
#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x03f8
#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x03f9
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x03fa
#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x03fb
#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x03fc
#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x03fd
#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x0400
#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
#define mmDC_ABM1_HG_MISC_CTRL 0x0401
#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2
#define mmDC_ABM1_LS_SUM_OF_LUMA 0x0402
#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x0403
#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0404
#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
#define mmDC_ABM1_LS_PIXEL_COUNT 0x0405
#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x0406
#define mmDC_ABM1_LS_OVR_SCAN_BIN_BASE_IDX 2
#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0407
#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0408
#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0409
#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
#define mmDC_ABM1_HG_SAMPLE_RATE 0x040a
#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
#define mmDC_ABM1_LS_SAMPLE_RATE 0x040b
#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x040c
#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x040d
#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x040e
#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x040f
#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0410
#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_1 0x0411
#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_2 0x0412
#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_3 0x0413
#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_4 0x0414
#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_5 0x0415
#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_6 0x0416
#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_7 0x0417
#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_8 0x0418
#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_9 0x0419
#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_10 0x041a
#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_11 0x041b
#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_12 0x041c
#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_13 0x041d
#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_14 0x041e
#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_15 0x041f
#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_16 0x0420
#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_17 0x0421
#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_18 0x0422
#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_19 0x0423
#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_20 0x0424
#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_21 0x0425
#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_22 0x0426
#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_23 0x0427
#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2
#define mmDC_ABM1_HG_RESULT_24 0x0428
#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0429
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x042a
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x042b
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x042c
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x042d
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x042e
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x042f
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0430
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0431
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x0451
#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_BASE_IDX 2
#define mmDC_ABM1_BL_MASTER_LOCK 0x0452
#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x04bc
#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO 0x04bd
#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO_CONTROL 0x04be
#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
#define mmAZALIA_SOCCLK_CONTROL 0x04bf
#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x04c0
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
#define mmAZALIA_DATA_DMA_CONTROL 0x04c1
#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_BDL_DMA_CONTROL 0x04c2
#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_RIRB_AND_DP_CONTROL 0x04c3
#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
#define mmAZALIA_CORB_DMA_CONTROL 0x04c4
#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x04cb
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x04cc
#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
#define mmAZALIA_GLOBAL_CAPABILITIES 0x04cd
#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x04ce
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x04cf
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x04d0
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL0 0x04d3
#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL1 0x04d4
#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL2 0x04d5
#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL3 0x04d6
#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_RESULT 0x04d7
#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL0 0x04d8
#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL1 0x04d9
#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL2 0x04da
#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL3 0x04db
#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_RESULT 0x04dc
#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL0 0x04dd
#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL1 0x04de
#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL2 0x04df
#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL3 0x04e0
#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_CRC0_RESULT 0x04e1
#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL0 0x04e2
#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL1 0x04e3
#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL2 0x04e4
#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL3 0x04e5
#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_CRC1_RESULT 0x04e6
#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_MEM_PWR_CTRL 0x04e8
#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
#define mmAZALIA_MEM_PWR_STATUS 0x04e9
#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0500
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0501
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0502
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0503
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x0504
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x0505
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x0506
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x0507
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x0508
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x0509
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x050a
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x050b
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x050c
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x050d
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x050f
#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0510
#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0511
#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0512
#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0513
#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x0514
#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x0515
#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x0516
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0517
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
#define mmDAC_ENABLE 0x155a
#define mmDAC_ENABLE_BASE_IDX 2
#define mmDAC_SOURCE_SELECT 0x155b
#define mmDAC_SOURCE_SELECT_BASE_IDX 2
#define mmDAC_CRC_EN 0x155c
#define mmDAC_CRC_EN_BASE_IDX 2
#define mmDAC_CRC_CONTROL 0x155d
#define mmDAC_CRC_CONTROL_BASE_IDX 2
#define mmDAC_CRC_SIG_RGB_MASK 0x155e
#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2
#define mmDAC_CRC_SIG_CONTROL_MASK 0x155f
#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2
#define mmDAC_CRC_SIG_RGB 0x1560
#define mmDAC_CRC_SIG_RGB_BASE_IDX 2
#define mmDAC_CRC_SIG_CONTROL 0x1561
#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2
#define mmDAC_SYNC_TRISTATE_CONTROL 0x1562
#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2
#define mmDAC_STEREOSYNC_SELECT 0x1563
#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2
#define mmDAC_AUTODETECT_CONTROL 0x1564
#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2
#define mmDAC_AUTODETECT_CONTROL2 0x1565
#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2
#define mmDAC_AUTODETECT_CONTROL3 0x1566
#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2
#define mmDAC_AUTODETECT_STATUS 0x1567
#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2
#define mmDAC_AUTODETECT_INT_CONTROL 0x1568
#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2
#define mmDAC_FORCE_OUTPUT_CNTL 0x1569
#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2
#define mmDAC_FORCE_DATA 0x156a
#define mmDAC_FORCE_DATA_BASE_IDX 2
#define mmDAC_POWERDOWN 0x156b
#define mmDAC_POWERDOWN_BASE_IDX 2
#define mmDAC_CONTROL 0x156c
#define mmDAC_CONTROL_BASE_IDX 2
#define mmDAC_COMPARATOR_ENABLE 0x156d
#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2
#define mmDAC_COMPARATOR_OUTPUT 0x156e
#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2
#define mmDAC_PWR_CNTL 0x156f
#define mmDAC_PWR_CNTL_BASE_IDX 2
#define mmDAC_DFT_CONFIG 0x1570
#define mmDAC_DFT_CONFIG_BASE_IDX 2
#define mmDAC_FIFO_STATUS 0x1571
#define mmDAC_FIFO_STATUS_BASE_IDX 2
#define mmDC_I2C_CONTROL 0x1584
#define mmDC_I2C_CONTROL_BASE_IDX 2
#define mmDC_I2C_ARBITRATION 0x1585
#define mmDC_I2C_ARBITRATION_BASE_IDX 2
#define mmDC_I2C_INTERRUPT_CONTROL 0x1586
#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDC_I2C_SW_STATUS 0x1587
#define mmDC_I2C_SW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC1_HW_STATUS 0x1588
#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC2_HW_STATUS 0x1589
#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC3_HW_STATUS 0x158a
#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC4_HW_STATUS 0x158b
#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC5_HW_STATUS 0x158c
#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC6_HW_STATUS 0x158d
#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC1_SPEED 0x158e
#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC1_SETUP 0x158f
#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC2_SPEED 0x1590
#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC2_SETUP 0x1591
#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC3_SPEED 0x1592
#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC3_SETUP 0x1593
#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC4_SPEED 0x1594
#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC4_SETUP 0x1595
#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC5_SPEED 0x1596
#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC5_SETUP 0x1597
#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC6_SPEED 0x1598
#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC6_SETUP 0x1599
#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
#define mmDC_I2C_TRANSACTION0 0x159a
#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
#define mmDC_I2C_TRANSACTION1 0x159b
#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
#define mmDC_I2C_TRANSACTION2 0x159c
#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
#define mmDC_I2C_TRANSACTION3 0x159d
#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
#define mmDC_I2C_DATA 0x159e
#define mmDC_I2C_DATA_BASE_IDX 2
#define mmDC_I2C_DDCVGA_HW_STATUS 0x159f
#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDCVGA_SPEED 0x15a0
#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2
#define mmDC_I2C_DDCVGA_SETUP 0x15a1
#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
#define mmDC_I2C_EDID_DETECT_CTRL 0x15a2
#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x15a3
#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
#define mmGENERIC_I2C_CONTROL 0x15a4
#define mmGENERIC_I2C_CONTROL_BASE_IDX 2
#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x15a5
#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
#define mmGENERIC_I2C_STATUS 0x15a6
#define mmGENERIC_I2C_STATUS_BASE_IDX 2
#define mmGENERIC_I2C_SPEED 0x15a7
#define mmGENERIC_I2C_SPEED_BASE_IDX 2
#define mmGENERIC_I2C_SETUP 0x15a8
#define mmGENERIC_I2C_SETUP_BASE_IDX 2
#define mmGENERIC_I2C_TRANSACTION 0x15a9
#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2
#define mmGENERIC_I2C_DATA 0x15aa
#define mmGENERIC_I2C_DATA_BASE_IDX 2
#define mmGENERIC_I2C_PIN_SELECTION 0x15ab
#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2
#define mmDCO_SCRATCH0 0x15b6
#define mmDCO_SCRATCH0_BASE_IDX 2
#define mmDCO_SCRATCH1 0x15b7
#define mmDCO_SCRATCH1_BASE_IDX 2
#define mmDCO_SCRATCH2 0x15b8
#define mmDCO_SCRATCH2_BASE_IDX 2
#define mmDCO_SCRATCH3 0x15b9
#define mmDCO_SCRATCH3_BASE_IDX 2
#define mmDCO_SCRATCH4 0x15ba
#define mmDCO_SCRATCH4_BASE_IDX 2
#define mmDCO_SCRATCH5 0x15bb
#define mmDCO_SCRATCH5_BASE_IDX 2
#define mmDCO_SCRATCH6 0x15bc
#define mmDCO_SCRATCH6_BASE_IDX 2
#define mmDCO_SCRATCH7 0x15bd
#define mmDCO_SCRATCH7_BASE_IDX 2
#define mmDCE_VCE_CONTROL 0x15be
#define mmDCE_VCE_CONTROL_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS 0x15bf
#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x15c0
#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x15c1
#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x15c2
#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x15c3
#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x15c4
#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x15c5
#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x15c6
#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x15c7
#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x15c8
#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
#define mmDCO_MEM_PWR_STATUS 0x15c9
#define mmDCO_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCO_MEM_PWR_CTRL 0x15ca
#define mmDCO_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCO_MEM_PWR_CTRL2 0x15cb
#define mmDCO_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDCO_CLK_CNTL 0x15cc
#define mmDCO_CLK_CNTL_BASE_IDX 2
#define mmDCO_POWER_MANAGEMENT_CNTL 0x15d0
#define mmDCO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
#define mmDIG_SOFT_RESET_2 0x15d2
#define mmDIG_SOFT_RESET_2_BASE_IDX 2
#define mmDCO_STEREOSYNC_SEL 0x15d6
#define mmDCO_STEREOSYNC_SEL_BASE_IDX 2
#define mmDCO_SOFT_RESET 0x15d9
#define mmDCO_SOFT_RESET_BASE_IDX 2
#define mmDIG_SOFT_RESET 0x15da
#define mmDIG_SOFT_RESET_BASE_IDX 2
#define mmDCO_MEM_PWR_STATUS1 0x15dc
#define mmDCO_MEM_PWR_STATUS1_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x15dd
#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
#define mmDCO_CLK_CNTL2 0x15de
#define mmDCO_CLK_CNTL2_BASE_IDX 2
#define mmDCO_CLK_CNTL3 0x15df
#define mmDCO_CLK_CNTL3_BASE_IDX 2
#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0x15eb
#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
#define mmDCO_PSP_INTERRUPT_STATUS 0x15ec
#define mmDCO_PSP_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCO_PSP_INTERRUPT_CLEAR 0x15ed
#define mmDCO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
#define mmDCO_GENERIC_INTERRUPT_MESSAGE 0x15ee
#define mmDCO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
#define mmDCO_GENERIC_INTERRUPT_CLEAR 0x15ef
#define mmDCO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
#define mmFMT_MEMORY0_CONTROL 0x15f0
#define mmFMT_MEMORY0_CONTROL_BASE_IDX 2
#define mmFMT_MEMORY1_CONTROL 0x15f1
#define mmFMT_MEMORY1_CONTROL_BASE_IDX 2
#define mmFMT_MEMORY2_CONTROL 0x15f2
#define mmFMT_MEMORY2_CONTROL_BASE_IDX 2
#define mmFMT_MEMORY3_CONTROL 0x15f3
#define mmFMT_MEMORY3_CONTROL_BASE_IDX 2
#define mmFMT_MEMORY4_CONTROL 0x15f4
#define mmFMT_MEMORY4_CONTROL_BASE_IDX 2
#define mmFMT_MEMORY5_CONTROL 0x15f5
#define mmFMT_MEMORY5_CONTROL_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x15f6
#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
#define mmDC_GENERICA 0x207e
#define mmDC_GENERICA_BASE_IDX 2
#define mmDC_GENERICB 0x207f
#define mmDC_GENERICB_BASE_IDX 2
#define mmDC_PAD_EXTERN_SIG 0x2080
#define mmDC_PAD_EXTERN_SIG_BASE_IDX 2
#define mmDC_REF_CLK_CNTL 0x2081
#define mmDC_REF_CLK_CNTL_BASE_IDX 2
#define mmDC_GPIO_DEBUG 0x2082
#define mmDC_GPIO_DEBUG_BASE_IDX 2
#define mmUNIPHYA_LINK_CNTL 0x2083
#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x2084
#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYB_LINK_CNTL 0x2085
#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2086
#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYC_LINK_CNTL 0x2087
#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2088
#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYD_LINK_CNTL 0x2089
#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x208a
#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYE_LINK_CNTL 0x208b
#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x208c
#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYF_LINK_CNTL 0x208d
#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x208e
#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYG_LINK_CNTL 0x208f
#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x2090
#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmDCIO_WRCMD_DELAY 0x2094
#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
#define mmDC_PINSTRAPS 0x2096
#define mmDC_PINSTRAPS_BASE_IDX 2
#define mmCC_DC_MISC_STRAPS 0x2097
#define mmCC_DC_MISC_STRAPS_BASE_IDX 2
#define mmDC_DVODATA_CONFIG 0x2098
#define mmDC_DVODATA_CONFIG_BASE_IDX 2
#define mmLVTMA_PWRSEQ_CNTL 0x2099
#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
#define mmLVTMA_PWRSEQ_STATE 0x209a
#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
#define mmLVTMA_PWRSEQ_REF_DIV 0x209b
#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
#define mmLVTMA_PWRSEQ_DELAY1 0x209c
#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
#define mmLVTMA_PWRSEQ_DELAY2 0x209d
#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
#define mmBL_PWM_CNTL 0x209e
#define mmBL_PWM_CNTL_BASE_IDX 2
#define mmBL_PWM_CNTL2 0x209f
#define mmBL_PWM_CNTL2_BASE_IDX 2
#define mmBL_PWM_PERIOD_CNTL 0x20a0
#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
#define mmBL_PWM_GRP1_REG_LOCK 0x20a1
#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
#define mmDCIO_GSL_GENLK_PAD_CNTL 0x20a2
#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x20a3
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
#define mmDCIO_GSL0_CNTL 0x20a4
#define mmDCIO_GSL0_CNTL_BASE_IDX 2
#define mmDCIO_GSL1_CNTL 0x20a5
#define mmDCIO_GSL1_CNTL_BASE_IDX 2
#define mmDCIO_GSL2_CNTL 0x20a6
#define mmDCIO_GSL2_CNTL_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x20a7
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x20a8
#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_BASE_IDX 2
#define mmDC_GPU_TIMER_READ 0x20a9
#define mmDC_GPU_TIMER_READ_BASE_IDX 2
#define mmDC_GPU_TIMER_READ_CNTL 0x20aa
#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
#define mmDCIO_CLOCK_CNTL 0x20ab
#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x20ae
#define mmDCO_DCFE_EXT_VSYNC_CNTL_BASE_IDX 2
#define mmDCIO_SOFT_RESET 0x20b4
#define mmDCIO_SOFT_RESET_BASE_IDX 2
#define mmDCIO_DPHY_SEL 0x20b5
#define mmDCIO_DPHY_SEL_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKA 0x20b6
#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKB 0x20b7
#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PERIOD 0x20b8
#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2
#define mmAUXP_IMPCAL 0x20b9
#define mmAUXP_IMPCAL_BASE_IDX 2
#define mmAUXN_IMPCAL 0x20ba
#define mmAUXN_IMPCAL_BASE_IDX 2
#define mmDCIO_IMPCAL_CNTL 0x20bb
#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PSW_AB 0x20bc
#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKC 0x20bd
#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKD 0x20be
#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2
#define mmDCIO_IMPCAL_CNTL_CD 0x20bf
#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PSW_CD 0x20c0
#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKE 0x20c1
#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKF 0x20c2
#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2
#define mmDCIO_IMPCAL_CNTL_EF 0x20c3
#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PSW_EF 0x20c4
#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2
#define mmUNIPHYLPA_LINK_CNTL 0x20c5
#define mmUNIPHYLPA_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYLPB_LINK_CNTL 0x20c6
#define mmUNIPHYLPB_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x20c7
#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x20c8
#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmDCIO_DPCS_TX_INTERRUPT 0x20c9
#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2
#define mmDCIO_DPCS_RX_INTERRUPT 0x20ca
#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2
#define mmDCIO_SEMAPHORE0 0x20cb
#define mmDCIO_SEMAPHORE0_BASE_IDX 2
#define mmDCIO_SEMAPHORE1 0x20cc
#define mmDCIO_SEMAPHORE1_BASE_IDX 2
#define mmDCIO_SEMAPHORE2 0x20cd
#define mmDCIO_SEMAPHORE2_BASE_IDX 2
#define mmDCIO_SEMAPHORE3 0x20ce
#define mmDCIO_SEMAPHORE3_BASE_IDX 2
#define mmDCIO_SEMAPHORE4 0x20cf
#define mmDCIO_SEMAPHORE4_BASE_IDX 2
#define mmDCIO_SEMAPHORE5 0x20d0
#define mmDCIO_SEMAPHORE5_BASE_IDX 2
#define mmDCIO_SEMAPHORE6 0x20d1
#define mmDCIO_SEMAPHORE6_BASE_IDX 2
#define mmDCIO_SEMAPHORE7 0x20d2
#define mmDCIO_SEMAPHORE7_BASE_IDX 2
#define mmDC_GPIO_GENERIC_MASK 0x20de
#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
#define mmDC_GPIO_GENERIC_A 0x20df
#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
#define mmDC_GPIO_GENERIC_EN 0x20e0
#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
#define mmDC_GPIO_GENERIC_Y 0x20e1
#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
#define mmDC_GPIO_DVODATA_MASK 0x20e2
#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2
#define mmDC_GPIO_DVODATA_A 0x20e3
#define mmDC_GPIO_DVODATA_A_BASE_IDX 2
#define mmDC_GPIO_DVODATA_EN 0x20e4
#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2
#define mmDC_GPIO_DVODATA_Y 0x20e5
#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2
#define mmDC_GPIO_DDC1_MASK 0x20e6
#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC1_A 0x20e7
#define mmDC_GPIO_DDC1_A_BASE_IDX 2
#define mmDC_GPIO_DDC1_EN 0x20e8
#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
#define mmDC_GPIO_DDC1_Y 0x20e9
#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
#define mmDC_GPIO_DDC2_MASK 0x20ea
#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC2_A 0x20eb
#define mmDC_GPIO_DDC2_A_BASE_IDX 2
#define mmDC_GPIO_DDC2_EN 0x20ec
#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
#define mmDC_GPIO_DDC2_Y 0x20ed
#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
#define mmDC_GPIO_DDC3_MASK 0x20ee
#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC3_A 0x20ef
#define mmDC_GPIO_DDC3_A_BASE_IDX 2
#define mmDC_GPIO_DDC3_EN 0x20f0
#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
#define mmDC_GPIO_DDC3_Y 0x20f1
#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
#define mmDC_GPIO_DDC4_MASK 0x20f2
#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC4_A 0x20f3
#define mmDC_GPIO_DDC4_A_BASE_IDX 2
#define mmDC_GPIO_DDC4_EN 0x20f4
#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
#define mmDC_GPIO_DDC4_Y 0x20f5
#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
#define mmDC_GPIO_DDC5_MASK 0x20f6
#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC5_A 0x20f7
#define mmDC_GPIO_DDC5_A_BASE_IDX 2
#define mmDC_GPIO_DDC5_EN 0x20f8
#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
#define mmDC_GPIO_DDC5_Y 0x20f9
#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
#define mmDC_GPIO_DDC6_MASK 0x20fa
#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC6_A 0x20fb
#define mmDC_GPIO_DDC6_A_BASE_IDX 2
#define mmDC_GPIO_DDC6_EN 0x20fc
#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
#define mmDC_GPIO_DDC6_Y 0x20fd
#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_MASK 0x20fe
#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_A 0x20ff
#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_EN 0x2100
#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_Y 0x2101
#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
#define mmDC_GPIO_SYNCA_MASK 0x2102
#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2
#define mmDC_GPIO_SYNCA_A 0x2103
#define mmDC_GPIO_SYNCA_A_BASE_IDX 2
#define mmDC_GPIO_SYNCA_EN 0x2104
#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2
#define mmDC_GPIO_SYNCA_Y 0x2105
#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2
#define mmDC_GPIO_GENLK_MASK 0x2106
#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
#define mmDC_GPIO_GENLK_A 0x2107
#define mmDC_GPIO_GENLK_A_BASE_IDX 2
#define mmDC_GPIO_GENLK_EN 0x2108
#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
#define mmDC_GPIO_GENLK_Y 0x2109
#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
#define mmDC_GPIO_HPD_MASK 0x210a
#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
#define mmDC_GPIO_HPD_A 0x210b
#define mmDC_GPIO_HPD_A_BASE_IDX 2
#define mmDC_GPIO_HPD_EN 0x210c
#define mmDC_GPIO_HPD_EN_BASE_IDX 2
#define mmDC_GPIO_HPD_Y 0x210d
#define mmDC_GPIO_HPD_Y_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_MASK 0x210e
#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_A 0x210f
#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_EN 0x2110
#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_Y 0x2111
#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
#define mmDC_GPIO_PAD_STRENGTH_1 0x2112
#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
#define mmDC_GPIO_PAD_STRENGTH_2 0x2113
#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
#define mmPHY_AUX_CNTL 0x2115
#define mmPHY_AUX_CNTL_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_MASK 0x2116
#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_A 0x2117
#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_EN 0x2118
#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_Y 0x2119
#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_STRENGTH 0x211a
#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2
#define mmDVO_STRENGTH_CONTROL 0x211b
#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2
#define mmDVO_VREF_CONTROL 0x211c
#define mmDVO_VREF_CONTROL_BASE_IDX 2
#define mmDVO_SKEW_ADJUST 0x211d
#define mmDVO_SKEW_ADJUST_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_MASK 0x2126
#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_A 0x2127
#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_EN 0x2128
#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_Y 0x2129
#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x212a
#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2
#define mmDC_GPIO_TX12_EN 0x212b
#define mmDC_GPIO_TX12_EN_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_0 0x212c
#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_1 0x212d
#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_2 0x212e
#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
#define mmDC_GPIO_RXEN 0x212f
#define mmDC_GPIO_RXEN_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_3 0x2130
#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_4 0x2131
#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_5 0x2132
#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2
#define mmAUXI2C_PAD_ALL_PWR_OK 0x2133
#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
#define mmDC_GPIO_PULLUPEN 0x2134
#define mmDC_GPIO_PULLUPEN_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_6 0x2135
#define mmDC_GPIO_AUX_CTRL_6_BASE_IDX 2
#define mmBPHYC_DAC_MACRO_CNTL 0x2136
#define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED0 0x2136
#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x2137
#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED1 0x2137
#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED2 0x2138
#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED3 0x2139
#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDISP_DSI_DUAL_CTRL 0x277e
#define mmDISP_DSI_DUAL_CTRL_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED0 0x283e
#define mmDPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED1 0x283f
#define mmDPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED2 0x2840
#define mmDPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED3 0x2841
#define mmDPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED4 0x2842
#define mmDPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED5 0x2843
#define mmDPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED6 0x2844
#define mmDPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED7 0x2845
#define mmDPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED8 0x2846
#define mmDPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED9 0x2847
#define mmDPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED10 0x2848
#define mmDPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED11 0x2849
#define mmDPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED12 0x284a
#define mmDPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED13 0x284b
#define mmDPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED14 0x284c
#define mmDPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED15 0x284d
#define mmDPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED16 0x284e
#define mmDPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED17 0x284f
#define mmDPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED18 0x2850
#define mmDPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED19 0x2851
#define mmDPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED20 0x2852
#define mmDPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED21 0x2853
#define mmDPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED22 0x2854
#define mmDPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED23 0x2855
#define mmDPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED24 0x2856
#define mmDPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED25 0x2857
#define mmDPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED26 0x2858
#define mmDPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED27 0x2859
#define mmDPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED28 0x285a
#define mmDPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED29 0x285b
#define mmDPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED30 0x285c
#define mmDPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED31 0x285d
#define mmDPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED32 0x285e
#define mmDPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED33 0x285f
#define mmDPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED34 0x2860
#define mmDPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED35 0x2861
#define mmDPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED36 0x2862
#define mmDPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED37 0x2863
#define mmDPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED38 0x2864
#define mmDPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED39 0x2865
#define mmDPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED40 0x2866
#define mmDPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED41 0x2867
#define mmDPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED42 0x2868
#define mmDPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED43 0x2869
#define mmDPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED44 0x286a
#define mmDPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED45 0x286b
#define mmDPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED46 0x286c
#define mmDPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED47 0x286d
#define mmDPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED48 0x286e
#define mmDPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED49 0x286f
#define mmDPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED50 0x2870
#define mmDPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED51 0x2871
#define mmDPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED52 0x2872
#define mmDPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED53 0x2873
#define mmDPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED54 0x2874
#define mmDPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED55 0x2875
#define mmDPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED56 0x2876
#define mmDPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED57 0x2877
#define mmDPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED58 0x2878
#define mmDPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED59 0x2879
#define mmDPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED60 0x287a
#define mmDPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED61 0x287b
#define mmDPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED62 0x287c
#define mmDPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDPHY_MACRO_CNTL_RESERVED63 0x287d
#define mmDPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDPRX_AUX_REFERENCE_PULSE_DIV 0x2a7e
#define mmDPRX_AUX_REFERENCE_PULSE_DIV_BASE_IDX 2
#define mmDPRX_AUX_CONTROL 0x2a7f
#define mmDPRX_AUX_CONTROL_BASE_IDX 2
#define mmDPRX_AUX_HPD_CONTROL1 0x2a80
#define mmDPRX_AUX_HPD_CONTROL1_BASE_IDX 2
#define mmDPRX_AUX_HPD_CONTROL2 0x2a81
#define mmDPRX_AUX_HPD_CONTROL2_BASE_IDX 2
#define mmDPRX_AUX_RX_STATUS 0x2a82
#define mmDPRX_AUX_RX_STATUS_BASE_IDX 2
#define mmDPRX_AUX_RX_ERROR_MASK 0x2a83
#define mmDPRX_AUX_RX_ERROR_MASK_BASE_IDX 2
#define mmDPRX_AUX_DPHY_TX_REF_CONTROL 0x2a84
#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDPRX_AUX_DPHY_TX_CONTROL 0x2a85
#define mmDPRX_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDPRX_AUX_DPHY_RX_CONTROL0 0x2a86
#define mmDPRX_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDPRX_AUX_DPHY_RX_CONTROL1 0x2a87
#define mmDPRX_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDPRX_AUX_DPHY_TX_STATUS 0x2a88
#define mmDPRX_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDPRX_AUX_DPHY_RX_STATUS 0x2a89
#define mmDPRX_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDPRX_AUX_DMCU_HW_INT_STATUS 0x2a8a
#define mmDPRX_AUX_DMCU_HW_INT_STATUS_BASE_IDX 2
#define mmDPRX_AUX_DMCU_HW_INT_ACK 0x2a8b
#define mmDPRX_AUX_DMCU_HW_INT_ACK_BASE_IDX 2
#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1 0x2a8c
#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_BASE_IDX 2
#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2 0x2a8d
#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_BASE_IDX 2
#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1 0x2a8e
#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_BASE_IDX 2
#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2 0x2a8f
#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_BASE_IDX 2
#define mmDPRX_AUX_AUX_BUF_INDEX 0x2a90
#define mmDPRX_AUX_AUX_BUF_INDEX_BASE_IDX 2
#define mmDPRX_AUX_AUX_BUF_DATA 0x2a91
#define mmDPRX_AUX_AUX_BUF_DATA_BASE_IDX 2
#define mmDPRX_AUX_EDID_INDEX 0x2a92
#define mmDPRX_AUX_EDID_INDEX_BASE_IDX 2
#define mmDPRX_AUX_EDID_DATA 0x2a93
#define mmDPRX_AUX_EDID_DATA_BASE_IDX 2
#define mmDPRX_AUX_DPCD_INDEX1 0x2a94
#define mmDPRX_AUX_DPCD_INDEX1_BASE_IDX 2
#define mmDPRX_AUX_DPCD_DATA1 0x2a95
#define mmDPRX_AUX_DPCD_DATA1_BASE_IDX 2
#define mmDPRX_AUX_DPCD_INDEX2 0x2a96
#define mmDPRX_AUX_DPCD_INDEX2_BASE_IDX 2
#define mmDPRX_AUX_DPCD_DATA2 0x2a97
#define mmDPRX_AUX_DPCD_DATA2_BASE_IDX 2
#define mmDPRX_AUX_MSG_INDEX1 0x2a98
#define mmDPRX_AUX_MSG_INDEX1_BASE_IDX 2
#define mmDPRX_AUX_MSG_DATA1 0x2a99
#define mmDPRX_AUX_MSG_DATA1_BASE_IDX 2
#define mmDPRX_AUX_MSG_INDEX2 0x2a9a
#define mmDPRX_AUX_MSG_INDEX2_BASE_IDX 2
#define mmDPRX_AUX_MSG_DATA2 0x2a9b
#define mmDPRX_AUX_MSG_DATA2_BASE_IDX 2
#define mmDPRX_AUX_KSV_INDEX1 0x2a9c
#define mmDPRX_AUX_KSV_INDEX1_BASE_IDX 2
#define mmDPRX_AUX_KSV_DATA1 0x2a9d
#define mmDPRX_AUX_KSV_DATA1_BASE_IDX 2
#define mmDPRX_AUX_KSV_INDEX2 0x2a9e
#define mmDPRX_AUX_KSV_INDEX2_BASE_IDX 2
#define mmDPRX_AUX_KSV_DATA2 0x2a9f
#define mmDPRX_AUX_KSV_DATA2_BASE_IDX 2
#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL 0x2aa0
#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_BASE_IDX 2
#define mmDPRX_AUX_MSG_BUF_CONTROL1 0x2aa1
#define mmDPRX_AUX_MSG_BUF_CONTROL1_BASE_IDX 2
#define mmDPRX_AUX_MSG_BUF_CONTROL2 0x2aa2
#define mmDPRX_AUX_MSG_BUF_CONTROL2_BASE_IDX 2
#define mmDPRX_AUX_SCRATCH1 0x2aa3
#define mmDPRX_AUX_SCRATCH1_BASE_IDX 2
#define mmDPRX_AUX_SCRATCH2 0x2aa4
#define mmDPRX_AUX_SCRATCH2_BASE_IDX 2
#define mmDPRX_AUX_MSG1_PENDING 0x2aa5
#define mmDPRX_AUX_MSG1_PENDING_BASE_IDX 2
#define mmDPRX_AUX_MSG2_PENDING 0x2aa6
#define mmDPRX_AUX_MSG2_PENDING_BASE_IDX 2
#define mmDPRX_AUX_MSG3_PENDING 0x2aa7
#define mmDPRX_AUX_MSG3_PENDING_BASE_IDX 2
#define mmDPRX_AUX_MSG4_PENDING 0x2aa8
#define mmDPRX_AUX_MSG4_PENDING_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET 0x2afe
#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET 0x2aff
#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_MSTM_CTRL 0x2b00
#define mmDPRX_DPHY_DPCD_MSTM_CTRL_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET 0x2b01
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS 0x2b02
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET 0x2b03
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS 0x2b04
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET 0x2b05
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS 0x2b06
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET 0x2b07
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_BASE_IDX 2
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS 0x2b08
#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_READY 0x2b09
#define mmDPRX_DPHY_READY_BASE_IDX 2
#define mmDPRX_DPHY_COMMA_STATUS 0x2b0b
#define mmDPRX_DPHY_COMMA_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED 0x2b0c
#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_BASE_IDX 2
#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED 0x2b0d
#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0 0x2b0f
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0 0x2b11
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0 0x2b12
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0 0x2b13
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1 0x2b14
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1 0x2b16
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1 0x2b17
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1 0x2b18
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2 0x2b19
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2 0x2b1b
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2 0x2b1c
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2 0x2b1d
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3 0x2b1e
#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3 0x2b20
#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3 0x2b21
#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_BASE_IDX 2
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3 0x2b22
#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_BASE_IDX 2
#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL 0x2b24
#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_BASE_IDX 2
#define mmDPRX_DPHY_SR_ERROR_COUNT_A 0x2b25
#define mmDPRX_DPHY_SR_ERROR_COUNT_A_BASE_IDX 2
#define mmDPRX_DPHY_BS_ERROR_COUNT_A 0x2b27
#define mmDPRX_DPHY_BS_ERROR_COUNT_A_BASE_IDX 2
#define mmDPRX_DPHY_BS_ERROR_COUNT_B 0x2b28
#define mmDPRX_DPHY_BS_ERROR_COUNT_B_BASE_IDX 2
#define mmDPRX_DPHY_LANESETUP0 0x2b2d
#define mmDPRX_DPHY_LANESETUP0_BASE_IDX 2
#define mmDPRX_DPHY_LANESETUP1 0x2b2e
#define mmDPRX_DPHY_LANESETUP1_BASE_IDX 2
#define mmDPRX_DPHY_LFSRADV 0x2b31
#define mmDPRX_DPHY_LFSRADV_BASE_IDX 2
#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT 0x2b32
#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_BASE_IDX 2
#define mmDPRX_DPHY_SET_ENABLE 0x2b33
#define mmDPRX_DPHY_SET_ENABLE_BASE_IDX 2
#define mmDPRX_DPHY_ECF_LSB 0x2b34
#define mmDPRX_DPHY_ECF_LSB_BASE_IDX 2
#define mmDPRX_DPHY_ECF_MSB 0x2b35
#define mmDPRX_DPHY_ECF_MSB_BASE_IDX 2
#define mmDPRX_DPHY_ENHANCED_FRAME_EN 0x2b36
#define mmDPRX_DPHY_ENHANCED_FRAME_EN_BASE_IDX 2
#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE 0x2b3c
#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_BASE_IDX 2
#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA 0x2b3d
#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_BASE_IDX 2
#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL 0x2b3e
#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_BASE_IDX 2
#define mmDPRX_DPHY_BYPASS 0x2b3f
#define mmDPRX_DPHY_BYPASS_BASE_IDX 2
#define mmDPRX_DPHY_INT_RESET 0x2b40
#define mmDPRX_DPHY_INT_RESET_BASE_IDX 2
#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS 0x2b41
#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS 0x2b43
#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS 0x2b44
#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS 0x2b46
#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS 0x2b48
#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS 0x2b49
#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS 0x2b4a
#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS 0x2b4b
#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS 0x2b4c
#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_BASE_IDX 2
#define mmDPRX_DPHY_SPARE 0x2b4d
#define mmDPRX_DPHY_SPARE_BASE_IDX 2
#define mmDCRX_GATE_DISABLE_CNTL 0x2b6e
#define mmDCRX_GATE_DISABLE_CNTL_BASE_IDX 2
#define mmDCRX_SOFT_RESET 0x2b6f
#define mmDCRX_SOFT_RESET_BASE_IDX 2
#define mmDCRX_LIGHT_SLEEP_CNTL 0x2b70
#define mmDCRX_LIGHT_SLEEP_CNTL_BASE_IDX 2
#define mmDCRX_DISPCLK_GATE_CNTL 0x2b73
#define mmDCRX_DISPCLK_GATE_CNTL_BASE_IDX 2
#define mmDCRX_CLK_CNTL 0x2b74
#define mmDCRX_CLK_CNTL_BASE_IDX 2
#define mmDCRX_TEST_CLK_CNTL 0x2b75
#define mmDCRX_TEST_CLK_CNTL_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x2c06
#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x2c07
#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x2c08
#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x2c09
#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x2c0a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x2c0b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x2c0c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x2c0d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x2c0e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x2c0f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x2c10
#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x2c11
#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x2c12
#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x2c13
#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x2c14
#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x2c15
#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x2c16
#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x2c17
#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x2c18
#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x2c19
#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x2c1a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x2c1b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x2c1c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x2c1d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x2c1e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x2c1f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x2c20
#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x2c21
#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x2c22
#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x2c23
#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x2c24
#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x2c25
#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x2c26
#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x2c27
#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x2c28
#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x2c29
#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x2c2a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x2c2b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x2c2c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x2c2d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x2c2e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x2c2f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x2c30
#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x2c31
#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x2c32
#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x2c33
#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x2c34
#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x2c35
#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x2c36
#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x2c37
#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x2c38
#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x2c39
#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x2c3a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x2c3b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x2c3c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x2c3d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x2c3e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x2c3f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x2c40
#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x2c41
#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x2c42
#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x2c43
#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x2c44
#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x2c45
#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x2c46
#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x2c47
#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x2c48
#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x2c49
#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x2c4a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x2c4b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x2c4c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x2c4d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x2c4e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x2c4f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x2c50
#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x2c51
#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x2c52
#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x2c53
#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x2c54
#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x2c55
#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x2c56
#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x2c57
#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x2c58
#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x2c59
#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x2c5a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x2c5b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x2c5c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x2c5d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x2c5e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x2c5f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x2c60
#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x2c61
#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x2c62
#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x2c63
#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x2c64
#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x2c65
#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x2c66
#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x2c67
#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x2c68
#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x2c69
#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x2c6a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x2c6b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x2c6c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x2c6d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x2c6e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x2c6f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x2c70
#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x2c71
#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x2c72
#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x2c73
#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x2c74
#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x2c75
#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x2c76
#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x2c77
#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x2c78
#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x2c79
#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x2c7a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x2c7b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x2c7c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x2c7d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x2c7e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x2c7f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x2c80
#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x2c81
#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x2c82
#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x2c83
#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x2c84
#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x2c85
#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x2c86
#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x2c87
#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x2c88
#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x2c89
#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x2c8a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x2c8b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x2c8c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x2c8d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x2c8e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x2c8f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x2c90
#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x2c91
#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x2c92
#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x2c93
#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x2c94
#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x2c95
#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x2c96
#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x2c97
#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x2c98
#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x2c99
#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x2c9a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x2c9b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x2c9c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x2c9d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x2c9e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x2c9f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x2ca0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x2ca1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x2ca2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x2ca3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x2ca4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x2ca5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x2ca6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x2ca7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x2ca8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x2ca9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x2caa
#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x2cab
#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x2cac
#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x2cad
#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x2cae
#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x2caf
#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x2cb0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x2cb1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x2cb2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x2cb3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x2cb4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x2cb5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x2cb6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x2cb7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x2cb8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x2cb9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x2cba
#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x2cbb
#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x2cbc
#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x2cbd
#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x2cbe
#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x2cbf
#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x2cc0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x2cc1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x2cc2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x2cc3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x2cc4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x2cc5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x2cc6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x2cc7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x2cc8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x2cc9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x2cca
#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x2ccb
#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x2ccc
#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x2ccd
#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x2cce
#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x2ccf
#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x2cd0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x2cd1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x2cd2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x2cd3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x2cd4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x2cd5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x2cd6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x2cd7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x2cd8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x2cd9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x2cda
#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x2cdb
#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x2cdc
#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x2cdd
#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x2cde
#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x2cdf
#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x2ce0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x2ce1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x2ce2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x2ce3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x2ce4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x2ce5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x2ce6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x2ce7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x2ce8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x2ce9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x2cea
#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x2ceb
#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x2cec
#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x2ced
#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x2cee
#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x2cef
#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x2cf0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x2cf1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x2cf2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x2cf3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x2cf4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x2cf5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x2cf6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x2cf7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x2cf8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x2cf9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x2cfa
#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x2cfb
#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x2cfc
#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x2cfd
#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x2cfe
#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x2cff
#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x2d00
#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x2d01
#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x2d02
#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x2d03
#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x2d04
#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x2d05
#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x2d06
#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x2d07
#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x2d08
#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x2d09
#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x2d0a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x2d0b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x2d0c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x2d0d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x2d0e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x2d0f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x2d10
#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x2d11
#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x2d12
#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x2d13
#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x2d14
#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x2d15
#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x2d16
#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x2d17
#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x2d18
#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x2d19
#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x2d1a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x2d1b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x2d1c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x2d1d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x2d1e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x2d1f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x2d20
#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x2d21
#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x2d22
#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x2d23
#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x2d24
#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x2d25
#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x2d26
#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x2d27
#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x2d28
#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x2d29
#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x2d2a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x2d2b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x2d2c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x2d2d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x2d2e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x2d2f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x2d30
#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x2d31
#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x2d32
#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x2d33
#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x2d34
#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x2d35
#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x2d36
#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x2d37
#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x2d38
#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x2d39
#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x2d3a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x2d3b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x2d3c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x2d3d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x2d3e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x2d3f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x2d40
#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x2d41
#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x2d42
#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x2d43
#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x2d44
#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x2d45
#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x2d46
#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x2d47
#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x2d48
#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x2d49
#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x2d4a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x2d4b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x2d4c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x2d4d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x2d4e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x2d4f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x2d50
#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x2d51
#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x2d52
#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x2d53
#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x2d54
#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x2d55
#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x2d56
#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x2d57
#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x2d58
#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x2d59
#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x2d5a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x2d5b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x2d5c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x2d5d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x2d5e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x2d5f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x2d60
#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x2d61
#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x2d62
#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x2d63
#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x2d64
#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x2d65
#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x2d66
#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x2d67
#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x2d68
#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x2d69
#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x2d6a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x2d6b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x2d6c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x2d6d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x2d6e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x2d6f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x2d70
#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x2d71
#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x2d72
#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x2d73
#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x2d74
#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x2d75
#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x2d76
#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x2d77
#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x2d78
#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x2d79
#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x2d7a
#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x2d7b
#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x2d7c
#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x2d7d
#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x2d7e
#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x2d7f
#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x2d80
#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_BASE_IDX 2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x2d81
#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_BASE_IDX 2
#define mmI2S0_CNTL 0x2d82
#define mmI2S0_CNTL_BASE_IDX 2
#define mmSPDIF0_CNTL 0x2d83
#define mmSPDIF0_CNTL_BASE_IDX 2
#define mmI2S1_CNTL 0x2d84
#define mmI2S1_CNTL_BASE_IDX 2
#define mmSPDIF1_CNTL 0x2d85
#define mmSPDIF1_CNTL_BASE_IDX 2
#define mmI2S0_STATUS 0x2d86
#define mmI2S0_STATUS_BASE_IDX 2
#define mmI2S1_STATUS 0x2d87
#define mmI2S1_STATUS_BASE_IDX 2
#define mmI2S0_CRC_TEST_CNTL 0x2d8a
#define mmI2S0_CRC_TEST_CNTL_BASE_IDX 2
#define mmI2S0_CRC_TEST_DATA_01 0x2d8b
#define mmI2S0_CRC_TEST_DATA_01_BASE_IDX 2
#define mmI2S0_CRC_TEST_DATA_23 0x2d8c
#define mmI2S0_CRC_TEST_DATA_23_BASE_IDX 2
#define mmI2S1_CRC_TEST_CNTL 0x2d8d
#define mmI2S1_CRC_TEST_CNTL_BASE_IDX 2
#define mmI2S1_CRC_TEST_DATA_0 0x2d8e
#define mmI2S1_CRC_TEST_DATA_0_BASE_IDX 2
#define mmSPDIF0_CRC_TEST_CNTL 0x2d8f
#define mmSPDIF0_CRC_TEST_CNTL_BASE_IDX 2
#define mmSPDIF0_CRC_TEST_DATA_0 0x2d90
#define mmSPDIF0_CRC_TEST_DATA_0_BASE_IDX 2
#define mmSPDIF1_CRC_TEST_CNTL 0x2d91
#define mmSPDIF1_CRC_TEST_CNTL_BASE_IDX 2
#define mmSPDIF1_CRC_TEST_DATA 0x2d92
#define mmSPDIF1_CRC_TEST_DATA_BASE_IDX 2
#define mmCRC_I2S_CONT_REPEAT_NUM 0x2d93
#define mmCRC_I2S_CONT_REPEAT_NUM_BASE_IDX 2
#define mmCRC_SPDIF_CONT_REPEAT_NUM 0x2d94
#define mmCRC_SPDIF_CONT_REPEAT_NUM_BASE_IDX 2
#define mmZCAL_MACRO_CNTL_RESERVED0 0x2d96
#define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmZCAL_MACRO_CNTL_RESERVED1 0x2d97
#define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmZCAL_MACRO_CNTL_RESERVED2 0x2d98
#define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmZCAL_MACRO_CNTL_RESERVED3 0x2d99
#define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmZCAL_MACRO_CNTL_RESERVED4 0x2d9a
#define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2
// addressBlock: dce_dc_azf0stream0_dispdec
// base address: 0x0
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x0458
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x0459
#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream1_dispdec
// base address: 0x8
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x045a
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x045b
#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream2_dispdec
// base address: 0x10
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x045c
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x045d
#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream3_dispdec
// base address: 0x18
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x045e
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x045f
#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream4_dispdec
// base address: 0x20
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0460
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0461
#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream5_dispdec
// base address: 0x28
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0462
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0463
#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream6_dispdec
// base address: 0x30
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x0464
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x0465
#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream7_dispdec
// base address: 0x38
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x0466
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x0467
#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0endpoint0_dispdec
// base address: 0x0
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0480
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0481
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0endpoint1_dispdec
// base address: 0x18
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0486
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0487
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0endpoint2_dispdec
// base address: 0x30
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x048c
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x048d
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0endpoint3_dispdec
// base address: 0x48
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0492
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0493
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0endpoint4_dispdec
// base address: 0x60
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0498
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0499
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0endpoint5_dispdec
// base address: 0x78
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x049e
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x049f
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0endpoint6_dispdec
// base address: 0x90
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04a4
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04a5
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0endpoint7_dispdec
// base address: 0xa8
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04aa
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04ab
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream8_dispdec
// base address: 0x320
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0520
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0521
#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream9_dispdec
// base address: 0x328
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0522
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0523
#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream10_dispdec
// base address: 0x330
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x0524
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x0525
#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream11_dispdec
// base address: 0x338
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x0526
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x0527
#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream12_dispdec
// base address: 0x340
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x0528
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x0529
#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream13_dispdec
// base address: 0x348
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x052a
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x052b
#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream14_dispdec
// base address: 0x350
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x052c
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x052d
#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0stream15_dispdec
// base address: 0x358
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x052e
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x052f
#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0inputendpoint0_dispdec
// base address: 0x0
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0534
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0535
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0inputendpoint1_dispdec
// base address: 0x10
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0538
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0539
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0inputendpoint2_dispdec
// base address: 0x20
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x053c
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x053d
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0inputendpoint3_dispdec
// base address: 0x30
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0540
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0541
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0inputendpoint4_dispdec
// base address: 0x40
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0544
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0545
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0inputendpoint5_dispdec
// base address: 0x50
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0548
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0549
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0inputendpoint6_dispdec
// base address: 0x60
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x054c
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x054d
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_azf0inputendpoint7_dispdec
// base address: 0x70
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0550
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0551
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcp0_dispdec
// base address: 0x0
#define mmDCP0_GRPH_ENABLE 0x055a
#define mmDCP0_GRPH_ENABLE_BASE_IDX 2
#define mmDCP0_GRPH_CONTROL 0x055b
#define mmDCP0_GRPH_CONTROL_BASE_IDX 2
#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x055c
#define mmDCP0_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
#define mmDCP0_GRPH_SWAP_CNTL 0x055d
#define mmDCP0_GRPH_SWAP_CNTL_BASE_IDX 2
#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x055e
#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x055f
#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP0_GRPH_PITCH 0x0560
#define mmDCP0_GRPH_PITCH_BASE_IDX 2
#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0561
#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0562
#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x0563
#define mmDCP0_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x0564
#define mmDCP0_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
#define mmDCP0_GRPH_X_START 0x0565
#define mmDCP0_GRPH_X_START_BASE_IDX 2
#define mmDCP0_GRPH_Y_START 0x0566
#define mmDCP0_GRPH_Y_START_BASE_IDX 2
#define mmDCP0_GRPH_X_END 0x0567
#define mmDCP0_GRPH_X_END_BASE_IDX 2
#define mmDCP0_GRPH_Y_END 0x0568
#define mmDCP0_GRPH_Y_END_BASE_IDX 2
#define mmDCP0_INPUT_GAMMA_CONTROL 0x0569
#define mmDCP0_INPUT_GAMMA_CONTROL_BASE_IDX 2
#define mmDCP0_GRPH_UPDATE 0x056a
#define mmDCP0_GRPH_UPDATE_BASE_IDX 2
#define mmDCP0_GRPH_FLIP_CONTROL 0x056b
#define mmDCP0_GRPH_FLIP_CONTROL_BASE_IDX 2
#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x056c
#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
#define mmDCP0_GRPH_DFQ_CONTROL 0x056d
#define mmDCP0_GRPH_DFQ_CONTROL_BASE_IDX 2
#define mmDCP0_GRPH_DFQ_STATUS 0x056e
#define mmDCP0_GRPH_DFQ_STATUS_BASE_IDX 2
#define mmDCP0_GRPH_INTERRUPT_STATUS 0x056f
#define mmDCP0_GRPH_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x0570
#define mmDCP0_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0571
#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x0572
#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP0_GRPH_COMPRESS_PITCH 0x0573
#define mmDCP0_GRPH_COMPRESS_PITCH_BASE_IDX 2
#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0574
#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0575
#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
#define mmDCP0_PRESCALE_GRPH_CONTROL 0x0576
#define mmDCP0_PRESCALE_GRPH_CONTROL_BASE_IDX 2
#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x0577
#define mmDCP0_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x0578
#define mmDCP0_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x0579
#define mmDCP0_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
#define mmDCP0_INPUT_CSC_CONTROL 0x057a
#define mmDCP0_INPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP0_INPUT_CSC_C11_C12 0x057b
#define mmDCP0_INPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP0_INPUT_CSC_C13_C14 0x057c
#define mmDCP0_INPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP0_INPUT_CSC_C21_C22 0x057d
#define mmDCP0_INPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP0_INPUT_CSC_C23_C24 0x057e
#define mmDCP0_INPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP0_INPUT_CSC_C31_C32 0x057f
#define mmDCP0_INPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP0_INPUT_CSC_C33_C34 0x0580
#define mmDCP0_INPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP0_OUTPUT_CSC_CONTROL 0x0581
#define mmDCP0_OUTPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP0_OUTPUT_CSC_C11_C12 0x0582
#define mmDCP0_OUTPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP0_OUTPUT_CSC_C13_C14 0x0583
#define mmDCP0_OUTPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP0_OUTPUT_CSC_C21_C22 0x0584
#define mmDCP0_OUTPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP0_OUTPUT_CSC_C23_C24 0x0585
#define mmDCP0_OUTPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP0_OUTPUT_CSC_C31_C32 0x0586
#define mmDCP0_OUTPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP0_OUTPUT_CSC_C33_C34 0x0587
#define mmDCP0_OUTPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x0588
#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x0589
#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x058a
#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x058b
#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x058c
#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x058d
#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x058e
#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x058f
#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x0590
#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x0591
#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x0592
#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x0593
#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
#define mmDCP0_DENORM_CONTROL 0x0594
#define mmDCP0_DENORM_CONTROL_BASE_IDX 2
#define mmDCP0_OUT_ROUND_CONTROL 0x0595
#define mmDCP0_OUT_ROUND_CONTROL_BASE_IDX 2
#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x0596
#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x0597
#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x0598
#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
#define mmDCP0_KEY_CONTROL 0x0599
#define mmDCP0_KEY_CONTROL_BASE_IDX 2
#define mmDCP0_KEY_RANGE_ALPHA 0x059a
#define mmDCP0_KEY_RANGE_ALPHA_BASE_IDX 2
#define mmDCP0_KEY_RANGE_RED 0x059b
#define mmDCP0_KEY_RANGE_RED_BASE_IDX 2
#define mmDCP0_KEY_RANGE_GREEN 0x059c
#define mmDCP0_KEY_RANGE_GREEN_BASE_IDX 2
#define mmDCP0_KEY_RANGE_BLUE 0x059d
#define mmDCP0_KEY_RANGE_BLUE_BASE_IDX 2
#define mmDCP0_DEGAMMA_CONTROL 0x059e
#define mmDCP0_DEGAMMA_CONTROL_BASE_IDX 2
#define mmDCP0_GAMUT_REMAP_CONTROL 0x059f
#define mmDCP0_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmDCP0_GAMUT_REMAP_C11_C12 0x05a0
#define mmDCP0_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmDCP0_GAMUT_REMAP_C13_C14 0x05a1
#define mmDCP0_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmDCP0_GAMUT_REMAP_C21_C22 0x05a2
#define mmDCP0_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmDCP0_GAMUT_REMAP_C23_C24 0x05a3
#define mmDCP0_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmDCP0_GAMUT_REMAP_C31_C32 0x05a4
#define mmDCP0_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmDCP0_GAMUT_REMAP_C33_C34 0x05a5
#define mmDCP0_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x05a6
#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
#define mmDCP0_DCP_RANDOM_SEEDS 0x05a7
#define mmDCP0_DCP_RANDOM_SEEDS_BASE_IDX 2
#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x05a8
#define mmDCP0_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
#define mmDCP0_CUR_CONTROL 0x05a9
#define mmDCP0_CUR_CONTROL_BASE_IDX 2
#define mmDCP0_CUR_SURFACE_ADDRESS 0x05aa
#define mmDCP0_CUR_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP0_CUR_SIZE 0x05ab
#define mmDCP0_CUR_SIZE_BASE_IDX 2
#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x05ac
#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP0_CUR_POSITION 0x05ad
#define mmDCP0_CUR_POSITION_BASE_IDX 2
#define mmDCP0_CUR_HOT_SPOT 0x05ae
#define mmDCP0_CUR_HOT_SPOT_BASE_IDX 2
#define mmDCP0_CUR_COLOR1 0x05af
#define mmDCP0_CUR_COLOR1_BASE_IDX 2
#define mmDCP0_CUR_COLOR2 0x05b0
#define mmDCP0_CUR_COLOR2_BASE_IDX 2
#define mmDCP0_CUR_UPDATE 0x05b1
#define mmDCP0_CUR_UPDATE_BASE_IDX 2
#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x05bb
#define mmDCP0_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
#define mmDCP0_CUR_STEREO_CONTROL 0x05bc
#define mmDCP0_CUR_STEREO_CONTROL_BASE_IDX 2
#define mmDCP0_DC_LUT_RW_MODE 0x05be
#define mmDCP0_DC_LUT_RW_MODE_BASE_IDX 2
#define mmDCP0_DC_LUT_RW_INDEX 0x05bf
#define mmDCP0_DC_LUT_RW_INDEX_BASE_IDX 2
#define mmDCP0_DC_LUT_SEQ_COLOR 0x05c0
#define mmDCP0_DC_LUT_SEQ_COLOR_BASE_IDX 2
#define mmDCP0_DC_LUT_PWL_DATA 0x05c1
#define mmDCP0_DC_LUT_PWL_DATA_BASE_IDX 2
#define mmDCP0_DC_LUT_30_COLOR 0x05c2
#define mmDCP0_DC_LUT_30_COLOR_BASE_IDX 2
#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x05c3
#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x05c4
#define mmDCP0_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP0_DC_LUT_AUTOFILL 0x05c5
#define mmDCP0_DC_LUT_AUTOFILL_BASE_IDX 2
#define mmDCP0_DC_LUT_CONTROL 0x05c6
#define mmDCP0_DC_LUT_CONTROL_BASE_IDX 2
#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x05c7
#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x05c8
#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x05c9
#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x05ca
#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x05cb
#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x05cc
#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
#define mmDCP0_DCP_CRC_CONTROL 0x05cd
#define mmDCP0_DCP_CRC_CONTROL_BASE_IDX 2
#define mmDCP0_DCP_CRC_MASK 0x05ce
#define mmDCP0_DCP_CRC_MASK_BASE_IDX 2
#define mmDCP0_DCP_CRC_CURRENT 0x05cf
#define mmDCP0_DCP_CRC_CURRENT_BASE_IDX 2
#define mmDCP0_DVMM_PTE_CONTROL 0x05d0
#define mmDCP0_DVMM_PTE_CONTROL_BASE_IDX 2
#define mmDCP0_DCP_CRC_LAST 0x05d1
#define mmDCP0_DCP_CRC_LAST_BASE_IDX 2
#define mmDCP0_DVMM_PTE_ARB_CONTROL 0x05d2
#define mmDCP0_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x05d4
#define mmDCP0_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
#define mmDCP0_DCP_GSL_CONTROL 0x05d5
#define mmDCP0_DCP_GSL_CONTROL_BASE_IDX 2
#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x05d6
#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x05dc
#define mmDCP0_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
#define mmDCP0_HW_ROTATION 0x05de
#define mmDCP0_HW_ROTATION_BASE_IDX 2
#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x05df
#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
#define mmDCP0_REGAMMA_CONTROL 0x05e0
#define mmDCP0_REGAMMA_CONTROL_BASE_IDX 2
#define mmDCP0_REGAMMA_LUT_INDEX 0x05e1
#define mmDCP0_REGAMMA_LUT_INDEX_BASE_IDX 2
#define mmDCP0_REGAMMA_LUT_DATA 0x05e2
#define mmDCP0_REGAMMA_LUT_DATA_BASE_IDX 2
#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x05e3
#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x05e4
#define mmDCP0_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x05e5
#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x05e6
#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x05e7
#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x05e8
#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x05e9
#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x05ea
#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x05eb
#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x05ec
#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x05ed
#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x05ee
#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x05ef
#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x05f0
#define mmDCP0_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x05f1
#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x05f2
#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x05f3
#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x05f4
#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x05f5
#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x05f6
#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x05f7
#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x05f8
#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x05f9
#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x05fa
#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x05fb
#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
#define mmDCP0_ALPHA_CONTROL 0x05fc
#define mmDCP0_ALPHA_CONTROL_BASE_IDX 2
#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x05fd
#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x05fe
#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x05ff
#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT 0x0600
#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY 0x0601
#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x0602
#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x0603
#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
// addressBlock: dce_dc_lb0_dispdec
// base address: 0x0
#define mmLB0_LB_DATA_FORMAT 0x061a
#define mmLB0_LB_DATA_FORMAT_BASE_IDX 2
#define mmLB0_LB_MEMORY_CTRL 0x061b
#define mmLB0_LB_MEMORY_CTRL_BASE_IDX 2
#define mmLB0_LB_MEMORY_SIZE_STATUS 0x061c
#define mmLB0_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
#define mmLB0_LB_DESKTOP_HEIGHT 0x061d
#define mmLB0_LB_DESKTOP_HEIGHT_BASE_IDX 2
#define mmLB0_LB_VLINE_START_END 0x061e
#define mmLB0_LB_VLINE_START_END_BASE_IDX 2
#define mmLB0_LB_VLINE2_START_END 0x061f
#define mmLB0_LB_VLINE2_START_END_BASE_IDX 2
#define mmLB0_LB_V_COUNTER 0x0620
#define mmLB0_LB_V_COUNTER_BASE_IDX 2
#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x0621
#define mmLB0_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
#define mmLB0_LB_INTERRUPT_MASK 0x0622
#define mmLB0_LB_INTERRUPT_MASK_BASE_IDX 2
#define mmLB0_LB_VLINE_STATUS 0x0623
#define mmLB0_LB_VLINE_STATUS_BASE_IDX 2
#define mmLB0_LB_VLINE2_STATUS 0x0624
#define mmLB0_LB_VLINE2_STATUS_BASE_IDX 2
#define mmLB0_LB_VBLANK_STATUS 0x0625
#define mmLB0_LB_VBLANK_STATUS_BASE_IDX 2
#define mmLB0_LB_SYNC_RESET_SEL 0x0626
#define mmLB0_LB_SYNC_RESET_SEL_BASE_IDX 2
#define mmLB0_LB_BLACK_KEYER_R_CR 0x0627
#define mmLB0_LB_BLACK_KEYER_R_CR_BASE_IDX 2
#define mmLB0_LB_BLACK_KEYER_G_Y 0x0628
#define mmLB0_LB_BLACK_KEYER_G_Y_BASE_IDX 2
#define mmLB0_LB_BLACK_KEYER_B_CB 0x0629
#define mmLB0_LB_BLACK_KEYER_B_CB_BASE_IDX 2
#define mmLB0_LB_KEYER_COLOR_CTRL 0x062a
#define mmLB0_LB_KEYER_COLOR_CTRL_BASE_IDX 2
#define mmLB0_LB_KEYER_COLOR_R_CR 0x062b
#define mmLB0_LB_KEYER_COLOR_R_CR_BASE_IDX 2
#define mmLB0_LB_KEYER_COLOR_G_Y 0x062c
#define mmLB0_LB_KEYER_COLOR_G_Y_BASE_IDX 2
#define mmLB0_LB_KEYER_COLOR_B_CB 0x062d
#define mmLB0_LB_KEYER_COLOR_B_CB_BASE_IDX 2
#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x062e
#define mmLB0_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x062f
#define mmLB0_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x0630
#define mmLB0_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x0631
#define mmLB0_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x0632
#define mmLB0_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x0633
#define mmLB0_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
#define mmLB0_LB_BUFFER_STATUS 0x0634
#define mmLB0_LB_BUFFER_STATUS_BASE_IDX 2
#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x0635
#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
#define mmLB0_MVP_AFR_FLIP_MODE 0x0636
#define mmLB0_MVP_AFR_FLIP_MODE_BASE_IDX 2
#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x0637
#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x0638
#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
#define mmLB0_DC_MVP_LB_CONTROL 0x0639
#define mmLB0_DC_MVP_LB_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dcfe0_dispdec
// base address: 0x0
#define mmDCFE0_DCFE_CLOCK_CONTROL 0x065a
#define mmDCFE0_DCFE_CLOCK_CONTROL_BASE_IDX 2
#define mmDCFE0_DCFE_SOFT_RESET 0x065b
#define mmDCFE0_DCFE_SOFT_RESET_BASE_IDX 2
#define mmDCFE0_DCFE_MEM_PWR_CTRL 0x065d
#define mmDCFE0_DCFE_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x065e
#define mmDCFE0_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDCFE0_DCFE_MEM_PWR_STATUS 0x065f
#define mmDCFE0_DCFE_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCFE0_DCFE_MISC 0x0660
#define mmDCFE0_DCFE_MISC_BASE_IDX 2
#define mmDCFE0_DCFE_FLUSH 0x0661
#define mmDCFE0_DCFE_FLUSH_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon3_dispdec
// base address: 0x1938
#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x066e
#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x066f
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0670
#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CNTL 0x0671
#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CNTL2 0x0672
#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0673
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0674
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_HI 0x0675
#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_LOW 0x0676
#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmif_pg0_dispdec
// base address: 0x0
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x067a
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x067b
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x067c
#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x067d
#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL 0x067e
#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x067f
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2 0x0680
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL 0x0681
#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x0682
#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_BASE_IDX 2
#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x0686
#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
#define mmDMIF_PG0_DPG_DVMM_STATUS 0x0687
#define mmDMIF_PG0_DPG_DVMM_STATUS_BASE_IDX 2
// addressBlock: dce_dc_scl0_dispdec
// base address: 0x0
#define mmSCL0_SCL_COEF_RAM_SELECT 0x069a
#define mmSCL0_SCL_COEF_RAM_SELECT_BASE_IDX 2
#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x069b
#define mmSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmSCL0_SCL_MODE 0x069c
#define mmSCL0_SCL_MODE_BASE_IDX 2
#define mmSCL0_SCL_TAP_CONTROL 0x069d
#define mmSCL0_SCL_TAP_CONTROL_BASE_IDX 2
#define mmSCL0_SCL_CONTROL 0x069e
#define mmSCL0_SCL_CONTROL_BASE_IDX 2
#define mmSCL0_SCL_BYPASS_CONTROL 0x069f
#define mmSCL0_SCL_BYPASS_CONTROL_BASE_IDX 2
#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x06a0
#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x06a1
#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x06a2
#define mmSCL0_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x06a3
#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL0_SCL_HORZ_FILTER_INIT 0x06a4
#define mmSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x06a5
#define mmSCL0_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x06a6
#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL0_SCL_VERT_FILTER_INIT 0x06a7
#define mmSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x06a8
#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmSCL0_SCL_ROUND_OFFSET 0x06a9
#define mmSCL0_SCL_ROUND_OFFSET_BASE_IDX 2
#define mmSCL0_SCL_UPDATE 0x06aa
#define mmSCL0_SCL_UPDATE_BASE_IDX 2
#define mmSCL0_SCL_F_SHARP_CONTROL 0x06ab
#define mmSCL0_SCL_F_SHARP_CONTROL_BASE_IDX 2
#define mmSCL0_SCL_ALU_CONTROL 0x06ac
#define mmSCL0_SCL_ALU_CONTROL_BASE_IDX 2
#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x06ad
#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
#define mmSCL0_VIEWPORT_START_SECONDARY 0x06ae
#define mmSCL0_VIEWPORT_START_SECONDARY_BASE_IDX 2
#define mmSCL0_VIEWPORT_START 0x06af
#define mmSCL0_VIEWPORT_START_BASE_IDX 2
#define mmSCL0_VIEWPORT_SIZE 0x06b0
#define mmSCL0_VIEWPORT_SIZE_BASE_IDX 2
#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x06b1
#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x06b2
#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmSCL0_SCL_MODE_CHANGE_DET1 0x06b3
#define mmSCL0_SCL_MODE_CHANGE_DET1_BASE_IDX 2
#define mmSCL0_SCL_MODE_CHANGE_DET2 0x06b4
#define mmSCL0_SCL_MODE_CHANGE_DET2_BASE_IDX 2
#define mmSCL0_SCL_MODE_CHANGE_DET3 0x06b5
#define mmSCL0_SCL_MODE_CHANGE_DET3_BASE_IDX 2
#define mmSCL0_SCL_MODE_CHANGE_MASK 0x06b6
#define mmSCL0_SCL_MODE_CHANGE_MASK_BASE_IDX 2
// addressBlock: dce_dc_blnd0_dispdec
// base address: 0x0
#define mmBLND0_BLND_CONTROL 0x06c7
#define mmBLND0_BLND_CONTROL_BASE_IDX 2
#define mmBLND0_BLND_SM_CONTROL2 0x06c8
#define mmBLND0_BLND_SM_CONTROL2_BASE_IDX 2
#define mmBLND0_BLND_CONTROL2 0x06c9
#define mmBLND0_BLND_CONTROL2_BASE_IDX 2
#define mmBLND0_BLND_UPDATE 0x06ca
#define mmBLND0_BLND_UPDATE_BASE_IDX 2
#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x06cb
#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
#define mmBLND0_BLND_V_UPDATE_LOCK 0x06cc
#define mmBLND0_BLND_V_UPDATE_LOCK_BASE_IDX 2
#define mmBLND0_BLND_REG_UPDATE_STATUS 0x06cd
#define mmBLND0_BLND_REG_UPDATE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_crtc0_dispdec
// base address: 0x0
#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x06d2
#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
#define mmCRTC0_CRTC_H_TOTAL 0x06d3
#define mmCRTC0_CRTC_H_TOTAL_BASE_IDX 2
#define mmCRTC0_CRTC_H_BLANK_START_END 0x06d4
#define mmCRTC0_CRTC_H_BLANK_START_END_BASE_IDX 2
#define mmCRTC0_CRTC_H_SYNC_A 0x06d5
#define mmCRTC0_CRTC_H_SYNC_A_BASE_IDX 2
#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x06d6
#define mmCRTC0_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC0_CRTC_H_SYNC_B 0x06d7
#define mmCRTC0_CRTC_H_SYNC_B_BASE_IDX 2
#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x06d8
#define mmCRTC0_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC0_CRTC_VBI_END 0x06d9
#define mmCRTC0_CRTC_VBI_END_BASE_IDX 2
#define mmCRTC0_CRTC_V_TOTAL 0x06da
#define mmCRTC0_CRTC_V_TOTAL_BASE_IDX 2
#define mmCRTC0_CRTC_V_TOTAL_MIN 0x06db
#define mmCRTC0_CRTC_V_TOTAL_MIN_BASE_IDX 2
#define mmCRTC0_CRTC_V_TOTAL_MAX 0x06dc
#define mmCRTC0_CRTC_V_TOTAL_MAX_BASE_IDX 2
#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x06dd
#define mmCRTC0_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x06de
#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x06df
#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmCRTC0_CRTC_V_BLANK_START_END 0x06e0
#define mmCRTC0_CRTC_V_BLANK_START_END_BASE_IDX 2
#define mmCRTC0_CRTC_V_SYNC_A 0x06e1
#define mmCRTC0_CRTC_V_SYNC_A_BASE_IDX 2
#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x06e2
#define mmCRTC0_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC0_CRTC_V_SYNC_B 0x06e3
#define mmCRTC0_CRTC_V_SYNC_B_BASE_IDX 2
#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x06e4
#define mmCRTC0_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC0_CRTC_DTMTEST_CNTL 0x06e5
#define mmCRTC0_CRTC_DTMTEST_CNTL_BASE_IDX 2
#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x06e6
#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
#define mmCRTC0_CRTC_TRIGA_CNTL 0x06e7
#define mmCRTC0_CRTC_TRIGA_CNTL_BASE_IDX 2
#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x06e8
#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC0_CRTC_TRIGB_CNTL 0x06e9
#define mmCRTC0_CRTC_TRIGB_CNTL_BASE_IDX 2
#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x06ea
#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x06eb
#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmCRTC0_CRTC_FLOW_CONTROL 0x06ec
#define mmCRTC0_CRTC_FLOW_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x06ed
#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x06ee
#define mmCRTC0_CRTC_AVSYNC_COUNTER_BASE_IDX 2
#define mmCRTC0_CRTC_CONTROL 0x06ef
#define mmCRTC0_CRTC_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_BLANK_CONTROL 0x06f0
#define mmCRTC0_CRTC_BLANK_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x06f1
#define mmCRTC0_CRTC_INTERLACE_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_INTERLACE_STATUS 0x06f2
#define mmCRTC0_CRTC_INTERLACE_STATUS_BASE_IDX 2
#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x06f3
#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x06f4
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x06f5
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmCRTC0_CRTC_STATUS 0x06f6
#define mmCRTC0_CRTC_STATUS_BASE_IDX 2
#define mmCRTC0_CRTC_STATUS_POSITION 0x06f7
#define mmCRTC0_CRTC_STATUS_POSITION_BASE_IDX 2
#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x06f8
#define mmCRTC0_CRTC_NOM_VERT_POSITION_BASE_IDX 2
#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x06f9
#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x06fa
#define mmCRTC0_CRTC_STATUS_VF_COUNT_BASE_IDX 2
#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x06fb
#define mmCRTC0_CRTC_STATUS_HV_COUNT_BASE_IDX 2
#define mmCRTC0_CRTC_COUNT_CONTROL 0x06fc
#define mmCRTC0_CRTC_COUNT_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_COUNT_RESET 0x06fd
#define mmCRTC0_CRTC_COUNT_RESET_BASE_IDX 2
#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x06fe
#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x06ff
#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_STEREO_STATUS 0x0700
#define mmCRTC0_CRTC_STEREO_STATUS_BASE_IDX 2
#define mmCRTC0_CRTC_STEREO_CONTROL 0x0701
#define mmCRTC0_CRTC_STEREO_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x0702
#define mmCRTC0_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x0703
#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x0704
#define mmCRTC0_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x0705
#define mmCRTC0_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
#define mmCRTC0_CRTC_START_LINE_CONTROL 0x0706
#define mmCRTC0_CRTC_START_LINE_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x0707
#define mmCRTC0_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_UPDATE_LOCK 0x0708
#define mmCRTC0_CRTC_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x0709
#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x070a
#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x070b
#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x070c
#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x070d
#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x070e
#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x070f
#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x0710
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0711
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
#define mmCRTC0_CRTC_MVP_STATUS 0x0712
#define mmCRTC0_CRTC_MVP_STATUS_BASE_IDX 2
#define mmCRTC0_CRTC_MASTER_EN 0x0713
#define mmCRTC0_CRTC_MASTER_EN_BASE_IDX 2
#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x0714
#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x0715
#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x0717
#define mmCRTC0_CRTC_OVERSCAN_COLOR_BASE_IDX 2
#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x0718
#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x0719
#define mmCRTC0_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x071a
#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmCRTC0_CRTC_BLACK_COLOR 0x071b
#define mmCRTC0_CRTC_BLACK_COLOR_BASE_IDX 2
#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x071c
#define mmCRTC0_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x071d
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x071e
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x071f
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0720
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0721
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0722
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_CRC_CNTL 0x0723
#define mmCRTC0_CRTC_CRC_CNTL_BASE_IDX 2
#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x0724
#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0725
#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x0726
#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0727
#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_CRC0_DATA_RG 0x0728
#define mmCRTC0_CRTC_CRC0_DATA_RG_BASE_IDX 2
#define mmCRTC0_CRTC_CRC0_DATA_B 0x0729
#define mmCRTC0_CRTC_CRC0_DATA_B_BASE_IDX 2
#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x072a
#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x072b
#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x072c
#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x072d
#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_CRC1_DATA_RG 0x072e
#define mmCRTC0_CRTC_CRC1_DATA_RG_BASE_IDX 2
#define mmCRTC0_CRTC_CRC1_DATA_B 0x072f
#define mmCRTC0_CRTC_CRC1_DATA_B_BASE_IDX 2
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x0730
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0731
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0732
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0733
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0734
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0735
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x0736
#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x0737
#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x0738
#define mmCRTC0_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
#define mmCRTC0_CRTC_GSL_WINDOW 0x0739
#define mmCRTC0_CRTC_GSL_WINDOW_BASE_IDX 2
#define mmCRTC0_CRTC_GSL_CONTROL 0x073a
#define mmCRTC0_CRTC_GSL_CONTROL_BASE_IDX 2
#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS 0x073d
#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmCRTC0_CRTC_DRR_CONTROL 0x073e
#define mmCRTC0_CRTC_DRR_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_fmt0_dispdec
// base address: 0x0
#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x0742
#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x0743
#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x0744
#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x0745
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT0_FMT_CONTROL 0x0746
#define mmFMT0_FMT_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x0747
#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x0748
#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x0749
#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x074a
#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_CNTL 0x074e
#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT0_FMT_CRC_CNTL 0x074f
#define mmFMT0_FMT_CRC_CNTL_BASE_IDX 2
#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x0750
#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0751
#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x0752
#define mmFMT0_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x0753
#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0754
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_420_HBLANK_EARLY_START 0x0755
#define mmFMT0_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
// addressBlock: dce_dc_dcp1_dispdec
// base address: 0x800
#define mmDCP1_GRPH_ENABLE 0x075a
#define mmDCP1_GRPH_ENABLE_BASE_IDX 2
#define mmDCP1_GRPH_CONTROL 0x075b
#define mmDCP1_GRPH_CONTROL_BASE_IDX 2
#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x075c
#define mmDCP1_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
#define mmDCP1_GRPH_SWAP_CNTL 0x075d
#define mmDCP1_GRPH_SWAP_CNTL_BASE_IDX 2
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x075e
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x075f
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP1_GRPH_PITCH 0x0760
#define mmDCP1_GRPH_PITCH_BASE_IDX 2
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0761
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0762
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x0763
#define mmDCP1_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x0764
#define mmDCP1_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
#define mmDCP1_GRPH_X_START 0x0765
#define mmDCP1_GRPH_X_START_BASE_IDX 2
#define mmDCP1_GRPH_Y_START 0x0766
#define mmDCP1_GRPH_Y_START_BASE_IDX 2
#define mmDCP1_GRPH_X_END 0x0767
#define mmDCP1_GRPH_X_END_BASE_IDX 2
#define mmDCP1_GRPH_Y_END 0x0768
#define mmDCP1_GRPH_Y_END_BASE_IDX 2
#define mmDCP1_INPUT_GAMMA_CONTROL 0x0769
#define mmDCP1_INPUT_GAMMA_CONTROL_BASE_IDX 2
#define mmDCP1_GRPH_UPDATE 0x076a
#define mmDCP1_GRPH_UPDATE_BASE_IDX 2
#define mmDCP1_GRPH_FLIP_CONTROL 0x076b
#define mmDCP1_GRPH_FLIP_CONTROL_BASE_IDX 2
#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x076c
#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
#define mmDCP1_GRPH_DFQ_CONTROL 0x076d
#define mmDCP1_GRPH_DFQ_CONTROL_BASE_IDX 2
#define mmDCP1_GRPH_DFQ_STATUS 0x076e
#define mmDCP1_GRPH_DFQ_STATUS_BASE_IDX 2
#define mmDCP1_GRPH_INTERRUPT_STATUS 0x076f
#define mmDCP1_GRPH_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x0770
#define mmDCP1_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0771
#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x0772
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP1_GRPH_COMPRESS_PITCH 0x0773
#define mmDCP1_GRPH_COMPRESS_PITCH_BASE_IDX 2
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0774
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0775
#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
#define mmDCP1_PRESCALE_GRPH_CONTROL 0x0776
#define mmDCP1_PRESCALE_GRPH_CONTROL_BASE_IDX 2
#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x0777
#define mmDCP1_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x0778
#define mmDCP1_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x0779
#define mmDCP1_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
#define mmDCP1_INPUT_CSC_CONTROL 0x077a
#define mmDCP1_INPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP1_INPUT_CSC_C11_C12 0x077b
#define mmDCP1_INPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP1_INPUT_CSC_C13_C14 0x077c
#define mmDCP1_INPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP1_INPUT_CSC_C21_C22 0x077d
#define mmDCP1_INPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP1_INPUT_CSC_C23_C24 0x077e
#define mmDCP1_INPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP1_INPUT_CSC_C31_C32 0x077f
#define mmDCP1_INPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP1_INPUT_CSC_C33_C34 0x0780
#define mmDCP1_INPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP1_OUTPUT_CSC_CONTROL 0x0781
#define mmDCP1_OUTPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP1_OUTPUT_CSC_C11_C12 0x0782
#define mmDCP1_OUTPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP1_OUTPUT_CSC_C13_C14 0x0783
#define mmDCP1_OUTPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP1_OUTPUT_CSC_C21_C22 0x0784
#define mmDCP1_OUTPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP1_OUTPUT_CSC_C23_C24 0x0785
#define mmDCP1_OUTPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP1_OUTPUT_CSC_C31_C32 0x0786
#define mmDCP1_OUTPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP1_OUTPUT_CSC_C33_C34 0x0787
#define mmDCP1_OUTPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x0788
#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x0789
#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x078a
#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x078b
#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x078c
#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x078d
#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x078e
#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x078f
#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x0790
#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x0791
#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x0792
#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x0793
#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
#define mmDCP1_DENORM_CONTROL 0x0794
#define mmDCP1_DENORM_CONTROL_BASE_IDX 2
#define mmDCP1_OUT_ROUND_CONTROL 0x0795
#define mmDCP1_OUT_ROUND_CONTROL_BASE_IDX 2
#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x0796
#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x0797
#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x0798
#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
#define mmDCP1_KEY_CONTROL 0x0799
#define mmDCP1_KEY_CONTROL_BASE_IDX 2
#define mmDCP1_KEY_RANGE_ALPHA 0x079a
#define mmDCP1_KEY_RANGE_ALPHA_BASE_IDX 2
#define mmDCP1_KEY_RANGE_RED 0x079b
#define mmDCP1_KEY_RANGE_RED_BASE_IDX 2
#define mmDCP1_KEY_RANGE_GREEN 0x079c
#define mmDCP1_KEY_RANGE_GREEN_BASE_IDX 2
#define mmDCP1_KEY_RANGE_BLUE 0x079d
#define mmDCP1_KEY_RANGE_BLUE_BASE_IDX 2
#define mmDCP1_DEGAMMA_CONTROL 0x079e
#define mmDCP1_DEGAMMA_CONTROL_BASE_IDX 2
#define mmDCP1_GAMUT_REMAP_CONTROL 0x079f
#define mmDCP1_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmDCP1_GAMUT_REMAP_C11_C12 0x07a0
#define mmDCP1_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmDCP1_GAMUT_REMAP_C13_C14 0x07a1
#define mmDCP1_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmDCP1_GAMUT_REMAP_C21_C22 0x07a2
#define mmDCP1_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmDCP1_GAMUT_REMAP_C23_C24 0x07a3
#define mmDCP1_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmDCP1_GAMUT_REMAP_C31_C32 0x07a4
#define mmDCP1_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmDCP1_GAMUT_REMAP_C33_C34 0x07a5
#define mmDCP1_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x07a6
#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
#define mmDCP1_DCP_RANDOM_SEEDS 0x07a7
#define mmDCP1_DCP_RANDOM_SEEDS_BASE_IDX 2
#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x07a8
#define mmDCP1_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
#define mmDCP1_CUR_CONTROL 0x07a9
#define mmDCP1_CUR_CONTROL_BASE_IDX 2
#define mmDCP1_CUR_SURFACE_ADDRESS 0x07aa
#define mmDCP1_CUR_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP1_CUR_SIZE 0x07ab
#define mmDCP1_CUR_SIZE_BASE_IDX 2
#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x07ac
#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP1_CUR_POSITION 0x07ad
#define mmDCP1_CUR_POSITION_BASE_IDX 2
#define mmDCP1_CUR_HOT_SPOT 0x07ae
#define mmDCP1_CUR_HOT_SPOT_BASE_IDX 2
#define mmDCP1_CUR_COLOR1 0x07af
#define mmDCP1_CUR_COLOR1_BASE_IDX 2
#define mmDCP1_CUR_COLOR2 0x07b0
#define mmDCP1_CUR_COLOR2_BASE_IDX 2
#define mmDCP1_CUR_UPDATE 0x07b1
#define mmDCP1_CUR_UPDATE_BASE_IDX 2
#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x07bb
#define mmDCP1_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
#define mmDCP1_CUR_STEREO_CONTROL 0x07bc
#define mmDCP1_CUR_STEREO_CONTROL_BASE_IDX 2
#define mmDCP1_DC_LUT_RW_MODE 0x07be
#define mmDCP1_DC_LUT_RW_MODE_BASE_IDX 2
#define mmDCP1_DC_LUT_RW_INDEX 0x07bf
#define mmDCP1_DC_LUT_RW_INDEX_BASE_IDX 2
#define mmDCP1_DC_LUT_SEQ_COLOR 0x07c0
#define mmDCP1_DC_LUT_SEQ_COLOR_BASE_IDX 2
#define mmDCP1_DC_LUT_PWL_DATA 0x07c1
#define mmDCP1_DC_LUT_PWL_DATA_BASE_IDX 2
#define mmDCP1_DC_LUT_30_COLOR 0x07c2
#define mmDCP1_DC_LUT_30_COLOR_BASE_IDX 2
#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x07c3
#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x07c4
#define mmDCP1_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP1_DC_LUT_AUTOFILL 0x07c5
#define mmDCP1_DC_LUT_AUTOFILL_BASE_IDX 2
#define mmDCP1_DC_LUT_CONTROL 0x07c6
#define mmDCP1_DC_LUT_CONTROL_BASE_IDX 2
#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x07c7
#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x07c8
#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x07c9
#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x07ca
#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x07cb
#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x07cc
#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
#define mmDCP1_DCP_CRC_CONTROL 0x07cd
#define mmDCP1_DCP_CRC_CONTROL_BASE_IDX 2
#define mmDCP1_DCP_CRC_MASK 0x07ce
#define mmDCP1_DCP_CRC_MASK_BASE_IDX 2
#define mmDCP1_DCP_CRC_CURRENT 0x07cf
#define mmDCP1_DCP_CRC_CURRENT_BASE_IDX 2
#define mmDCP1_DVMM_PTE_CONTROL 0x07d0
#define mmDCP1_DVMM_PTE_CONTROL_BASE_IDX 2
#define mmDCP1_DCP_CRC_LAST 0x07d1
#define mmDCP1_DCP_CRC_LAST_BASE_IDX 2
#define mmDCP1_DVMM_PTE_ARB_CONTROL 0x07d2
#define mmDCP1_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x07d4
#define mmDCP1_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
#define mmDCP1_DCP_GSL_CONTROL 0x07d5
#define mmDCP1_DCP_GSL_CONTROL_BASE_IDX 2
#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x07d6
#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x07dc
#define mmDCP1_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
#define mmDCP1_HW_ROTATION 0x07de
#define mmDCP1_HW_ROTATION_BASE_IDX 2
#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x07df
#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
#define mmDCP1_REGAMMA_CONTROL 0x07e0
#define mmDCP1_REGAMMA_CONTROL_BASE_IDX 2
#define mmDCP1_REGAMMA_LUT_INDEX 0x07e1
#define mmDCP1_REGAMMA_LUT_INDEX_BASE_IDX 2
#define mmDCP1_REGAMMA_LUT_DATA 0x07e2
#define mmDCP1_REGAMMA_LUT_DATA_BASE_IDX 2
#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x07e3
#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x07e4
#define mmDCP1_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x07e5
#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x07e6
#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x07e7
#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x07e8
#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x07e9
#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x07ea
#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x07eb
#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x07ec
#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x07ed
#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x07ee
#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x07ef
#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x07f0
#define mmDCP1_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x07f1
#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x07f2
#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x07f3
#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x07f4
#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x07f5
#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x07f6
#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x07f7
#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x07f8
#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x07f9
#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x07fa
#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x07fb
#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
#define mmDCP1_ALPHA_CONTROL 0x07fc
#define mmDCP1_ALPHA_CONTROL_BASE_IDX 2
#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x07fd
#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x07fe
#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x07ff
#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT 0x0800
#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY 0x0801
#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x0802
#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x0803
#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
// addressBlock: dce_dc_lb1_dispdec
// base address: 0x800
#define mmLB1_LB_DATA_FORMAT 0x081a
#define mmLB1_LB_DATA_FORMAT_BASE_IDX 2
#define mmLB1_LB_MEMORY_CTRL 0x081b
#define mmLB1_LB_MEMORY_CTRL_BASE_IDX 2
#define mmLB1_LB_MEMORY_SIZE_STATUS 0x081c
#define mmLB1_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
#define mmLB1_LB_DESKTOP_HEIGHT 0x081d
#define mmLB1_LB_DESKTOP_HEIGHT_BASE_IDX 2
#define mmLB1_LB_VLINE_START_END 0x081e
#define mmLB1_LB_VLINE_START_END_BASE_IDX 2
#define mmLB1_LB_VLINE2_START_END 0x081f
#define mmLB1_LB_VLINE2_START_END_BASE_IDX 2
#define mmLB1_LB_V_COUNTER 0x0820
#define mmLB1_LB_V_COUNTER_BASE_IDX 2
#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x0821
#define mmLB1_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
#define mmLB1_LB_INTERRUPT_MASK 0x0822
#define mmLB1_LB_INTERRUPT_MASK_BASE_IDX 2
#define mmLB1_LB_VLINE_STATUS 0x0823
#define mmLB1_LB_VLINE_STATUS_BASE_IDX 2
#define mmLB1_LB_VLINE2_STATUS 0x0824
#define mmLB1_LB_VLINE2_STATUS_BASE_IDX 2
#define mmLB1_LB_VBLANK_STATUS 0x0825
#define mmLB1_LB_VBLANK_STATUS_BASE_IDX 2
#define mmLB1_LB_SYNC_RESET_SEL 0x0826
#define mmLB1_LB_SYNC_RESET_SEL_BASE_IDX 2
#define mmLB1_LB_BLACK_KEYER_R_CR 0x0827
#define mmLB1_LB_BLACK_KEYER_R_CR_BASE_IDX 2
#define mmLB1_LB_BLACK_KEYER_G_Y 0x0828
#define mmLB1_LB_BLACK_KEYER_G_Y_BASE_IDX 2
#define mmLB1_LB_BLACK_KEYER_B_CB 0x0829
#define mmLB1_LB_BLACK_KEYER_B_CB_BASE_IDX 2
#define mmLB1_LB_KEYER_COLOR_CTRL 0x082a
#define mmLB1_LB_KEYER_COLOR_CTRL_BASE_IDX 2
#define mmLB1_LB_KEYER_COLOR_R_CR 0x082b
#define mmLB1_LB_KEYER_COLOR_R_CR_BASE_IDX 2
#define mmLB1_LB_KEYER_COLOR_G_Y 0x082c
#define mmLB1_LB_KEYER_COLOR_G_Y_BASE_IDX 2
#define mmLB1_LB_KEYER_COLOR_B_CB 0x082d
#define mmLB1_LB_KEYER_COLOR_B_CB_BASE_IDX 2
#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x082e
#define mmLB1_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x082f
#define mmLB1_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x0830
#define mmLB1_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x0831
#define mmLB1_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x0832
#define mmLB1_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x0833
#define mmLB1_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
#define mmLB1_LB_BUFFER_STATUS 0x0834
#define mmLB1_LB_BUFFER_STATUS_BASE_IDX 2
#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x0835
#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
#define mmLB1_MVP_AFR_FLIP_MODE 0x0836
#define mmLB1_MVP_AFR_FLIP_MODE_BASE_IDX 2
#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x0837
#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x0838
#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
#define mmLB1_DC_MVP_LB_CONTROL 0x0839
#define mmLB1_DC_MVP_LB_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dcfe1_dispdec
// base address: 0x800
#define mmDCFE1_DCFE_CLOCK_CONTROL 0x085a
#define mmDCFE1_DCFE_CLOCK_CONTROL_BASE_IDX 2
#define mmDCFE1_DCFE_SOFT_RESET 0x085b
#define mmDCFE1_DCFE_SOFT_RESET_BASE_IDX 2
#define mmDCFE1_DCFE_MEM_PWR_CTRL 0x085d
#define mmDCFE1_DCFE_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x085e
#define mmDCFE1_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDCFE1_DCFE_MEM_PWR_STATUS 0x085f
#define mmDCFE1_DCFE_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCFE1_DCFE_MISC 0x0860
#define mmDCFE1_DCFE_MISC_BASE_IDX 2
#define mmDCFE1_DCFE_FLUSH 0x0861
#define mmDCFE1_DCFE_FLUSH_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon4_dispdec
// base address: 0x2138
#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x086e
#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x086f
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0870
#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CNTL 0x0871
#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CNTL2 0x0872
#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0873
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0874
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_HI 0x0875
#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_LOW 0x0876
#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmif_pg1_dispdec
// base address: 0x800
#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x087a
#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x087b
#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x087c
#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x087d
#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL 0x087e
#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x087f
#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2 0x0880
#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL 0x0881
#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x0882
#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_BASE_IDX 2
#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x0886
#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
#define mmDMIF_PG1_DPG_DVMM_STATUS 0x0887
#define mmDMIF_PG1_DPG_DVMM_STATUS_BASE_IDX 2
// addressBlock: dce_dc_scl1_dispdec
// base address: 0x800
#define mmSCL1_SCL_COEF_RAM_SELECT 0x089a
#define mmSCL1_SCL_COEF_RAM_SELECT_BASE_IDX 2
#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x089b
#define mmSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmSCL1_SCL_MODE 0x089c
#define mmSCL1_SCL_MODE_BASE_IDX 2
#define mmSCL1_SCL_TAP_CONTROL 0x089d
#define mmSCL1_SCL_TAP_CONTROL_BASE_IDX 2
#define mmSCL1_SCL_CONTROL 0x089e
#define mmSCL1_SCL_CONTROL_BASE_IDX 2
#define mmSCL1_SCL_BYPASS_CONTROL 0x089f
#define mmSCL1_SCL_BYPASS_CONTROL_BASE_IDX 2
#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x08a0
#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x08a1
#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x08a2
#define mmSCL1_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x08a3
#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL1_SCL_HORZ_FILTER_INIT 0x08a4
#define mmSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x08a5
#define mmSCL1_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x08a6
#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL1_SCL_VERT_FILTER_INIT 0x08a7
#define mmSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x08a8
#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmSCL1_SCL_ROUND_OFFSET 0x08a9
#define mmSCL1_SCL_ROUND_OFFSET_BASE_IDX 2
#define mmSCL1_SCL_UPDATE 0x08aa
#define mmSCL1_SCL_UPDATE_BASE_IDX 2
#define mmSCL1_SCL_F_SHARP_CONTROL 0x08ab
#define mmSCL1_SCL_F_SHARP_CONTROL_BASE_IDX 2
#define mmSCL1_SCL_ALU_CONTROL 0x08ac
#define mmSCL1_SCL_ALU_CONTROL_BASE_IDX 2
#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x08ad
#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
#define mmSCL1_VIEWPORT_START_SECONDARY 0x08ae
#define mmSCL1_VIEWPORT_START_SECONDARY_BASE_IDX 2
#define mmSCL1_VIEWPORT_START 0x08af
#define mmSCL1_VIEWPORT_START_BASE_IDX 2
#define mmSCL1_VIEWPORT_SIZE 0x08b0
#define mmSCL1_VIEWPORT_SIZE_BASE_IDX 2
#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x08b1
#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x08b2
#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmSCL1_SCL_MODE_CHANGE_DET1 0x08b3
#define mmSCL1_SCL_MODE_CHANGE_DET1_BASE_IDX 2
#define mmSCL1_SCL_MODE_CHANGE_DET2 0x08b4
#define mmSCL1_SCL_MODE_CHANGE_DET2_BASE_IDX 2
#define mmSCL1_SCL_MODE_CHANGE_DET3 0x08b5
#define mmSCL1_SCL_MODE_CHANGE_DET3_BASE_IDX 2
#define mmSCL1_SCL_MODE_CHANGE_MASK 0x08b6
#define mmSCL1_SCL_MODE_CHANGE_MASK_BASE_IDX 2
// addressBlock: dce_dc_blnd1_dispdec
// base address: 0x800
#define mmBLND1_BLND_CONTROL 0x08c7
#define mmBLND1_BLND_CONTROL_BASE_IDX 2
#define mmBLND1_BLND_SM_CONTROL2 0x08c8
#define mmBLND1_BLND_SM_CONTROL2_BASE_IDX 2
#define mmBLND1_BLND_CONTROL2 0x08c9
#define mmBLND1_BLND_CONTROL2_BASE_IDX 2
#define mmBLND1_BLND_UPDATE 0x08ca
#define mmBLND1_BLND_UPDATE_BASE_IDX 2
#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x08cb
#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
#define mmBLND1_BLND_V_UPDATE_LOCK 0x08cc
#define mmBLND1_BLND_V_UPDATE_LOCK_BASE_IDX 2
#define mmBLND1_BLND_REG_UPDATE_STATUS 0x08cd
#define mmBLND1_BLND_REG_UPDATE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_crtc1_dispdec
// base address: 0x800
#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x08d2
#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
#define mmCRTC1_CRTC_H_TOTAL 0x08d3
#define mmCRTC1_CRTC_H_TOTAL_BASE_IDX 2
#define mmCRTC1_CRTC_H_BLANK_START_END 0x08d4
#define mmCRTC1_CRTC_H_BLANK_START_END_BASE_IDX 2
#define mmCRTC1_CRTC_H_SYNC_A 0x08d5
#define mmCRTC1_CRTC_H_SYNC_A_BASE_IDX 2
#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x08d6
#define mmCRTC1_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC1_CRTC_H_SYNC_B 0x08d7
#define mmCRTC1_CRTC_H_SYNC_B_BASE_IDX 2
#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x08d8
#define mmCRTC1_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC1_CRTC_VBI_END 0x08d9
#define mmCRTC1_CRTC_VBI_END_BASE_IDX 2
#define mmCRTC1_CRTC_V_TOTAL 0x08da
#define mmCRTC1_CRTC_V_TOTAL_BASE_IDX 2
#define mmCRTC1_CRTC_V_TOTAL_MIN 0x08db
#define mmCRTC1_CRTC_V_TOTAL_MIN_BASE_IDX 2
#define mmCRTC1_CRTC_V_TOTAL_MAX 0x08dc
#define mmCRTC1_CRTC_V_TOTAL_MAX_BASE_IDX 2
#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x08dd
#define mmCRTC1_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x08de
#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x08df
#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmCRTC1_CRTC_V_BLANK_START_END 0x08e0
#define mmCRTC1_CRTC_V_BLANK_START_END_BASE_IDX 2
#define mmCRTC1_CRTC_V_SYNC_A 0x08e1
#define mmCRTC1_CRTC_V_SYNC_A_BASE_IDX 2
#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x08e2
#define mmCRTC1_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC1_CRTC_V_SYNC_B 0x08e3
#define mmCRTC1_CRTC_V_SYNC_B_BASE_IDX 2
#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x08e4
#define mmCRTC1_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC1_CRTC_DTMTEST_CNTL 0x08e5
#define mmCRTC1_CRTC_DTMTEST_CNTL_BASE_IDX 2
#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x08e6
#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
#define mmCRTC1_CRTC_TRIGA_CNTL 0x08e7
#define mmCRTC1_CRTC_TRIGA_CNTL_BASE_IDX 2
#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x08e8
#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC1_CRTC_TRIGB_CNTL 0x08e9
#define mmCRTC1_CRTC_TRIGB_CNTL_BASE_IDX 2
#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x08ea
#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x08eb
#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmCRTC1_CRTC_FLOW_CONTROL 0x08ec
#define mmCRTC1_CRTC_FLOW_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x08ed
#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x08ee
#define mmCRTC1_CRTC_AVSYNC_COUNTER_BASE_IDX 2
#define mmCRTC1_CRTC_CONTROL 0x08ef
#define mmCRTC1_CRTC_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_BLANK_CONTROL 0x08f0
#define mmCRTC1_CRTC_BLANK_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x08f1
#define mmCRTC1_CRTC_INTERLACE_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_INTERLACE_STATUS 0x08f2
#define mmCRTC1_CRTC_INTERLACE_STATUS_BASE_IDX 2
#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x08f3
#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x08f4
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x08f5
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmCRTC1_CRTC_STATUS 0x08f6
#define mmCRTC1_CRTC_STATUS_BASE_IDX 2
#define mmCRTC1_CRTC_STATUS_POSITION 0x08f7
#define mmCRTC1_CRTC_STATUS_POSITION_BASE_IDX 2
#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x08f8
#define mmCRTC1_CRTC_NOM_VERT_POSITION_BASE_IDX 2
#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x08f9
#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x08fa
#define mmCRTC1_CRTC_STATUS_VF_COUNT_BASE_IDX 2
#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x08fb
#define mmCRTC1_CRTC_STATUS_HV_COUNT_BASE_IDX 2
#define mmCRTC1_CRTC_COUNT_CONTROL 0x08fc
#define mmCRTC1_CRTC_COUNT_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_COUNT_RESET 0x08fd
#define mmCRTC1_CRTC_COUNT_RESET_BASE_IDX 2
#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x08fe
#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x08ff
#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_STEREO_STATUS 0x0900
#define mmCRTC1_CRTC_STEREO_STATUS_BASE_IDX 2
#define mmCRTC1_CRTC_STEREO_CONTROL 0x0901
#define mmCRTC1_CRTC_STEREO_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x0902
#define mmCRTC1_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x0903
#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x0904
#define mmCRTC1_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x0905
#define mmCRTC1_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
#define mmCRTC1_CRTC_START_LINE_CONTROL 0x0906
#define mmCRTC1_CRTC_START_LINE_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x0907
#define mmCRTC1_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_UPDATE_LOCK 0x0908
#define mmCRTC1_CRTC_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x0909
#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x090a
#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x090b
#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x090c
#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x090d
#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x090e
#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x090f
#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x0910
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0911
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
#define mmCRTC1_CRTC_MVP_STATUS 0x0912
#define mmCRTC1_CRTC_MVP_STATUS_BASE_IDX 2
#define mmCRTC1_CRTC_MASTER_EN 0x0913
#define mmCRTC1_CRTC_MASTER_EN_BASE_IDX 2
#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x0914
#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x0915
#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x0917
#define mmCRTC1_CRTC_OVERSCAN_COLOR_BASE_IDX 2
#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x0918
#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x0919
#define mmCRTC1_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x091a
#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmCRTC1_CRTC_BLACK_COLOR 0x091b
#define mmCRTC1_CRTC_BLACK_COLOR_BASE_IDX 2
#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x091c
#define mmCRTC1_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x091d
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x091e
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x091f
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0920
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0921
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0922
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_CRC_CNTL 0x0923
#define mmCRTC1_CRTC_CRC_CNTL_BASE_IDX 2
#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x0924
#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0925
#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x0926
#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0927
#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_CRC0_DATA_RG 0x0928
#define mmCRTC1_CRTC_CRC0_DATA_RG_BASE_IDX 2
#define mmCRTC1_CRTC_CRC0_DATA_B 0x0929
#define mmCRTC1_CRTC_CRC0_DATA_B_BASE_IDX 2
#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x092a
#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x092b
#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x092c
#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x092d
#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_CRC1_DATA_RG 0x092e
#define mmCRTC1_CRTC_CRC1_DATA_RG_BASE_IDX 2
#define mmCRTC1_CRTC_CRC1_DATA_B 0x092f
#define mmCRTC1_CRTC_CRC1_DATA_B_BASE_IDX 2
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x0930
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0931
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0932
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0933
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0934
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0935
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x0936
#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x0937
#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x0938
#define mmCRTC1_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
#define mmCRTC1_CRTC_GSL_WINDOW 0x0939
#define mmCRTC1_CRTC_GSL_WINDOW_BASE_IDX 2
#define mmCRTC1_CRTC_GSL_CONTROL 0x093a
#define mmCRTC1_CRTC_GSL_CONTROL_BASE_IDX 2
#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS 0x093d
#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmCRTC1_CRTC_DRR_CONTROL 0x093e
#define mmCRTC1_CRTC_DRR_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_fmt1_dispdec
// base address: 0x800
#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x0942
#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x0943
#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x0944
#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x0945
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT1_FMT_CONTROL 0x0946
#define mmFMT1_FMT_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x0947
#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x0948
#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x0949
#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x094a
#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_CNTL 0x094e
#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT1_FMT_CRC_CNTL 0x094f
#define mmFMT1_FMT_CRC_CNTL_BASE_IDX 2
#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x0950
#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0951
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x0952
#define mmFMT1_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x0953
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0954
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_420_HBLANK_EARLY_START 0x0955
#define mmFMT1_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
// addressBlock: dce_dc_dcp2_dispdec
// base address: 0x1000
#define mmDCP2_GRPH_ENABLE 0x095a
#define mmDCP2_GRPH_ENABLE_BASE_IDX 2
#define mmDCP2_GRPH_CONTROL 0x095b
#define mmDCP2_GRPH_CONTROL_BASE_IDX 2
#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x095c
#define mmDCP2_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
#define mmDCP2_GRPH_SWAP_CNTL 0x095d
#define mmDCP2_GRPH_SWAP_CNTL_BASE_IDX 2
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x095e
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x095f
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP2_GRPH_PITCH 0x0960
#define mmDCP2_GRPH_PITCH_BASE_IDX 2
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0961
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0962
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x0963
#define mmDCP2_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x0964
#define mmDCP2_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
#define mmDCP2_GRPH_X_START 0x0965
#define mmDCP2_GRPH_X_START_BASE_IDX 2
#define mmDCP2_GRPH_Y_START 0x0966
#define mmDCP2_GRPH_Y_START_BASE_IDX 2
#define mmDCP2_GRPH_X_END 0x0967
#define mmDCP2_GRPH_X_END_BASE_IDX 2
#define mmDCP2_GRPH_Y_END 0x0968
#define mmDCP2_GRPH_Y_END_BASE_IDX 2
#define mmDCP2_INPUT_GAMMA_CONTROL 0x0969
#define mmDCP2_INPUT_GAMMA_CONTROL_BASE_IDX 2
#define mmDCP2_GRPH_UPDATE 0x096a
#define mmDCP2_GRPH_UPDATE_BASE_IDX 2
#define mmDCP2_GRPH_FLIP_CONTROL 0x096b
#define mmDCP2_GRPH_FLIP_CONTROL_BASE_IDX 2
#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x096c
#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
#define mmDCP2_GRPH_DFQ_CONTROL 0x096d
#define mmDCP2_GRPH_DFQ_CONTROL_BASE_IDX 2
#define mmDCP2_GRPH_DFQ_STATUS 0x096e
#define mmDCP2_GRPH_DFQ_STATUS_BASE_IDX 2
#define mmDCP2_GRPH_INTERRUPT_STATUS 0x096f
#define mmDCP2_GRPH_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x0970
#define mmDCP2_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0971
#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x0972
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP2_GRPH_COMPRESS_PITCH 0x0973
#define mmDCP2_GRPH_COMPRESS_PITCH_BASE_IDX 2
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0974
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0975
#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
#define mmDCP2_PRESCALE_GRPH_CONTROL 0x0976
#define mmDCP2_PRESCALE_GRPH_CONTROL_BASE_IDX 2
#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x0977
#define mmDCP2_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x0978
#define mmDCP2_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x0979
#define mmDCP2_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
#define mmDCP2_INPUT_CSC_CONTROL 0x097a
#define mmDCP2_INPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP2_INPUT_CSC_C11_C12 0x097b
#define mmDCP2_INPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP2_INPUT_CSC_C13_C14 0x097c
#define mmDCP2_INPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP2_INPUT_CSC_C21_C22 0x097d
#define mmDCP2_INPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP2_INPUT_CSC_C23_C24 0x097e
#define mmDCP2_INPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP2_INPUT_CSC_C31_C32 0x097f
#define mmDCP2_INPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP2_INPUT_CSC_C33_C34 0x0980
#define mmDCP2_INPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP2_OUTPUT_CSC_CONTROL 0x0981
#define mmDCP2_OUTPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP2_OUTPUT_CSC_C11_C12 0x0982
#define mmDCP2_OUTPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP2_OUTPUT_CSC_C13_C14 0x0983
#define mmDCP2_OUTPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP2_OUTPUT_CSC_C21_C22 0x0984
#define mmDCP2_OUTPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP2_OUTPUT_CSC_C23_C24 0x0985
#define mmDCP2_OUTPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP2_OUTPUT_CSC_C31_C32 0x0986
#define mmDCP2_OUTPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP2_OUTPUT_CSC_C33_C34 0x0987
#define mmDCP2_OUTPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x0988
#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x0989
#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x098a
#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x098b
#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x098c
#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x098d
#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x098e
#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x098f
#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x0990
#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x0991
#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x0992
#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x0993
#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
#define mmDCP2_DENORM_CONTROL 0x0994
#define mmDCP2_DENORM_CONTROL_BASE_IDX 2
#define mmDCP2_OUT_ROUND_CONTROL 0x0995
#define mmDCP2_OUT_ROUND_CONTROL_BASE_IDX 2
#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x0996
#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x0997
#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x0998
#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
#define mmDCP2_KEY_CONTROL 0x0999
#define mmDCP2_KEY_CONTROL_BASE_IDX 2
#define mmDCP2_KEY_RANGE_ALPHA 0x099a
#define mmDCP2_KEY_RANGE_ALPHA_BASE_IDX 2
#define mmDCP2_KEY_RANGE_RED 0x099b
#define mmDCP2_KEY_RANGE_RED_BASE_IDX 2
#define mmDCP2_KEY_RANGE_GREEN 0x099c
#define mmDCP2_KEY_RANGE_GREEN_BASE_IDX 2
#define mmDCP2_KEY_RANGE_BLUE 0x099d
#define mmDCP2_KEY_RANGE_BLUE_BASE_IDX 2
#define mmDCP2_DEGAMMA_CONTROL 0x099e
#define mmDCP2_DEGAMMA_CONTROL_BASE_IDX 2
#define mmDCP2_GAMUT_REMAP_CONTROL 0x099f
#define mmDCP2_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmDCP2_GAMUT_REMAP_C11_C12 0x09a0
#define mmDCP2_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmDCP2_GAMUT_REMAP_C13_C14 0x09a1
#define mmDCP2_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmDCP2_GAMUT_REMAP_C21_C22 0x09a2
#define mmDCP2_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmDCP2_GAMUT_REMAP_C23_C24 0x09a3
#define mmDCP2_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmDCP2_GAMUT_REMAP_C31_C32 0x09a4
#define mmDCP2_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmDCP2_GAMUT_REMAP_C33_C34 0x09a5
#define mmDCP2_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x09a6
#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
#define mmDCP2_DCP_RANDOM_SEEDS 0x09a7
#define mmDCP2_DCP_RANDOM_SEEDS_BASE_IDX 2
#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x09a8
#define mmDCP2_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
#define mmDCP2_CUR_CONTROL 0x09a9
#define mmDCP2_CUR_CONTROL_BASE_IDX 2
#define mmDCP2_CUR_SURFACE_ADDRESS 0x09aa
#define mmDCP2_CUR_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP2_CUR_SIZE 0x09ab
#define mmDCP2_CUR_SIZE_BASE_IDX 2
#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x09ac
#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP2_CUR_POSITION 0x09ad
#define mmDCP2_CUR_POSITION_BASE_IDX 2
#define mmDCP2_CUR_HOT_SPOT 0x09ae
#define mmDCP2_CUR_HOT_SPOT_BASE_IDX 2
#define mmDCP2_CUR_COLOR1 0x09af
#define mmDCP2_CUR_COLOR1_BASE_IDX 2
#define mmDCP2_CUR_COLOR2 0x09b0
#define mmDCP2_CUR_COLOR2_BASE_IDX 2
#define mmDCP2_CUR_UPDATE 0x09b1
#define mmDCP2_CUR_UPDATE_BASE_IDX 2
#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x09bb
#define mmDCP2_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
#define mmDCP2_CUR_STEREO_CONTROL 0x09bc
#define mmDCP2_CUR_STEREO_CONTROL_BASE_IDX 2
#define mmDCP2_DC_LUT_RW_MODE 0x09be
#define mmDCP2_DC_LUT_RW_MODE_BASE_IDX 2
#define mmDCP2_DC_LUT_RW_INDEX 0x09bf
#define mmDCP2_DC_LUT_RW_INDEX_BASE_IDX 2
#define mmDCP2_DC_LUT_SEQ_COLOR 0x09c0
#define mmDCP2_DC_LUT_SEQ_COLOR_BASE_IDX 2
#define mmDCP2_DC_LUT_PWL_DATA 0x09c1
#define mmDCP2_DC_LUT_PWL_DATA_BASE_IDX 2
#define mmDCP2_DC_LUT_30_COLOR 0x09c2
#define mmDCP2_DC_LUT_30_COLOR_BASE_IDX 2
#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x09c3
#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x09c4
#define mmDCP2_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP2_DC_LUT_AUTOFILL 0x09c5
#define mmDCP2_DC_LUT_AUTOFILL_BASE_IDX 2
#define mmDCP2_DC_LUT_CONTROL 0x09c6
#define mmDCP2_DC_LUT_CONTROL_BASE_IDX 2
#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x09c7
#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x09c8
#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x09c9
#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x09ca
#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x09cb
#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x09cc
#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
#define mmDCP2_DCP_CRC_CONTROL 0x09cd
#define mmDCP2_DCP_CRC_CONTROL_BASE_IDX 2
#define mmDCP2_DCP_CRC_MASK 0x09ce
#define mmDCP2_DCP_CRC_MASK_BASE_IDX 2
#define mmDCP2_DCP_CRC_CURRENT 0x09cf
#define mmDCP2_DCP_CRC_CURRENT_BASE_IDX 2
#define mmDCP2_DVMM_PTE_CONTROL 0x09d0
#define mmDCP2_DVMM_PTE_CONTROL_BASE_IDX 2
#define mmDCP2_DCP_CRC_LAST 0x09d1
#define mmDCP2_DCP_CRC_LAST_BASE_IDX 2
#define mmDCP2_DVMM_PTE_ARB_CONTROL 0x09d2
#define mmDCP2_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x09d4
#define mmDCP2_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
#define mmDCP2_DCP_GSL_CONTROL 0x09d5
#define mmDCP2_DCP_GSL_CONTROL_BASE_IDX 2
#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x09d6
#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x09dc
#define mmDCP2_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
#define mmDCP2_HW_ROTATION 0x09de
#define mmDCP2_HW_ROTATION_BASE_IDX 2
#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x09df
#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
#define mmDCP2_REGAMMA_CONTROL 0x09e0
#define mmDCP2_REGAMMA_CONTROL_BASE_IDX 2
#define mmDCP2_REGAMMA_LUT_INDEX 0x09e1
#define mmDCP2_REGAMMA_LUT_INDEX_BASE_IDX 2
#define mmDCP2_REGAMMA_LUT_DATA 0x09e2
#define mmDCP2_REGAMMA_LUT_DATA_BASE_IDX 2
#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x09e3
#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x09e4
#define mmDCP2_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x09e5
#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x09e6
#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x09e7
#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x09e8
#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x09e9
#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x09ea
#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x09eb
#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x09ec
#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x09ed
#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x09ee
#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x09ef
#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x09f0
#define mmDCP2_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x09f1
#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x09f2
#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x09f3
#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x09f4
#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x09f5
#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x09f6
#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x09f7
#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x09f8
#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x09f9
#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x09fa
#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x09fb
#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
#define mmDCP2_ALPHA_CONTROL 0x09fc
#define mmDCP2_ALPHA_CONTROL_BASE_IDX 2
#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x09fd
#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x09fe
#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x09ff
#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT 0x0a00
#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY 0x0a01
#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x0a02
#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x0a03
#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
// addressBlock: dce_dc_lb2_dispdec
// base address: 0x1000
#define mmLB2_LB_DATA_FORMAT 0x0a1a
#define mmLB2_LB_DATA_FORMAT_BASE_IDX 2
#define mmLB2_LB_MEMORY_CTRL 0x0a1b
#define mmLB2_LB_MEMORY_CTRL_BASE_IDX 2
#define mmLB2_LB_MEMORY_SIZE_STATUS 0x0a1c
#define mmLB2_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
#define mmLB2_LB_DESKTOP_HEIGHT 0x0a1d
#define mmLB2_LB_DESKTOP_HEIGHT_BASE_IDX 2
#define mmLB2_LB_VLINE_START_END 0x0a1e
#define mmLB2_LB_VLINE_START_END_BASE_IDX 2
#define mmLB2_LB_VLINE2_START_END 0x0a1f
#define mmLB2_LB_VLINE2_START_END_BASE_IDX 2
#define mmLB2_LB_V_COUNTER 0x0a20
#define mmLB2_LB_V_COUNTER_BASE_IDX 2
#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x0a21
#define mmLB2_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
#define mmLB2_LB_INTERRUPT_MASK 0x0a22
#define mmLB2_LB_INTERRUPT_MASK_BASE_IDX 2
#define mmLB2_LB_VLINE_STATUS 0x0a23
#define mmLB2_LB_VLINE_STATUS_BASE_IDX 2
#define mmLB2_LB_VLINE2_STATUS 0x0a24
#define mmLB2_LB_VLINE2_STATUS_BASE_IDX 2
#define mmLB2_LB_VBLANK_STATUS 0x0a25
#define mmLB2_LB_VBLANK_STATUS_BASE_IDX 2
#define mmLB2_LB_SYNC_RESET_SEL 0x0a26
#define mmLB2_LB_SYNC_RESET_SEL_BASE_IDX 2
#define mmLB2_LB_BLACK_KEYER_R_CR 0x0a27
#define mmLB2_LB_BLACK_KEYER_R_CR_BASE_IDX 2
#define mmLB2_LB_BLACK_KEYER_G_Y 0x0a28
#define mmLB2_LB_BLACK_KEYER_G_Y_BASE_IDX 2
#define mmLB2_LB_BLACK_KEYER_B_CB 0x0a29
#define mmLB2_LB_BLACK_KEYER_B_CB_BASE_IDX 2
#define mmLB2_LB_KEYER_COLOR_CTRL 0x0a2a
#define mmLB2_LB_KEYER_COLOR_CTRL_BASE_IDX 2
#define mmLB2_LB_KEYER_COLOR_R_CR 0x0a2b
#define mmLB2_LB_KEYER_COLOR_R_CR_BASE_IDX 2
#define mmLB2_LB_KEYER_COLOR_G_Y 0x0a2c
#define mmLB2_LB_KEYER_COLOR_G_Y_BASE_IDX 2
#define mmLB2_LB_KEYER_COLOR_B_CB 0x0a2d
#define mmLB2_LB_KEYER_COLOR_B_CB_BASE_IDX 2
#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x0a2e
#define mmLB2_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x0a2f
#define mmLB2_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x0a30
#define mmLB2_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x0a31
#define mmLB2_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x0a32
#define mmLB2_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x0a33
#define mmLB2_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
#define mmLB2_LB_BUFFER_STATUS 0x0a34
#define mmLB2_LB_BUFFER_STATUS_BASE_IDX 2
#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x0a35
#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
#define mmLB2_MVP_AFR_FLIP_MODE 0x0a36
#define mmLB2_MVP_AFR_FLIP_MODE_BASE_IDX 2
#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x0a37
#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x0a38
#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
#define mmLB2_DC_MVP_LB_CONTROL 0x0a39
#define mmLB2_DC_MVP_LB_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dcfe2_dispdec
// base address: 0x1000
#define mmDCFE2_DCFE_CLOCK_CONTROL 0x0a5a
#define mmDCFE2_DCFE_CLOCK_CONTROL_BASE_IDX 2
#define mmDCFE2_DCFE_SOFT_RESET 0x0a5b
#define mmDCFE2_DCFE_SOFT_RESET_BASE_IDX 2
#define mmDCFE2_DCFE_MEM_PWR_CTRL 0x0a5d
#define mmDCFE2_DCFE_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x0a5e
#define mmDCFE2_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDCFE2_DCFE_MEM_PWR_STATUS 0x0a5f
#define mmDCFE2_DCFE_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCFE2_DCFE_MISC 0x0a60
#define mmDCFE2_DCFE_MISC_BASE_IDX 2
#define mmDCFE2_DCFE_FLUSH 0x0a61
#define mmDCFE2_DCFE_FLUSH_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon5_dispdec
// base address: 0x2938
#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0a6e
#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0a6f
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0a70
#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CNTL 0x0a71
#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CNTL2 0x0a72
#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0a73
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0a74
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_HI 0x0a75
#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_LOW 0x0a76
#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmif_pg2_dispdec
// base address: 0x1000
#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x0a7a
#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x0a7b
#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x0a7c
#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x0a7d
#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0a7e
#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x0a7f
#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2 0x0a80
#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL 0x0a81
#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x0a82
#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_BASE_IDX 2
#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x0a86
#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
#define mmDMIF_PG2_DPG_DVMM_STATUS 0x0a87
#define mmDMIF_PG2_DPG_DVMM_STATUS_BASE_IDX 2
// addressBlock: dce_dc_scl2_dispdec
// base address: 0x1000
#define mmSCL2_SCL_COEF_RAM_SELECT 0x0a9a
#define mmSCL2_SCL_COEF_RAM_SELECT_BASE_IDX 2
#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x0a9b
#define mmSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmSCL2_SCL_MODE 0x0a9c
#define mmSCL2_SCL_MODE_BASE_IDX 2
#define mmSCL2_SCL_TAP_CONTROL 0x0a9d
#define mmSCL2_SCL_TAP_CONTROL_BASE_IDX 2
#define mmSCL2_SCL_CONTROL 0x0a9e
#define mmSCL2_SCL_CONTROL_BASE_IDX 2
#define mmSCL2_SCL_BYPASS_CONTROL 0x0a9f
#define mmSCL2_SCL_BYPASS_CONTROL_BASE_IDX 2
#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0aa0
#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x0aa1
#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x0aa2
#define mmSCL2_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0aa3
#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL2_SCL_HORZ_FILTER_INIT 0x0aa4
#define mmSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x0aa5
#define mmSCL2_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0aa6
#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL2_SCL_VERT_FILTER_INIT 0x0aa7
#define mmSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x0aa8
#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmSCL2_SCL_ROUND_OFFSET 0x0aa9
#define mmSCL2_SCL_ROUND_OFFSET_BASE_IDX 2
#define mmSCL2_SCL_UPDATE 0x0aaa
#define mmSCL2_SCL_UPDATE_BASE_IDX 2
#define mmSCL2_SCL_F_SHARP_CONTROL 0x0aab
#define mmSCL2_SCL_F_SHARP_CONTROL_BASE_IDX 2
#define mmSCL2_SCL_ALU_CONTROL 0x0aac
#define mmSCL2_SCL_ALU_CONTROL_BASE_IDX 2
#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x0aad
#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
#define mmSCL2_VIEWPORT_START_SECONDARY 0x0aae
#define mmSCL2_VIEWPORT_START_SECONDARY_BASE_IDX 2
#define mmSCL2_VIEWPORT_START 0x0aaf
#define mmSCL2_VIEWPORT_START_BASE_IDX 2
#define mmSCL2_VIEWPORT_SIZE 0x0ab0
#define mmSCL2_VIEWPORT_SIZE_BASE_IDX 2
#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x0ab1
#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x0ab2
#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmSCL2_SCL_MODE_CHANGE_DET1 0x0ab3
#define mmSCL2_SCL_MODE_CHANGE_DET1_BASE_IDX 2
#define mmSCL2_SCL_MODE_CHANGE_DET2 0x0ab4
#define mmSCL2_SCL_MODE_CHANGE_DET2_BASE_IDX 2
#define mmSCL2_SCL_MODE_CHANGE_DET3 0x0ab5
#define mmSCL2_SCL_MODE_CHANGE_DET3_BASE_IDX 2
#define mmSCL2_SCL_MODE_CHANGE_MASK 0x0ab6
#define mmSCL2_SCL_MODE_CHANGE_MASK_BASE_IDX 2
// addressBlock: dce_dc_blnd2_dispdec
// base address: 0x1000
#define mmBLND2_BLND_CONTROL 0x0ac7
#define mmBLND2_BLND_CONTROL_BASE_IDX 2
#define mmBLND2_BLND_SM_CONTROL2 0x0ac8
#define mmBLND2_BLND_SM_CONTROL2_BASE_IDX 2
#define mmBLND2_BLND_CONTROL2 0x0ac9
#define mmBLND2_BLND_CONTROL2_BASE_IDX 2
#define mmBLND2_BLND_UPDATE 0x0aca
#define mmBLND2_BLND_UPDATE_BASE_IDX 2
#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x0acb
#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
#define mmBLND2_BLND_V_UPDATE_LOCK 0x0acc
#define mmBLND2_BLND_V_UPDATE_LOCK_BASE_IDX 2
#define mmBLND2_BLND_REG_UPDATE_STATUS 0x0acd
#define mmBLND2_BLND_REG_UPDATE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_crtc2_dispdec
// base address: 0x1000
#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x0ad2
#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
#define mmCRTC2_CRTC_H_TOTAL 0x0ad3
#define mmCRTC2_CRTC_H_TOTAL_BASE_IDX 2
#define mmCRTC2_CRTC_H_BLANK_START_END 0x0ad4
#define mmCRTC2_CRTC_H_BLANK_START_END_BASE_IDX 2
#define mmCRTC2_CRTC_H_SYNC_A 0x0ad5
#define mmCRTC2_CRTC_H_SYNC_A_BASE_IDX 2
#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x0ad6
#define mmCRTC2_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC2_CRTC_H_SYNC_B 0x0ad7
#define mmCRTC2_CRTC_H_SYNC_B_BASE_IDX 2
#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x0ad8
#define mmCRTC2_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC2_CRTC_VBI_END 0x0ad9
#define mmCRTC2_CRTC_VBI_END_BASE_IDX 2
#define mmCRTC2_CRTC_V_TOTAL 0x0ada
#define mmCRTC2_CRTC_V_TOTAL_BASE_IDX 2
#define mmCRTC2_CRTC_V_TOTAL_MIN 0x0adb
#define mmCRTC2_CRTC_V_TOTAL_MIN_BASE_IDX 2
#define mmCRTC2_CRTC_V_TOTAL_MAX 0x0adc
#define mmCRTC2_CRTC_V_TOTAL_MAX_BASE_IDX 2
#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x0add
#define mmCRTC2_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x0ade
#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x0adf
#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmCRTC2_CRTC_V_BLANK_START_END 0x0ae0
#define mmCRTC2_CRTC_V_BLANK_START_END_BASE_IDX 2
#define mmCRTC2_CRTC_V_SYNC_A 0x0ae1
#define mmCRTC2_CRTC_V_SYNC_A_BASE_IDX 2
#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x0ae2
#define mmCRTC2_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC2_CRTC_V_SYNC_B 0x0ae3
#define mmCRTC2_CRTC_V_SYNC_B_BASE_IDX 2
#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x0ae4
#define mmCRTC2_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC2_CRTC_DTMTEST_CNTL 0x0ae5
#define mmCRTC2_CRTC_DTMTEST_CNTL_BASE_IDX 2
#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x0ae6
#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
#define mmCRTC2_CRTC_TRIGA_CNTL 0x0ae7
#define mmCRTC2_CRTC_TRIGA_CNTL_BASE_IDX 2
#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x0ae8
#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC2_CRTC_TRIGB_CNTL 0x0ae9
#define mmCRTC2_CRTC_TRIGB_CNTL_BASE_IDX 2
#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x0aea
#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x0aeb
#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmCRTC2_CRTC_FLOW_CONTROL 0x0aec
#define mmCRTC2_CRTC_FLOW_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x0aed
#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x0aee
#define mmCRTC2_CRTC_AVSYNC_COUNTER_BASE_IDX 2
#define mmCRTC2_CRTC_CONTROL 0x0aef
#define mmCRTC2_CRTC_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_BLANK_CONTROL 0x0af0
#define mmCRTC2_CRTC_BLANK_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x0af1
#define mmCRTC2_CRTC_INTERLACE_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_INTERLACE_STATUS 0x0af2
#define mmCRTC2_CRTC_INTERLACE_STATUS_BASE_IDX 2
#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x0af3
#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x0af4
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x0af5
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmCRTC2_CRTC_STATUS 0x0af6
#define mmCRTC2_CRTC_STATUS_BASE_IDX 2
#define mmCRTC2_CRTC_STATUS_POSITION 0x0af7
#define mmCRTC2_CRTC_STATUS_POSITION_BASE_IDX 2
#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x0af8
#define mmCRTC2_CRTC_NOM_VERT_POSITION_BASE_IDX 2
#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x0af9
#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x0afa
#define mmCRTC2_CRTC_STATUS_VF_COUNT_BASE_IDX 2
#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x0afb
#define mmCRTC2_CRTC_STATUS_HV_COUNT_BASE_IDX 2
#define mmCRTC2_CRTC_COUNT_CONTROL 0x0afc
#define mmCRTC2_CRTC_COUNT_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_COUNT_RESET 0x0afd
#define mmCRTC2_CRTC_COUNT_RESET_BASE_IDX 2
#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0afe
#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x0aff
#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_STEREO_STATUS 0x0b00
#define mmCRTC2_CRTC_STEREO_STATUS_BASE_IDX 2
#define mmCRTC2_CRTC_STEREO_CONTROL 0x0b01
#define mmCRTC2_CRTC_STEREO_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x0b02
#define mmCRTC2_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x0b03
#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x0b04
#define mmCRTC2_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x0b05
#define mmCRTC2_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
#define mmCRTC2_CRTC_START_LINE_CONTROL 0x0b06
#define mmCRTC2_CRTC_START_LINE_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x0b07
#define mmCRTC2_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_UPDATE_LOCK 0x0b08
#define mmCRTC2_CRTC_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x0b09
#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0b0a
#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x0b0b
#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x0b0c
#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x0b0d
#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x0b0e
#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x0b0f
#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x0b10
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0b11
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
#define mmCRTC2_CRTC_MVP_STATUS 0x0b12
#define mmCRTC2_CRTC_MVP_STATUS_BASE_IDX 2
#define mmCRTC2_CRTC_MASTER_EN 0x0b13
#define mmCRTC2_CRTC_MASTER_EN_BASE_IDX 2
#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x0b14
#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x0b15
#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x0b17
#define mmCRTC2_CRTC_OVERSCAN_COLOR_BASE_IDX 2
#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x0b18
#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x0b19
#define mmCRTC2_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x0b1a
#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmCRTC2_CRTC_BLACK_COLOR 0x0b1b
#define mmCRTC2_CRTC_BLACK_COLOR_BASE_IDX 2
#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x0b1c
#define mmCRTC2_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0b1d
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0b1e
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0b1f
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0b20
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0b21
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0b22
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_CRC_CNTL 0x0b23
#define mmCRTC2_CRTC_CRC_CNTL_BASE_IDX 2
#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x0b24
#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0b25
#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x0b26
#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0b27
#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_CRC0_DATA_RG 0x0b28
#define mmCRTC2_CRTC_CRC0_DATA_RG_BASE_IDX 2
#define mmCRTC2_CRTC_CRC0_DATA_B 0x0b29
#define mmCRTC2_CRTC_CRC0_DATA_B_BASE_IDX 2
#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x0b2a
#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0b2b
#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x0b2c
#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0b2d
#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_CRC1_DATA_RG 0x0b2e
#define mmCRTC2_CRTC_CRC1_DATA_RG_BASE_IDX 2
#define mmCRTC2_CRTC_CRC1_DATA_B 0x0b2f
#define mmCRTC2_CRTC_CRC1_DATA_B_BASE_IDX 2
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x0b30
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0b31
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0b32
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0b33
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0b34
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0b35
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x0b36
#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x0b37
#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x0b38
#define mmCRTC2_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
#define mmCRTC2_CRTC_GSL_WINDOW 0x0b39
#define mmCRTC2_CRTC_GSL_WINDOW_BASE_IDX 2
#define mmCRTC2_CRTC_GSL_CONTROL 0x0b3a
#define mmCRTC2_CRTC_GSL_CONTROL_BASE_IDX 2
#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS 0x0b3d
#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmCRTC2_CRTC_DRR_CONTROL 0x0b3e
#define mmCRTC2_CRTC_DRR_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_fmt2_dispdec
// base address: 0x1000
#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x0b42
#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x0b43
#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x0b44
#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x0b45
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT2_FMT_CONTROL 0x0b46
#define mmFMT2_FMT_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x0b47
#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x0b48
#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x0b49
#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x0b4a
#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT2_FMT_CLAMP_CNTL 0x0b4e
#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT2_FMT_CRC_CNTL 0x0b4f
#define mmFMT2_FMT_CRC_CNTL_BASE_IDX 2
#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x0b50
#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0b51
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x0b52
#define mmFMT2_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x0b53
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0b54
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_420_HBLANK_EARLY_START 0x0b55
#define mmFMT2_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
// addressBlock: dce_dc_dcp3_dispdec
// base address: 0x1800
#define mmDCP3_GRPH_ENABLE 0x0b5a
#define mmDCP3_GRPH_ENABLE_BASE_IDX 2
#define mmDCP3_GRPH_CONTROL 0x0b5b
#define mmDCP3_GRPH_CONTROL_BASE_IDX 2
#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x0b5c
#define mmDCP3_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
#define mmDCP3_GRPH_SWAP_CNTL 0x0b5d
#define mmDCP3_GRPH_SWAP_CNTL_BASE_IDX 2
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x0b5e
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x0b5f
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP3_GRPH_PITCH 0x0b60
#define mmDCP3_GRPH_PITCH_BASE_IDX 2
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0b61
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0b62
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x0b63
#define mmDCP3_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x0b64
#define mmDCP3_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
#define mmDCP3_GRPH_X_START 0x0b65
#define mmDCP3_GRPH_X_START_BASE_IDX 2
#define mmDCP3_GRPH_Y_START 0x0b66
#define mmDCP3_GRPH_Y_START_BASE_IDX 2
#define mmDCP3_GRPH_X_END 0x0b67
#define mmDCP3_GRPH_X_END_BASE_IDX 2
#define mmDCP3_GRPH_Y_END 0x0b68
#define mmDCP3_GRPH_Y_END_BASE_IDX 2
#define mmDCP3_INPUT_GAMMA_CONTROL 0x0b69
#define mmDCP3_INPUT_GAMMA_CONTROL_BASE_IDX 2
#define mmDCP3_GRPH_UPDATE 0x0b6a
#define mmDCP3_GRPH_UPDATE_BASE_IDX 2
#define mmDCP3_GRPH_FLIP_CONTROL 0x0b6b
#define mmDCP3_GRPH_FLIP_CONTROL_BASE_IDX 2
#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x0b6c
#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
#define mmDCP3_GRPH_DFQ_CONTROL 0x0b6d
#define mmDCP3_GRPH_DFQ_CONTROL_BASE_IDX 2
#define mmDCP3_GRPH_DFQ_STATUS 0x0b6e
#define mmDCP3_GRPH_DFQ_STATUS_BASE_IDX 2
#define mmDCP3_GRPH_INTERRUPT_STATUS 0x0b6f
#define mmDCP3_GRPH_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x0b70
#define mmDCP3_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0b71
#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x0b72
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP3_GRPH_COMPRESS_PITCH 0x0b73
#define mmDCP3_GRPH_COMPRESS_PITCH_BASE_IDX 2
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0b74
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0b75
#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
#define mmDCP3_PRESCALE_GRPH_CONTROL 0x0b76
#define mmDCP3_PRESCALE_GRPH_CONTROL_BASE_IDX 2
#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x0b77
#define mmDCP3_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x0b78
#define mmDCP3_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x0b79
#define mmDCP3_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
#define mmDCP3_INPUT_CSC_CONTROL 0x0b7a
#define mmDCP3_INPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP3_INPUT_CSC_C11_C12 0x0b7b
#define mmDCP3_INPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP3_INPUT_CSC_C13_C14 0x0b7c
#define mmDCP3_INPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP3_INPUT_CSC_C21_C22 0x0b7d
#define mmDCP3_INPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP3_INPUT_CSC_C23_C24 0x0b7e
#define mmDCP3_INPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP3_INPUT_CSC_C31_C32 0x0b7f
#define mmDCP3_INPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP3_INPUT_CSC_C33_C34 0x0b80
#define mmDCP3_INPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP3_OUTPUT_CSC_CONTROL 0x0b81
#define mmDCP3_OUTPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP3_OUTPUT_CSC_C11_C12 0x0b82
#define mmDCP3_OUTPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP3_OUTPUT_CSC_C13_C14 0x0b83
#define mmDCP3_OUTPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP3_OUTPUT_CSC_C21_C22 0x0b84
#define mmDCP3_OUTPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP3_OUTPUT_CSC_C23_C24 0x0b85
#define mmDCP3_OUTPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP3_OUTPUT_CSC_C31_C32 0x0b86
#define mmDCP3_OUTPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP3_OUTPUT_CSC_C33_C34 0x0b87
#define mmDCP3_OUTPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x0b88
#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x0b89
#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x0b8a
#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x0b8b
#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x0b8c
#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x0b8d
#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x0b8e
#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x0b8f
#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x0b90
#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x0b91
#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x0b92
#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x0b93
#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
#define mmDCP3_DENORM_CONTROL 0x0b94
#define mmDCP3_DENORM_CONTROL_BASE_IDX 2
#define mmDCP3_OUT_ROUND_CONTROL 0x0b95
#define mmDCP3_OUT_ROUND_CONTROL_BASE_IDX 2
#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x0b96
#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x0b97
#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x0b98
#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
#define mmDCP3_KEY_CONTROL 0x0b99
#define mmDCP3_KEY_CONTROL_BASE_IDX 2
#define mmDCP3_KEY_RANGE_ALPHA 0x0b9a
#define mmDCP3_KEY_RANGE_ALPHA_BASE_IDX 2
#define mmDCP3_KEY_RANGE_RED 0x0b9b
#define mmDCP3_KEY_RANGE_RED_BASE_IDX 2
#define mmDCP3_KEY_RANGE_GREEN 0x0b9c
#define mmDCP3_KEY_RANGE_GREEN_BASE_IDX 2
#define mmDCP3_KEY_RANGE_BLUE 0x0b9d
#define mmDCP3_KEY_RANGE_BLUE_BASE_IDX 2
#define mmDCP3_DEGAMMA_CONTROL 0x0b9e
#define mmDCP3_DEGAMMA_CONTROL_BASE_IDX 2
#define mmDCP3_GAMUT_REMAP_CONTROL 0x0b9f
#define mmDCP3_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmDCP3_GAMUT_REMAP_C11_C12 0x0ba0
#define mmDCP3_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmDCP3_GAMUT_REMAP_C13_C14 0x0ba1
#define mmDCP3_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmDCP3_GAMUT_REMAP_C21_C22 0x0ba2
#define mmDCP3_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmDCP3_GAMUT_REMAP_C23_C24 0x0ba3
#define mmDCP3_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmDCP3_GAMUT_REMAP_C31_C32 0x0ba4
#define mmDCP3_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmDCP3_GAMUT_REMAP_C33_C34 0x0ba5
#define mmDCP3_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x0ba6
#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
#define mmDCP3_DCP_RANDOM_SEEDS 0x0ba7
#define mmDCP3_DCP_RANDOM_SEEDS_BASE_IDX 2
#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x0ba8
#define mmDCP3_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
#define mmDCP3_CUR_CONTROL 0x0ba9
#define mmDCP3_CUR_CONTROL_BASE_IDX 2
#define mmDCP3_CUR_SURFACE_ADDRESS 0x0baa
#define mmDCP3_CUR_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP3_CUR_SIZE 0x0bab
#define mmDCP3_CUR_SIZE_BASE_IDX 2
#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x0bac
#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP3_CUR_POSITION 0x0bad
#define mmDCP3_CUR_POSITION_BASE_IDX 2
#define mmDCP3_CUR_HOT_SPOT 0x0bae
#define mmDCP3_CUR_HOT_SPOT_BASE_IDX 2
#define mmDCP3_CUR_COLOR1 0x0baf
#define mmDCP3_CUR_COLOR1_BASE_IDX 2
#define mmDCP3_CUR_COLOR2 0x0bb0
#define mmDCP3_CUR_COLOR2_BASE_IDX 2
#define mmDCP3_CUR_UPDATE 0x0bb1
#define mmDCP3_CUR_UPDATE_BASE_IDX 2
#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x0bbb
#define mmDCP3_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
#define mmDCP3_CUR_STEREO_CONTROL 0x0bbc
#define mmDCP3_CUR_STEREO_CONTROL_BASE_IDX 2
#define mmDCP3_DC_LUT_RW_MODE 0x0bbe
#define mmDCP3_DC_LUT_RW_MODE_BASE_IDX 2
#define mmDCP3_DC_LUT_RW_INDEX 0x0bbf
#define mmDCP3_DC_LUT_RW_INDEX_BASE_IDX 2
#define mmDCP3_DC_LUT_SEQ_COLOR 0x0bc0
#define mmDCP3_DC_LUT_SEQ_COLOR_BASE_IDX 2
#define mmDCP3_DC_LUT_PWL_DATA 0x0bc1
#define mmDCP3_DC_LUT_PWL_DATA_BASE_IDX 2
#define mmDCP3_DC_LUT_30_COLOR 0x0bc2
#define mmDCP3_DC_LUT_30_COLOR_BASE_IDX 2
#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x0bc3
#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x0bc4
#define mmDCP3_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP3_DC_LUT_AUTOFILL 0x0bc5
#define mmDCP3_DC_LUT_AUTOFILL_BASE_IDX 2
#define mmDCP3_DC_LUT_CONTROL 0x0bc6
#define mmDCP3_DC_LUT_CONTROL_BASE_IDX 2
#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x0bc7
#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x0bc8
#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x0bc9
#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x0bca
#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x0bcb
#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x0bcc
#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
#define mmDCP3_DCP_CRC_CONTROL 0x0bcd
#define mmDCP3_DCP_CRC_CONTROL_BASE_IDX 2
#define mmDCP3_DCP_CRC_MASK 0x0bce
#define mmDCP3_DCP_CRC_MASK_BASE_IDX 2
#define mmDCP3_DCP_CRC_CURRENT 0x0bcf
#define mmDCP3_DCP_CRC_CURRENT_BASE_IDX 2
#define mmDCP3_DVMM_PTE_CONTROL 0x0bd0
#define mmDCP3_DVMM_PTE_CONTROL_BASE_IDX 2
#define mmDCP3_DCP_CRC_LAST 0x0bd1
#define mmDCP3_DCP_CRC_LAST_BASE_IDX 2
#define mmDCP3_DVMM_PTE_ARB_CONTROL 0x0bd2
#define mmDCP3_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x0bd4
#define mmDCP3_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
#define mmDCP3_DCP_GSL_CONTROL 0x0bd5
#define mmDCP3_DCP_GSL_CONTROL_BASE_IDX 2
#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0bd6
#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x0bdc
#define mmDCP3_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
#define mmDCP3_HW_ROTATION 0x0bde
#define mmDCP3_HW_ROTATION_BASE_IDX 2
#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0bdf
#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
#define mmDCP3_REGAMMA_CONTROL 0x0be0
#define mmDCP3_REGAMMA_CONTROL_BASE_IDX 2
#define mmDCP3_REGAMMA_LUT_INDEX 0x0be1
#define mmDCP3_REGAMMA_LUT_INDEX_BASE_IDX 2
#define mmDCP3_REGAMMA_LUT_DATA 0x0be2
#define mmDCP3_REGAMMA_LUT_DATA_BASE_IDX 2
#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x0be3
#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x0be4
#define mmDCP3_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x0be5
#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x0be6
#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x0be7
#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x0be8
#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x0be9
#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x0bea
#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x0beb
#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x0bec
#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x0bed
#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x0bee
#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x0bef
#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x0bf0
#define mmDCP3_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x0bf1
#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x0bf2
#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x0bf3
#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x0bf4
#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x0bf5
#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x0bf6
#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x0bf7
#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x0bf8
#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x0bf9
#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x0bfa
#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x0bfb
#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
#define mmDCP3_ALPHA_CONTROL 0x0bfc
#define mmDCP3_ALPHA_CONTROL_BASE_IDX 2
#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0bfd
#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0bfe
#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0bff
#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT 0x0c00
#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY 0x0c01
#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x0c02
#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x0c03
#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
// addressBlock: dce_dc_lb3_dispdec
// base address: 0x1800
#define mmLB3_LB_DATA_FORMAT 0x0c1a
#define mmLB3_LB_DATA_FORMAT_BASE_IDX 2
#define mmLB3_LB_MEMORY_CTRL 0x0c1b
#define mmLB3_LB_MEMORY_CTRL_BASE_IDX 2
#define mmLB3_LB_MEMORY_SIZE_STATUS 0x0c1c
#define mmLB3_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
#define mmLB3_LB_DESKTOP_HEIGHT 0x0c1d
#define mmLB3_LB_DESKTOP_HEIGHT_BASE_IDX 2
#define mmLB3_LB_VLINE_START_END 0x0c1e
#define mmLB3_LB_VLINE_START_END_BASE_IDX 2
#define mmLB3_LB_VLINE2_START_END 0x0c1f
#define mmLB3_LB_VLINE2_START_END_BASE_IDX 2
#define mmLB3_LB_V_COUNTER 0x0c20
#define mmLB3_LB_V_COUNTER_BASE_IDX 2
#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x0c21
#define mmLB3_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
#define mmLB3_LB_INTERRUPT_MASK 0x0c22
#define mmLB3_LB_INTERRUPT_MASK_BASE_IDX 2
#define mmLB3_LB_VLINE_STATUS 0x0c23
#define mmLB3_LB_VLINE_STATUS_BASE_IDX 2
#define mmLB3_LB_VLINE2_STATUS 0x0c24
#define mmLB3_LB_VLINE2_STATUS_BASE_IDX 2
#define mmLB3_LB_VBLANK_STATUS 0x0c25
#define mmLB3_LB_VBLANK_STATUS_BASE_IDX 2
#define mmLB3_LB_SYNC_RESET_SEL 0x0c26
#define mmLB3_LB_SYNC_RESET_SEL_BASE_IDX 2
#define mmLB3_LB_BLACK_KEYER_R_CR 0x0c27
#define mmLB3_LB_BLACK_KEYER_R_CR_BASE_IDX 2
#define mmLB3_LB_BLACK_KEYER_G_Y 0x0c28
#define mmLB3_LB_BLACK_KEYER_G_Y_BASE_IDX 2
#define mmLB3_LB_BLACK_KEYER_B_CB 0x0c29
#define mmLB3_LB_BLACK_KEYER_B_CB_BASE_IDX 2
#define mmLB3_LB_KEYER_COLOR_CTRL 0x0c2a
#define mmLB3_LB_KEYER_COLOR_CTRL_BASE_IDX 2
#define mmLB3_LB_KEYER_COLOR_R_CR 0x0c2b
#define mmLB3_LB_KEYER_COLOR_R_CR_BASE_IDX 2
#define mmLB3_LB_KEYER_COLOR_G_Y 0x0c2c
#define mmLB3_LB_KEYER_COLOR_G_Y_BASE_IDX 2
#define mmLB3_LB_KEYER_COLOR_B_CB 0x0c2d
#define mmLB3_LB_KEYER_COLOR_B_CB_BASE_IDX 2
#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x0c2e
#define mmLB3_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x0c2f
#define mmLB3_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x0c30
#define mmLB3_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x0c31
#define mmLB3_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x0c32
#define mmLB3_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x0c33
#define mmLB3_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
#define mmLB3_LB_BUFFER_STATUS 0x0c34
#define mmLB3_LB_BUFFER_STATUS_BASE_IDX 2
#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x0c35
#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
#define mmLB3_MVP_AFR_FLIP_MODE 0x0c36
#define mmLB3_MVP_AFR_FLIP_MODE_BASE_IDX 2
#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x0c37
#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x0c38
#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
#define mmLB3_DC_MVP_LB_CONTROL 0x0c39
#define mmLB3_DC_MVP_LB_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dcfe3_dispdec
// base address: 0x1800
#define mmDCFE3_DCFE_CLOCK_CONTROL 0x0c5a
#define mmDCFE3_DCFE_CLOCK_CONTROL_BASE_IDX 2
#define mmDCFE3_DCFE_SOFT_RESET 0x0c5b
#define mmDCFE3_DCFE_SOFT_RESET_BASE_IDX 2
#define mmDCFE3_DCFE_MEM_PWR_CTRL 0x0c5d
#define mmDCFE3_DCFE_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x0c5e
#define mmDCFE3_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDCFE3_DCFE_MEM_PWR_STATUS 0x0c5f
#define mmDCFE3_DCFE_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCFE3_DCFE_MISC 0x0c60
#define mmDCFE3_DCFE_MISC_BASE_IDX 2
#define mmDCFE3_DCFE_FLUSH 0x0c61
#define mmDCFE3_DCFE_FLUSH_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon6_dispdec
// base address: 0x3138
#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x0c6e
#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x0c6f
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x0c70
#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CNTL 0x0c71
#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CNTL2 0x0c72
#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0c73
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0c74
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_HI 0x0c75
#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_LOW 0x0c76
#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmif_pg3_dispdec
// base address: 0x1800
#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x0c7a
#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x0c7b
#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x0c7c
#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x0c7d
#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0c7e
#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x0c7f
#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2 0x0c80
#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL 0x0c81
#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x0c82
#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_BASE_IDX 2
#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x0c86
#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
#define mmDMIF_PG3_DPG_DVMM_STATUS 0x0c87
#define mmDMIF_PG3_DPG_DVMM_STATUS_BASE_IDX 2
// addressBlock: dce_dc_scl3_dispdec
// base address: 0x1800
#define mmSCL3_SCL_COEF_RAM_SELECT 0x0c9a
#define mmSCL3_SCL_COEF_RAM_SELECT_BASE_IDX 2
#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x0c9b
#define mmSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmSCL3_SCL_MODE 0x0c9c
#define mmSCL3_SCL_MODE_BASE_IDX 2
#define mmSCL3_SCL_TAP_CONTROL 0x0c9d
#define mmSCL3_SCL_TAP_CONTROL_BASE_IDX 2
#define mmSCL3_SCL_CONTROL 0x0c9e
#define mmSCL3_SCL_CONTROL_BASE_IDX 2
#define mmSCL3_SCL_BYPASS_CONTROL 0x0c9f
#define mmSCL3_SCL_BYPASS_CONTROL_BASE_IDX 2
#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0ca0
#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x0ca1
#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x0ca2
#define mmSCL3_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0ca3
#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL3_SCL_HORZ_FILTER_INIT 0x0ca4
#define mmSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x0ca5
#define mmSCL3_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0ca6
#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL3_SCL_VERT_FILTER_INIT 0x0ca7
#define mmSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x0ca8
#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmSCL3_SCL_ROUND_OFFSET 0x0ca9
#define mmSCL3_SCL_ROUND_OFFSET_BASE_IDX 2
#define mmSCL3_SCL_UPDATE 0x0caa
#define mmSCL3_SCL_UPDATE_BASE_IDX 2
#define mmSCL3_SCL_F_SHARP_CONTROL 0x0cab
#define mmSCL3_SCL_F_SHARP_CONTROL_BASE_IDX 2
#define mmSCL3_SCL_ALU_CONTROL 0x0cac
#define mmSCL3_SCL_ALU_CONTROL_BASE_IDX 2
#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x0cad
#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
#define mmSCL3_VIEWPORT_START_SECONDARY 0x0cae
#define mmSCL3_VIEWPORT_START_SECONDARY_BASE_IDX 2
#define mmSCL3_VIEWPORT_START 0x0caf
#define mmSCL3_VIEWPORT_START_BASE_IDX 2
#define mmSCL3_VIEWPORT_SIZE 0x0cb0
#define mmSCL3_VIEWPORT_SIZE_BASE_IDX 2
#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x0cb1
#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x0cb2
#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmSCL3_SCL_MODE_CHANGE_DET1 0x0cb3
#define mmSCL3_SCL_MODE_CHANGE_DET1_BASE_IDX 2
#define mmSCL3_SCL_MODE_CHANGE_DET2 0x0cb4
#define mmSCL3_SCL_MODE_CHANGE_DET2_BASE_IDX 2
#define mmSCL3_SCL_MODE_CHANGE_DET3 0x0cb5
#define mmSCL3_SCL_MODE_CHANGE_DET3_BASE_IDX 2
#define mmSCL3_SCL_MODE_CHANGE_MASK 0x0cb6
#define mmSCL3_SCL_MODE_CHANGE_MASK_BASE_IDX 2
// addressBlock: dce_dc_blnd3_dispdec
// base address: 0x1800
#define mmBLND3_BLND_CONTROL 0x0cc7
#define mmBLND3_BLND_CONTROL_BASE_IDX 2
#define mmBLND3_BLND_SM_CONTROL2 0x0cc8
#define mmBLND3_BLND_SM_CONTROL2_BASE_IDX 2
#define mmBLND3_BLND_CONTROL2 0x0cc9
#define mmBLND3_BLND_CONTROL2_BASE_IDX 2
#define mmBLND3_BLND_UPDATE 0x0cca
#define mmBLND3_BLND_UPDATE_BASE_IDX 2
#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x0ccb
#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
#define mmBLND3_BLND_V_UPDATE_LOCK 0x0ccc
#define mmBLND3_BLND_V_UPDATE_LOCK_BASE_IDX 2
#define mmBLND3_BLND_REG_UPDATE_STATUS 0x0ccd
#define mmBLND3_BLND_REG_UPDATE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_crtc3_dispdec
// base address: 0x1800
#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x0cd2
#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
#define mmCRTC3_CRTC_H_TOTAL 0x0cd3
#define mmCRTC3_CRTC_H_TOTAL_BASE_IDX 2
#define mmCRTC3_CRTC_H_BLANK_START_END 0x0cd4
#define mmCRTC3_CRTC_H_BLANK_START_END_BASE_IDX 2
#define mmCRTC3_CRTC_H_SYNC_A 0x0cd5
#define mmCRTC3_CRTC_H_SYNC_A_BASE_IDX 2
#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x0cd6
#define mmCRTC3_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC3_CRTC_H_SYNC_B 0x0cd7
#define mmCRTC3_CRTC_H_SYNC_B_BASE_IDX 2
#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x0cd8
#define mmCRTC3_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC3_CRTC_VBI_END 0x0cd9
#define mmCRTC3_CRTC_VBI_END_BASE_IDX 2
#define mmCRTC3_CRTC_V_TOTAL 0x0cda
#define mmCRTC3_CRTC_V_TOTAL_BASE_IDX 2
#define mmCRTC3_CRTC_V_TOTAL_MIN 0x0cdb
#define mmCRTC3_CRTC_V_TOTAL_MIN_BASE_IDX 2
#define mmCRTC3_CRTC_V_TOTAL_MAX 0x0cdc
#define mmCRTC3_CRTC_V_TOTAL_MAX_BASE_IDX 2
#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x0cdd
#define mmCRTC3_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x0cde
#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x0cdf
#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmCRTC3_CRTC_V_BLANK_START_END 0x0ce0
#define mmCRTC3_CRTC_V_BLANK_START_END_BASE_IDX 2
#define mmCRTC3_CRTC_V_SYNC_A 0x0ce1
#define mmCRTC3_CRTC_V_SYNC_A_BASE_IDX 2
#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x0ce2
#define mmCRTC3_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC3_CRTC_V_SYNC_B 0x0ce3
#define mmCRTC3_CRTC_V_SYNC_B_BASE_IDX 2
#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x0ce4
#define mmCRTC3_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC3_CRTC_DTMTEST_CNTL 0x0ce5
#define mmCRTC3_CRTC_DTMTEST_CNTL_BASE_IDX 2
#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x0ce6
#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
#define mmCRTC3_CRTC_TRIGA_CNTL 0x0ce7
#define mmCRTC3_CRTC_TRIGA_CNTL_BASE_IDX 2
#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x0ce8
#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC3_CRTC_TRIGB_CNTL 0x0ce9
#define mmCRTC3_CRTC_TRIGB_CNTL_BASE_IDX 2
#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x0cea
#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x0ceb
#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmCRTC3_CRTC_FLOW_CONTROL 0x0cec
#define mmCRTC3_CRTC_FLOW_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x0ced
#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x0cee
#define mmCRTC3_CRTC_AVSYNC_COUNTER_BASE_IDX 2
#define mmCRTC3_CRTC_CONTROL 0x0cef
#define mmCRTC3_CRTC_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_BLANK_CONTROL 0x0cf0
#define mmCRTC3_CRTC_BLANK_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x0cf1
#define mmCRTC3_CRTC_INTERLACE_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_INTERLACE_STATUS 0x0cf2
#define mmCRTC3_CRTC_INTERLACE_STATUS_BASE_IDX 2
#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x0cf3
#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x0cf4
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x0cf5
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmCRTC3_CRTC_STATUS 0x0cf6
#define mmCRTC3_CRTC_STATUS_BASE_IDX 2
#define mmCRTC3_CRTC_STATUS_POSITION 0x0cf7
#define mmCRTC3_CRTC_STATUS_POSITION_BASE_IDX 2
#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x0cf8
#define mmCRTC3_CRTC_NOM_VERT_POSITION_BASE_IDX 2
#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x0cf9
#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x0cfa
#define mmCRTC3_CRTC_STATUS_VF_COUNT_BASE_IDX 2
#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x0cfb
#define mmCRTC3_CRTC_STATUS_HV_COUNT_BASE_IDX 2
#define mmCRTC3_CRTC_COUNT_CONTROL 0x0cfc
#define mmCRTC3_CRTC_COUNT_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_COUNT_RESET 0x0cfd
#define mmCRTC3_CRTC_COUNT_RESET_BASE_IDX 2
#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0cfe
#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x0cff
#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_STEREO_STATUS 0x0d00
#define mmCRTC3_CRTC_STEREO_STATUS_BASE_IDX 2
#define mmCRTC3_CRTC_STEREO_CONTROL 0x0d01
#define mmCRTC3_CRTC_STEREO_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x0d02
#define mmCRTC3_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x0d03
#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x0d04
#define mmCRTC3_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x0d05
#define mmCRTC3_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
#define mmCRTC3_CRTC_START_LINE_CONTROL 0x0d06
#define mmCRTC3_CRTC_START_LINE_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x0d07
#define mmCRTC3_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_UPDATE_LOCK 0x0d08
#define mmCRTC3_CRTC_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x0d09
#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0d0a
#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x0d0b
#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x0d0c
#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x0d0d
#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x0d0e
#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x0d0f
#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x0d10
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0d11
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
#define mmCRTC3_CRTC_MVP_STATUS 0x0d12
#define mmCRTC3_CRTC_MVP_STATUS_BASE_IDX 2
#define mmCRTC3_CRTC_MASTER_EN 0x0d13
#define mmCRTC3_CRTC_MASTER_EN_BASE_IDX 2
#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x0d14
#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x0d15
#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x0d17
#define mmCRTC3_CRTC_OVERSCAN_COLOR_BASE_IDX 2
#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x0d18
#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x0d19
#define mmCRTC3_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x0d1a
#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmCRTC3_CRTC_BLACK_COLOR 0x0d1b
#define mmCRTC3_CRTC_BLACK_COLOR_BASE_IDX 2
#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x0d1c
#define mmCRTC3_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0d1d
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0d1e
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0d1f
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0d20
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0d21
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0d22
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_CRC_CNTL 0x0d23
#define mmCRTC3_CRTC_CRC_CNTL_BASE_IDX 2
#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x0d24
#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0d25
#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x0d26
#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0d27
#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_CRC0_DATA_RG 0x0d28
#define mmCRTC3_CRTC_CRC0_DATA_RG_BASE_IDX 2
#define mmCRTC3_CRTC_CRC0_DATA_B 0x0d29
#define mmCRTC3_CRTC_CRC0_DATA_B_BASE_IDX 2
#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x0d2a
#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0d2b
#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x0d2c
#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0d2d
#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_CRC1_DATA_RG 0x0d2e
#define mmCRTC3_CRTC_CRC1_DATA_RG_BASE_IDX 2
#define mmCRTC3_CRTC_CRC1_DATA_B 0x0d2f
#define mmCRTC3_CRTC_CRC1_DATA_B_BASE_IDX 2
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x0d30
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0d31
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0d32
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0d33
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0d34
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0d35
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x0d36
#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x0d37
#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x0d38
#define mmCRTC3_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
#define mmCRTC3_CRTC_GSL_WINDOW 0x0d39
#define mmCRTC3_CRTC_GSL_WINDOW_BASE_IDX 2
#define mmCRTC3_CRTC_GSL_CONTROL 0x0d3a
#define mmCRTC3_CRTC_GSL_CONTROL_BASE_IDX 2
#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS 0x0d3d
#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmCRTC3_CRTC_DRR_CONTROL 0x0d3e
#define mmCRTC3_CRTC_DRR_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_fmt3_dispdec
// base address: 0x1800
#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x0d42
#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x0d43
#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x0d44
#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x0d45
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT3_FMT_CONTROL 0x0d46
#define mmFMT3_FMT_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x0d47
#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x0d48
#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x0d49
#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x0d4a
#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT3_FMT_CLAMP_CNTL 0x0d4e
#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT3_FMT_CRC_CNTL 0x0d4f
#define mmFMT3_FMT_CRC_CNTL_BASE_IDX 2
#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x0d50
#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0d51
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x0d52
#define mmFMT3_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x0d53
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0d54
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_420_HBLANK_EARLY_START 0x0d55
#define mmFMT3_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
// addressBlock: dce_dc_dcp4_dispdec
// base address: 0x2000
#define mmDCP4_GRPH_ENABLE 0x0d5a
#define mmDCP4_GRPH_ENABLE_BASE_IDX 2
#define mmDCP4_GRPH_CONTROL 0x0d5b
#define mmDCP4_GRPH_CONTROL_BASE_IDX 2
#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x0d5c
#define mmDCP4_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
#define mmDCP4_GRPH_SWAP_CNTL 0x0d5d
#define mmDCP4_GRPH_SWAP_CNTL_BASE_IDX 2
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x0d5e
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x0d5f
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP4_GRPH_PITCH 0x0d60
#define mmDCP4_GRPH_PITCH_BASE_IDX 2
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0d61
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0d62
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x0d63
#define mmDCP4_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x0d64
#define mmDCP4_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
#define mmDCP4_GRPH_X_START 0x0d65
#define mmDCP4_GRPH_X_START_BASE_IDX 2
#define mmDCP4_GRPH_Y_START 0x0d66
#define mmDCP4_GRPH_Y_START_BASE_IDX 2
#define mmDCP4_GRPH_X_END 0x0d67
#define mmDCP4_GRPH_X_END_BASE_IDX 2
#define mmDCP4_GRPH_Y_END 0x0d68
#define mmDCP4_GRPH_Y_END_BASE_IDX 2
#define mmDCP4_INPUT_GAMMA_CONTROL 0x0d69
#define mmDCP4_INPUT_GAMMA_CONTROL_BASE_IDX 2
#define mmDCP4_GRPH_UPDATE 0x0d6a
#define mmDCP4_GRPH_UPDATE_BASE_IDX 2
#define mmDCP4_GRPH_FLIP_CONTROL 0x0d6b
#define mmDCP4_GRPH_FLIP_CONTROL_BASE_IDX 2
#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x0d6c
#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
#define mmDCP4_GRPH_DFQ_CONTROL 0x0d6d
#define mmDCP4_GRPH_DFQ_CONTROL_BASE_IDX 2
#define mmDCP4_GRPH_DFQ_STATUS 0x0d6e
#define mmDCP4_GRPH_DFQ_STATUS_BASE_IDX 2
#define mmDCP4_GRPH_INTERRUPT_STATUS 0x0d6f
#define mmDCP4_GRPH_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x0d70
#define mmDCP4_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0d71
#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x0d72
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP4_GRPH_COMPRESS_PITCH 0x0d73
#define mmDCP4_GRPH_COMPRESS_PITCH_BASE_IDX 2
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0d74
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0d75
#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
#define mmDCP4_PRESCALE_GRPH_CONTROL 0x0d76
#define mmDCP4_PRESCALE_GRPH_CONTROL_BASE_IDX 2
#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x0d77
#define mmDCP4_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x0d78
#define mmDCP4_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x0d79
#define mmDCP4_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
#define mmDCP4_INPUT_CSC_CONTROL 0x0d7a
#define mmDCP4_INPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP4_INPUT_CSC_C11_C12 0x0d7b
#define mmDCP4_INPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP4_INPUT_CSC_C13_C14 0x0d7c
#define mmDCP4_INPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP4_INPUT_CSC_C21_C22 0x0d7d
#define mmDCP4_INPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP4_INPUT_CSC_C23_C24 0x0d7e
#define mmDCP4_INPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP4_INPUT_CSC_C31_C32 0x0d7f
#define mmDCP4_INPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP4_INPUT_CSC_C33_C34 0x0d80
#define mmDCP4_INPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP4_OUTPUT_CSC_CONTROL 0x0d81
#define mmDCP4_OUTPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP4_OUTPUT_CSC_C11_C12 0x0d82
#define mmDCP4_OUTPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP4_OUTPUT_CSC_C13_C14 0x0d83
#define mmDCP4_OUTPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP4_OUTPUT_CSC_C21_C22 0x0d84
#define mmDCP4_OUTPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP4_OUTPUT_CSC_C23_C24 0x0d85
#define mmDCP4_OUTPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP4_OUTPUT_CSC_C31_C32 0x0d86
#define mmDCP4_OUTPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP4_OUTPUT_CSC_C33_C34 0x0d87
#define mmDCP4_OUTPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x0d88
#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x0d89
#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x0d8a
#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x0d8b
#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x0d8c
#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x0d8d
#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x0d8e
#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x0d8f
#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x0d90
#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x0d91
#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x0d92
#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x0d93
#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
#define mmDCP4_DENORM_CONTROL 0x0d94
#define mmDCP4_DENORM_CONTROL_BASE_IDX 2
#define mmDCP4_OUT_ROUND_CONTROL 0x0d95
#define mmDCP4_OUT_ROUND_CONTROL_BASE_IDX 2
#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x0d96
#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x0d97
#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x0d98
#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
#define mmDCP4_KEY_CONTROL 0x0d99
#define mmDCP4_KEY_CONTROL_BASE_IDX 2
#define mmDCP4_KEY_RANGE_ALPHA 0x0d9a
#define mmDCP4_KEY_RANGE_ALPHA_BASE_IDX 2
#define mmDCP4_KEY_RANGE_RED 0x0d9b
#define mmDCP4_KEY_RANGE_RED_BASE_IDX 2
#define mmDCP4_KEY_RANGE_GREEN 0x0d9c
#define mmDCP4_KEY_RANGE_GREEN_BASE_IDX 2
#define mmDCP4_KEY_RANGE_BLUE 0x0d9d
#define mmDCP4_KEY_RANGE_BLUE_BASE_IDX 2
#define mmDCP4_DEGAMMA_CONTROL 0x0d9e
#define mmDCP4_DEGAMMA_CONTROL_BASE_IDX 2
#define mmDCP4_GAMUT_REMAP_CONTROL 0x0d9f
#define mmDCP4_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmDCP4_GAMUT_REMAP_C11_C12 0x0da0
#define mmDCP4_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmDCP4_GAMUT_REMAP_C13_C14 0x0da1
#define mmDCP4_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmDCP4_GAMUT_REMAP_C21_C22 0x0da2
#define mmDCP4_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmDCP4_GAMUT_REMAP_C23_C24 0x0da3
#define mmDCP4_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmDCP4_GAMUT_REMAP_C31_C32 0x0da4
#define mmDCP4_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmDCP4_GAMUT_REMAP_C33_C34 0x0da5
#define mmDCP4_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x0da6
#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
#define mmDCP4_DCP_RANDOM_SEEDS 0x0da7
#define mmDCP4_DCP_RANDOM_SEEDS_BASE_IDX 2
#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x0da8
#define mmDCP4_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
#define mmDCP4_CUR_CONTROL 0x0da9
#define mmDCP4_CUR_CONTROL_BASE_IDX 2
#define mmDCP4_CUR_SURFACE_ADDRESS 0x0daa
#define mmDCP4_CUR_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP4_CUR_SIZE 0x0dab
#define mmDCP4_CUR_SIZE_BASE_IDX 2
#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x0dac
#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP4_CUR_POSITION 0x0dad
#define mmDCP4_CUR_POSITION_BASE_IDX 2
#define mmDCP4_CUR_HOT_SPOT 0x0dae
#define mmDCP4_CUR_HOT_SPOT_BASE_IDX 2
#define mmDCP4_CUR_COLOR1 0x0daf
#define mmDCP4_CUR_COLOR1_BASE_IDX 2
#define mmDCP4_CUR_COLOR2 0x0db0
#define mmDCP4_CUR_COLOR2_BASE_IDX 2
#define mmDCP4_CUR_UPDATE 0x0db1
#define mmDCP4_CUR_UPDATE_BASE_IDX 2
#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x0dbb
#define mmDCP4_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
#define mmDCP4_CUR_STEREO_CONTROL 0x0dbc
#define mmDCP4_CUR_STEREO_CONTROL_BASE_IDX 2
#define mmDCP4_DC_LUT_RW_MODE 0x0dbe
#define mmDCP4_DC_LUT_RW_MODE_BASE_IDX 2
#define mmDCP4_DC_LUT_RW_INDEX 0x0dbf
#define mmDCP4_DC_LUT_RW_INDEX_BASE_IDX 2
#define mmDCP4_DC_LUT_SEQ_COLOR 0x0dc0
#define mmDCP4_DC_LUT_SEQ_COLOR_BASE_IDX 2
#define mmDCP4_DC_LUT_PWL_DATA 0x0dc1
#define mmDCP4_DC_LUT_PWL_DATA_BASE_IDX 2
#define mmDCP4_DC_LUT_30_COLOR 0x0dc2
#define mmDCP4_DC_LUT_30_COLOR_BASE_IDX 2
#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x0dc3
#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x0dc4
#define mmDCP4_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP4_DC_LUT_AUTOFILL 0x0dc5
#define mmDCP4_DC_LUT_AUTOFILL_BASE_IDX 2
#define mmDCP4_DC_LUT_CONTROL 0x0dc6
#define mmDCP4_DC_LUT_CONTROL_BASE_IDX 2
#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x0dc7
#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x0dc8
#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x0dc9
#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x0dca
#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x0dcb
#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x0dcc
#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
#define mmDCP4_DCP_CRC_CONTROL 0x0dcd
#define mmDCP4_DCP_CRC_CONTROL_BASE_IDX 2
#define mmDCP4_DCP_CRC_MASK 0x0dce
#define mmDCP4_DCP_CRC_MASK_BASE_IDX 2
#define mmDCP4_DCP_CRC_CURRENT 0x0dcf
#define mmDCP4_DCP_CRC_CURRENT_BASE_IDX 2
#define mmDCP4_DVMM_PTE_CONTROL 0x0dd0
#define mmDCP4_DVMM_PTE_CONTROL_BASE_IDX 2
#define mmDCP4_DCP_CRC_LAST 0x0dd1
#define mmDCP4_DCP_CRC_LAST_BASE_IDX 2
#define mmDCP4_DVMM_PTE_ARB_CONTROL 0x0dd2
#define mmDCP4_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x0dd4
#define mmDCP4_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
#define mmDCP4_DCP_GSL_CONTROL 0x0dd5
#define mmDCP4_DCP_GSL_CONTROL_BASE_IDX 2
#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0dd6
#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x0ddc
#define mmDCP4_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
#define mmDCP4_HW_ROTATION 0x0dde
#define mmDCP4_HW_ROTATION_BASE_IDX 2
#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0ddf
#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
#define mmDCP4_REGAMMA_CONTROL 0x0de0
#define mmDCP4_REGAMMA_CONTROL_BASE_IDX 2
#define mmDCP4_REGAMMA_LUT_INDEX 0x0de1
#define mmDCP4_REGAMMA_LUT_INDEX_BASE_IDX 2
#define mmDCP4_REGAMMA_LUT_DATA 0x0de2
#define mmDCP4_REGAMMA_LUT_DATA_BASE_IDX 2
#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x0de3
#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x0de4
#define mmDCP4_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x0de5
#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x0de6
#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x0de7
#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x0de8
#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x0de9
#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x0dea
#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x0deb
#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x0dec
#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x0ded
#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x0dee
#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x0def
#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x0df0
#define mmDCP4_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x0df1
#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x0df2
#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x0df3
#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x0df4
#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x0df5
#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x0df6
#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x0df7
#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x0df8
#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x0df9
#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x0dfa
#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x0dfb
#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
#define mmDCP4_ALPHA_CONTROL 0x0dfc
#define mmDCP4_ALPHA_CONTROL_BASE_IDX 2
#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0dfd
#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0dfe
#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0dff
#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT 0x0e00
#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY 0x0e01
#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x0e02
#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x0e03
#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
// addressBlock: dce_dc_lb4_dispdec
// base address: 0x2000
#define mmLB4_LB_DATA_FORMAT 0x0e1a
#define mmLB4_LB_DATA_FORMAT_BASE_IDX 2
#define mmLB4_LB_MEMORY_CTRL 0x0e1b
#define mmLB4_LB_MEMORY_CTRL_BASE_IDX 2
#define mmLB4_LB_MEMORY_SIZE_STATUS 0x0e1c
#define mmLB4_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
#define mmLB4_LB_DESKTOP_HEIGHT 0x0e1d
#define mmLB4_LB_DESKTOP_HEIGHT_BASE_IDX 2
#define mmLB4_LB_VLINE_START_END 0x0e1e
#define mmLB4_LB_VLINE_START_END_BASE_IDX 2
#define mmLB4_LB_VLINE2_START_END 0x0e1f
#define mmLB4_LB_VLINE2_START_END_BASE_IDX 2
#define mmLB4_LB_V_COUNTER 0x0e20
#define mmLB4_LB_V_COUNTER_BASE_IDX 2
#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x0e21
#define mmLB4_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
#define mmLB4_LB_INTERRUPT_MASK 0x0e22
#define mmLB4_LB_INTERRUPT_MASK_BASE_IDX 2
#define mmLB4_LB_VLINE_STATUS 0x0e23
#define mmLB4_LB_VLINE_STATUS_BASE_IDX 2
#define mmLB4_LB_VLINE2_STATUS 0x0e24
#define mmLB4_LB_VLINE2_STATUS_BASE_IDX 2
#define mmLB4_LB_VBLANK_STATUS 0x0e25
#define mmLB4_LB_VBLANK_STATUS_BASE_IDX 2
#define mmLB4_LB_SYNC_RESET_SEL 0x0e26
#define mmLB4_LB_SYNC_RESET_SEL_BASE_IDX 2
#define mmLB4_LB_BLACK_KEYER_R_CR 0x0e27
#define mmLB4_LB_BLACK_KEYER_R_CR_BASE_IDX 2
#define mmLB4_LB_BLACK_KEYER_G_Y 0x0e28
#define mmLB4_LB_BLACK_KEYER_G_Y_BASE_IDX 2
#define mmLB4_LB_BLACK_KEYER_B_CB 0x0e29
#define mmLB4_LB_BLACK_KEYER_B_CB_BASE_IDX 2
#define mmLB4_LB_KEYER_COLOR_CTRL 0x0e2a
#define mmLB4_LB_KEYER_COLOR_CTRL_BASE_IDX 2
#define mmLB4_LB_KEYER_COLOR_R_CR 0x0e2b
#define mmLB4_LB_KEYER_COLOR_R_CR_BASE_IDX 2
#define mmLB4_LB_KEYER_COLOR_G_Y 0x0e2c
#define mmLB4_LB_KEYER_COLOR_G_Y_BASE_IDX 2
#define mmLB4_LB_KEYER_COLOR_B_CB 0x0e2d
#define mmLB4_LB_KEYER_COLOR_B_CB_BASE_IDX 2
#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x0e2e
#define mmLB4_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x0e2f
#define mmLB4_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x0e30
#define mmLB4_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x0e31
#define mmLB4_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x0e32
#define mmLB4_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x0e33
#define mmLB4_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
#define mmLB4_LB_BUFFER_STATUS 0x0e34
#define mmLB4_LB_BUFFER_STATUS_BASE_IDX 2
#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x0e35
#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
#define mmLB4_MVP_AFR_FLIP_MODE 0x0e36
#define mmLB4_MVP_AFR_FLIP_MODE_BASE_IDX 2
#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x0e37
#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x0e38
#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
#define mmLB4_DC_MVP_LB_CONTROL 0x0e39
#define mmLB4_DC_MVP_LB_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dcfe4_dispdec
// base address: 0x2000
#define mmDCFE4_DCFE_CLOCK_CONTROL 0x0e5a
#define mmDCFE4_DCFE_CLOCK_CONTROL_BASE_IDX 2
#define mmDCFE4_DCFE_SOFT_RESET 0x0e5b
#define mmDCFE4_DCFE_SOFT_RESET_BASE_IDX 2
#define mmDCFE4_DCFE_MEM_PWR_CTRL 0x0e5d
#define mmDCFE4_DCFE_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x0e5e
#define mmDCFE4_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDCFE4_DCFE_MEM_PWR_STATUS 0x0e5f
#define mmDCFE4_DCFE_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCFE4_DCFE_MISC 0x0e60
#define mmDCFE4_DCFE_MISC_BASE_IDX 2
#define mmDCFE4_DCFE_FLUSH 0x0e61
#define mmDCFE4_DCFE_FLUSH_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon7_dispdec
// base address: 0x3938
#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0e6e
#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x0e6f
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x0e70
#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CNTL 0x0e71
#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CNTL2 0x0e72
#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0e73
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0e74
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_HI 0x0e75
#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_LOW 0x0e76
#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmif_pg4_dispdec
// base address: 0x2000
#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x0e7a
#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x0e7b
#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x0e7c
#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x0e7d
#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0e7e
#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x0e7f
#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2 0x0e80
#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL 0x0e81
#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x0e82
#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_BASE_IDX 2
#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x0e86
#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
#define mmDMIF_PG4_DPG_DVMM_STATUS 0x0e87
#define mmDMIF_PG4_DPG_DVMM_STATUS_BASE_IDX 2
// addressBlock: dce_dc_scl4_dispdec
// base address: 0x2000
#define mmSCL4_SCL_COEF_RAM_SELECT 0x0e9a
#define mmSCL4_SCL_COEF_RAM_SELECT_BASE_IDX 2
#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x0e9b
#define mmSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmSCL4_SCL_MODE 0x0e9c
#define mmSCL4_SCL_MODE_BASE_IDX 2
#define mmSCL4_SCL_TAP_CONTROL 0x0e9d
#define mmSCL4_SCL_TAP_CONTROL_BASE_IDX 2
#define mmSCL4_SCL_CONTROL 0x0e9e
#define mmSCL4_SCL_CONTROL_BASE_IDX 2
#define mmSCL4_SCL_BYPASS_CONTROL 0x0e9f
#define mmSCL4_SCL_BYPASS_CONTROL_BASE_IDX 2
#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x0ea0
#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x0ea1
#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x0ea2
#define mmSCL4_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x0ea3
#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL4_SCL_HORZ_FILTER_INIT 0x0ea4
#define mmSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x0ea5
#define mmSCL4_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x0ea6
#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL4_SCL_VERT_FILTER_INIT 0x0ea7
#define mmSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x0ea8
#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmSCL4_SCL_ROUND_OFFSET 0x0ea9
#define mmSCL4_SCL_ROUND_OFFSET_BASE_IDX 2
#define mmSCL4_SCL_UPDATE 0x0eaa
#define mmSCL4_SCL_UPDATE_BASE_IDX 2
#define mmSCL4_SCL_F_SHARP_CONTROL 0x0eab
#define mmSCL4_SCL_F_SHARP_CONTROL_BASE_IDX 2
#define mmSCL4_SCL_ALU_CONTROL 0x0eac
#define mmSCL4_SCL_ALU_CONTROL_BASE_IDX 2
#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x0ead
#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
#define mmSCL4_VIEWPORT_START_SECONDARY 0x0eae
#define mmSCL4_VIEWPORT_START_SECONDARY_BASE_IDX 2
#define mmSCL4_VIEWPORT_START 0x0eaf
#define mmSCL4_VIEWPORT_START_BASE_IDX 2
#define mmSCL4_VIEWPORT_SIZE 0x0eb0
#define mmSCL4_VIEWPORT_SIZE_BASE_IDX 2
#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x0eb1
#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x0eb2
#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmSCL4_SCL_MODE_CHANGE_DET1 0x0eb3
#define mmSCL4_SCL_MODE_CHANGE_DET1_BASE_IDX 2
#define mmSCL4_SCL_MODE_CHANGE_DET2 0x0eb4
#define mmSCL4_SCL_MODE_CHANGE_DET2_BASE_IDX 2
#define mmSCL4_SCL_MODE_CHANGE_DET3 0x0eb5
#define mmSCL4_SCL_MODE_CHANGE_DET3_BASE_IDX 2
#define mmSCL4_SCL_MODE_CHANGE_MASK 0x0eb6
#define mmSCL4_SCL_MODE_CHANGE_MASK_BASE_IDX 2
// addressBlock: dce_dc_blnd4_dispdec
// base address: 0x2000
#define mmBLND4_BLND_CONTROL 0x0ec7
#define mmBLND4_BLND_CONTROL_BASE_IDX 2
#define mmBLND4_BLND_SM_CONTROL2 0x0ec8
#define mmBLND4_BLND_SM_CONTROL2_BASE_IDX 2
#define mmBLND4_BLND_CONTROL2 0x0ec9
#define mmBLND4_BLND_CONTROL2_BASE_IDX 2
#define mmBLND4_BLND_UPDATE 0x0eca
#define mmBLND4_BLND_UPDATE_BASE_IDX 2
#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x0ecb
#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
#define mmBLND4_BLND_V_UPDATE_LOCK 0x0ecc
#define mmBLND4_BLND_V_UPDATE_LOCK_BASE_IDX 2
#define mmBLND4_BLND_REG_UPDATE_STATUS 0x0ecd
#define mmBLND4_BLND_REG_UPDATE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_crtc4_dispdec
// base address: 0x2000
#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x0ed2
#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
#define mmCRTC4_CRTC_H_TOTAL 0x0ed3
#define mmCRTC4_CRTC_H_TOTAL_BASE_IDX 2
#define mmCRTC4_CRTC_H_BLANK_START_END 0x0ed4
#define mmCRTC4_CRTC_H_BLANK_START_END_BASE_IDX 2
#define mmCRTC4_CRTC_H_SYNC_A 0x0ed5
#define mmCRTC4_CRTC_H_SYNC_A_BASE_IDX 2
#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x0ed6
#define mmCRTC4_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC4_CRTC_H_SYNC_B 0x0ed7
#define mmCRTC4_CRTC_H_SYNC_B_BASE_IDX 2
#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x0ed8
#define mmCRTC4_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC4_CRTC_VBI_END 0x0ed9
#define mmCRTC4_CRTC_VBI_END_BASE_IDX 2
#define mmCRTC4_CRTC_V_TOTAL 0x0eda
#define mmCRTC4_CRTC_V_TOTAL_BASE_IDX 2
#define mmCRTC4_CRTC_V_TOTAL_MIN 0x0edb
#define mmCRTC4_CRTC_V_TOTAL_MIN_BASE_IDX 2
#define mmCRTC4_CRTC_V_TOTAL_MAX 0x0edc
#define mmCRTC4_CRTC_V_TOTAL_MAX_BASE_IDX 2
#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x0edd
#define mmCRTC4_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x0ede
#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x0edf
#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmCRTC4_CRTC_V_BLANK_START_END 0x0ee0
#define mmCRTC4_CRTC_V_BLANK_START_END_BASE_IDX 2
#define mmCRTC4_CRTC_V_SYNC_A 0x0ee1
#define mmCRTC4_CRTC_V_SYNC_A_BASE_IDX 2
#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x0ee2
#define mmCRTC4_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC4_CRTC_V_SYNC_B 0x0ee3
#define mmCRTC4_CRTC_V_SYNC_B_BASE_IDX 2
#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x0ee4
#define mmCRTC4_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC4_CRTC_DTMTEST_CNTL 0x0ee5
#define mmCRTC4_CRTC_DTMTEST_CNTL_BASE_IDX 2
#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x0ee6
#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
#define mmCRTC4_CRTC_TRIGA_CNTL 0x0ee7
#define mmCRTC4_CRTC_TRIGA_CNTL_BASE_IDX 2
#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x0ee8
#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC4_CRTC_TRIGB_CNTL 0x0ee9
#define mmCRTC4_CRTC_TRIGB_CNTL_BASE_IDX 2
#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x0eea
#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x0eeb
#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmCRTC4_CRTC_FLOW_CONTROL 0x0eec
#define mmCRTC4_CRTC_FLOW_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x0eed
#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x0eee
#define mmCRTC4_CRTC_AVSYNC_COUNTER_BASE_IDX 2
#define mmCRTC4_CRTC_CONTROL 0x0eef
#define mmCRTC4_CRTC_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_BLANK_CONTROL 0x0ef0
#define mmCRTC4_CRTC_BLANK_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x0ef1
#define mmCRTC4_CRTC_INTERLACE_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_INTERLACE_STATUS 0x0ef2
#define mmCRTC4_CRTC_INTERLACE_STATUS_BASE_IDX 2
#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x0ef3
#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x0ef4
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x0ef5
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmCRTC4_CRTC_STATUS 0x0ef6
#define mmCRTC4_CRTC_STATUS_BASE_IDX 2
#define mmCRTC4_CRTC_STATUS_POSITION 0x0ef7
#define mmCRTC4_CRTC_STATUS_POSITION_BASE_IDX 2
#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x0ef8
#define mmCRTC4_CRTC_NOM_VERT_POSITION_BASE_IDX 2
#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x0ef9
#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x0efa
#define mmCRTC4_CRTC_STATUS_VF_COUNT_BASE_IDX 2
#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x0efb
#define mmCRTC4_CRTC_STATUS_HV_COUNT_BASE_IDX 2
#define mmCRTC4_CRTC_COUNT_CONTROL 0x0efc
#define mmCRTC4_CRTC_COUNT_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_COUNT_RESET 0x0efd
#define mmCRTC4_CRTC_COUNT_RESET_BASE_IDX 2
#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0efe
#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x0eff
#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_STEREO_STATUS 0x0f00
#define mmCRTC4_CRTC_STEREO_STATUS_BASE_IDX 2
#define mmCRTC4_CRTC_STEREO_CONTROL 0x0f01
#define mmCRTC4_CRTC_STEREO_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x0f02
#define mmCRTC4_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x0f03
#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x0f04
#define mmCRTC4_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x0f05
#define mmCRTC4_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
#define mmCRTC4_CRTC_START_LINE_CONTROL 0x0f06
#define mmCRTC4_CRTC_START_LINE_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x0f07
#define mmCRTC4_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_UPDATE_LOCK 0x0f08
#define mmCRTC4_CRTC_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x0f09
#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0f0a
#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x0f0b
#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x0f0c
#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x0f0d
#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x0f0e
#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x0f0f
#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x0f10
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0f11
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
#define mmCRTC4_CRTC_MVP_STATUS 0x0f12
#define mmCRTC4_CRTC_MVP_STATUS_BASE_IDX 2
#define mmCRTC4_CRTC_MASTER_EN 0x0f13
#define mmCRTC4_CRTC_MASTER_EN_BASE_IDX 2
#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x0f14
#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x0f15
#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x0f17
#define mmCRTC4_CRTC_OVERSCAN_COLOR_BASE_IDX 2
#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x0f18
#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x0f19
#define mmCRTC4_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x0f1a
#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmCRTC4_CRTC_BLACK_COLOR 0x0f1b
#define mmCRTC4_CRTC_BLACK_COLOR_BASE_IDX 2
#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x0f1c
#define mmCRTC4_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0f1d
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0f1e
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0f1f
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0f20
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0f21
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0f22
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_CRC_CNTL 0x0f23
#define mmCRTC4_CRTC_CRC_CNTL_BASE_IDX 2
#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x0f24
#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0f25
#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x0f26
#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0f27
#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_CRC0_DATA_RG 0x0f28
#define mmCRTC4_CRTC_CRC0_DATA_RG_BASE_IDX 2
#define mmCRTC4_CRTC_CRC0_DATA_B 0x0f29
#define mmCRTC4_CRTC_CRC0_DATA_B_BASE_IDX 2
#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x0f2a
#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0f2b
#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x0f2c
#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0f2d
#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_CRC1_DATA_RG 0x0f2e
#define mmCRTC4_CRTC_CRC1_DATA_RG_BASE_IDX 2
#define mmCRTC4_CRTC_CRC1_DATA_B 0x0f2f
#define mmCRTC4_CRTC_CRC1_DATA_B_BASE_IDX 2
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x0f30
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0f31
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0f32
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0f33
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0f34
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0f35
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x0f36
#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x0f37
#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x0f38
#define mmCRTC4_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
#define mmCRTC4_CRTC_GSL_WINDOW 0x0f39
#define mmCRTC4_CRTC_GSL_WINDOW_BASE_IDX 2
#define mmCRTC4_CRTC_GSL_CONTROL 0x0f3a
#define mmCRTC4_CRTC_GSL_CONTROL_BASE_IDX 2
#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS 0x0f3d
#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e
#define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x395d
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
// addressBlock: dce_dc_fmt4_dispdec
// base address: 0x2000
#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x0f42
#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x0f43
#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x0f44
#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x0f45
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT4_FMT_CONTROL 0x0f46
#define mmFMT4_FMT_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x0f47
#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x0f48
#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x0f49
#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x0f4a
#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT4_FMT_CLAMP_CNTL 0x0f4e
#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT4_FMT_CRC_CNTL 0x0f4f
#define mmFMT4_FMT_CRC_CNTL_BASE_IDX 2
#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x0f50
#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0f51
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x0f52
#define mmFMT4_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x0f53
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0f54
#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_420_HBLANK_EARLY_START 0x0f55
#define mmFMT4_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
// addressBlock: dce_dc_dcp5_dispdec
// base address: 0x2800
#define mmDCP5_GRPH_ENABLE 0x0f5a
#define mmDCP5_GRPH_ENABLE_BASE_IDX 2
#define mmDCP5_GRPH_CONTROL 0x0f5b
#define mmDCP5_GRPH_CONTROL_BASE_IDX 2
#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x0f5c
#define mmDCP5_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
#define mmDCP5_GRPH_SWAP_CNTL 0x0f5d
#define mmDCP5_GRPH_SWAP_CNTL_BASE_IDX 2
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x0f5e
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x0f5f
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP5_GRPH_PITCH 0x0f60
#define mmDCP5_GRPH_PITCH_BASE_IDX 2
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0f61
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0f62
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x0f63
#define mmDCP5_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x0f64
#define mmDCP5_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
#define mmDCP5_GRPH_X_START 0x0f65
#define mmDCP5_GRPH_X_START_BASE_IDX 2
#define mmDCP5_GRPH_Y_START 0x0f66
#define mmDCP5_GRPH_Y_START_BASE_IDX 2
#define mmDCP5_GRPH_X_END 0x0f67
#define mmDCP5_GRPH_X_END_BASE_IDX 2
#define mmDCP5_GRPH_Y_END 0x0f68
#define mmDCP5_GRPH_Y_END_BASE_IDX 2
#define mmDCP5_INPUT_GAMMA_CONTROL 0x0f69
#define mmDCP5_INPUT_GAMMA_CONTROL_BASE_IDX 2
#define mmDCP5_GRPH_UPDATE 0x0f6a
#define mmDCP5_GRPH_UPDATE_BASE_IDX 2
#define mmDCP5_GRPH_FLIP_CONTROL 0x0f6b
#define mmDCP5_GRPH_FLIP_CONTROL_BASE_IDX 2
#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x0f6c
#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
#define mmDCP5_GRPH_DFQ_CONTROL 0x0f6d
#define mmDCP5_GRPH_DFQ_CONTROL_BASE_IDX 2
#define mmDCP5_GRPH_DFQ_STATUS 0x0f6e
#define mmDCP5_GRPH_DFQ_STATUS_BASE_IDX 2
#define mmDCP5_GRPH_INTERRUPT_STATUS 0x0f6f
#define mmDCP5_GRPH_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x0f70
#define mmDCP5_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0f71
#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x0f72
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP5_GRPH_COMPRESS_PITCH 0x0f73
#define mmDCP5_GRPH_COMPRESS_PITCH_BASE_IDX 2
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0f74
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0f75
#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
#define mmDCP5_PRESCALE_GRPH_CONTROL 0x0f76
#define mmDCP5_PRESCALE_GRPH_CONTROL_BASE_IDX 2
#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x0f77
#define mmDCP5_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x0f78
#define mmDCP5_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x0f79
#define mmDCP5_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
#define mmDCP5_INPUT_CSC_CONTROL 0x0f7a
#define mmDCP5_INPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP5_INPUT_CSC_C11_C12 0x0f7b
#define mmDCP5_INPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP5_INPUT_CSC_C13_C14 0x0f7c
#define mmDCP5_INPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP5_INPUT_CSC_C21_C22 0x0f7d
#define mmDCP5_INPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP5_INPUT_CSC_C23_C24 0x0f7e
#define mmDCP5_INPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP5_INPUT_CSC_C31_C32 0x0f7f
#define mmDCP5_INPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP5_INPUT_CSC_C33_C34 0x0f80
#define mmDCP5_INPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP5_OUTPUT_CSC_CONTROL 0x0f81
#define mmDCP5_OUTPUT_CSC_CONTROL_BASE_IDX 2
#define mmDCP5_OUTPUT_CSC_C11_C12 0x0f82
#define mmDCP5_OUTPUT_CSC_C11_C12_BASE_IDX 2
#define mmDCP5_OUTPUT_CSC_C13_C14 0x0f83
#define mmDCP5_OUTPUT_CSC_C13_C14_BASE_IDX 2
#define mmDCP5_OUTPUT_CSC_C21_C22 0x0f84
#define mmDCP5_OUTPUT_CSC_C21_C22_BASE_IDX 2
#define mmDCP5_OUTPUT_CSC_C23_C24 0x0f85
#define mmDCP5_OUTPUT_CSC_C23_C24_BASE_IDX 2
#define mmDCP5_OUTPUT_CSC_C31_C32 0x0f86
#define mmDCP5_OUTPUT_CSC_C31_C32_BASE_IDX 2
#define mmDCP5_OUTPUT_CSC_C33_C34 0x0f87
#define mmDCP5_OUTPUT_CSC_C33_C34_BASE_IDX 2
#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x0f88
#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x0f89
#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x0f8a
#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x0f8b
#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x0f8c
#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x0f8d
#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x0f8e
#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x0f8f
#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x0f90
#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x0f91
#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x0f92
#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x0f93
#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
#define mmDCP5_DENORM_CONTROL 0x0f94
#define mmDCP5_DENORM_CONTROL_BASE_IDX 2
#define mmDCP5_OUT_ROUND_CONTROL 0x0f95
#define mmDCP5_OUT_ROUND_CONTROL_BASE_IDX 2
#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x0f96
#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x0f97
#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x0f98
#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
#define mmDCP5_KEY_CONTROL 0x0f99
#define mmDCP5_KEY_CONTROL_BASE_IDX 2
#define mmDCP5_KEY_RANGE_ALPHA 0x0f9a
#define mmDCP5_KEY_RANGE_ALPHA_BASE_IDX 2
#define mmDCP5_KEY_RANGE_RED 0x0f9b
#define mmDCP5_KEY_RANGE_RED_BASE_IDX 2
#define mmDCP5_KEY_RANGE_GREEN 0x0f9c
#define mmDCP5_KEY_RANGE_GREEN_BASE_IDX 2
#define mmDCP5_KEY_RANGE_BLUE 0x0f9d
#define mmDCP5_KEY_RANGE_BLUE_BASE_IDX 2
#define mmDCP5_DEGAMMA_CONTROL 0x0f9e
#define mmDCP5_DEGAMMA_CONTROL_BASE_IDX 2
#define mmDCP5_GAMUT_REMAP_CONTROL 0x0f9f
#define mmDCP5_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmDCP5_GAMUT_REMAP_C11_C12 0x0fa0
#define mmDCP5_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmDCP5_GAMUT_REMAP_C13_C14 0x0fa1
#define mmDCP5_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmDCP5_GAMUT_REMAP_C21_C22 0x0fa2
#define mmDCP5_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmDCP5_GAMUT_REMAP_C23_C24 0x0fa3
#define mmDCP5_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmDCP5_GAMUT_REMAP_C31_C32 0x0fa4
#define mmDCP5_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmDCP5_GAMUT_REMAP_C33_C34 0x0fa5
#define mmDCP5_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x0fa6
#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
#define mmDCP5_DCP_RANDOM_SEEDS 0x0fa7
#define mmDCP5_DCP_RANDOM_SEEDS_BASE_IDX 2
#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x0fa8
#define mmDCP5_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
#define mmDCP5_CUR_CONTROL 0x0fa9
#define mmDCP5_CUR_CONTROL_BASE_IDX 2
#define mmDCP5_CUR_SURFACE_ADDRESS 0x0faa
#define mmDCP5_CUR_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP5_CUR_SIZE 0x0fab
#define mmDCP5_CUR_SIZE_BASE_IDX 2
#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x0fac
#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP5_CUR_POSITION 0x0fad
#define mmDCP5_CUR_POSITION_BASE_IDX 2
#define mmDCP5_CUR_HOT_SPOT 0x0fae
#define mmDCP5_CUR_HOT_SPOT_BASE_IDX 2
#define mmDCP5_CUR_COLOR1 0x0faf
#define mmDCP5_CUR_COLOR1_BASE_IDX 2
#define mmDCP5_CUR_COLOR2 0x0fb0
#define mmDCP5_CUR_COLOR2_BASE_IDX 2
#define mmDCP5_CUR_UPDATE 0x0fb1
#define mmDCP5_CUR_UPDATE_BASE_IDX 2
#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x0fbb
#define mmDCP5_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
#define mmDCP5_CUR_STEREO_CONTROL 0x0fbc
#define mmDCP5_CUR_STEREO_CONTROL_BASE_IDX 2
#define mmDCP5_DC_LUT_RW_MODE 0x0fbe
#define mmDCP5_DC_LUT_RW_MODE_BASE_IDX 2
#define mmDCP5_DC_LUT_RW_INDEX 0x0fbf
#define mmDCP5_DC_LUT_RW_INDEX_BASE_IDX 2
#define mmDCP5_DC_LUT_SEQ_COLOR 0x0fc0
#define mmDCP5_DC_LUT_SEQ_COLOR_BASE_IDX 2
#define mmDCP5_DC_LUT_PWL_DATA 0x0fc1
#define mmDCP5_DC_LUT_PWL_DATA_BASE_IDX 2
#define mmDCP5_DC_LUT_30_COLOR 0x0fc2
#define mmDCP5_DC_LUT_30_COLOR_BASE_IDX 2
#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x0fc3
#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x0fc4
#define mmDCP5_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP5_DC_LUT_AUTOFILL 0x0fc5
#define mmDCP5_DC_LUT_AUTOFILL_BASE_IDX 2
#define mmDCP5_DC_LUT_CONTROL 0x0fc6
#define mmDCP5_DC_LUT_CONTROL_BASE_IDX 2
#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x0fc7
#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x0fc8
#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x0fc9
#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x0fca
#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x0fcb
#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x0fcc
#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
#define mmDCP5_DCP_CRC_CONTROL 0x0fcd
#define mmDCP5_DCP_CRC_CONTROL_BASE_IDX 2
#define mmDCP5_DCP_CRC_MASK 0x0fce
#define mmDCP5_DCP_CRC_MASK_BASE_IDX 2
#define mmDCP5_DCP_CRC_CURRENT 0x0fcf
#define mmDCP5_DCP_CRC_CURRENT_BASE_IDX 2
#define mmDCP5_DVMM_PTE_CONTROL 0x0fd0
#define mmDCP5_DVMM_PTE_CONTROL_BASE_IDX 2
#define mmDCP5_DCP_CRC_LAST 0x0fd1
#define mmDCP5_DCP_CRC_LAST_BASE_IDX 2
#define mmDCP5_DVMM_PTE_ARB_CONTROL 0x0fd2
#define mmDCP5_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x0fd4
#define mmDCP5_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
#define mmDCP5_DCP_GSL_CONTROL 0x0fd5
#define mmDCP5_DCP_GSL_CONTROL_BASE_IDX 2
#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0fd6
#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x0fdc
#define mmDCP5_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
#define mmDCP5_HW_ROTATION 0x0fde
#define mmDCP5_HW_ROTATION_BASE_IDX 2
#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0fdf
#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
#define mmDCP5_REGAMMA_CONTROL 0x0fe0
#define mmDCP5_REGAMMA_CONTROL_BASE_IDX 2
#define mmDCP5_REGAMMA_LUT_INDEX 0x0fe1
#define mmDCP5_REGAMMA_LUT_INDEX_BASE_IDX 2
#define mmDCP5_REGAMMA_LUT_DATA 0x0fe2
#define mmDCP5_REGAMMA_LUT_DATA_BASE_IDX 2
#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x0fe3
#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x0fe4
#define mmDCP5_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x0fe5
#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x0fe6
#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x0fe7
#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x0fe8
#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x0fe9
#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x0fea
#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x0feb
#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x0fec
#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x0fed
#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x0fee
#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x0fef
#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x0ff0
#define mmDCP5_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x0ff1
#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x0ff2
#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x0ff3
#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x0ff4
#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x0ff5
#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x0ff6
#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x0ff7
#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x0ff8
#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x0ff9
#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x0ffa
#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x0ffb
#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
#define mmDCP5_ALPHA_CONTROL 0x0ffc
#define mmDCP5_ALPHA_CONTROL_BASE_IDX 2
#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0ffd
#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0ffe
#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0fff
#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT 0x1000
#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY 0x1001
#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x1002
#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x1003
#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
// addressBlock: dce_dc_lb5_dispdec
// base address: 0x2800
#define mmLB5_LB_DATA_FORMAT 0x101a
#define mmLB5_LB_DATA_FORMAT_BASE_IDX 2
#define mmLB5_LB_MEMORY_CTRL 0x101b
#define mmLB5_LB_MEMORY_CTRL_BASE_IDX 2
#define mmLB5_LB_MEMORY_SIZE_STATUS 0x101c
#define mmLB5_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
#define mmLB5_LB_DESKTOP_HEIGHT 0x101d
#define mmLB5_LB_DESKTOP_HEIGHT_BASE_IDX 2
#define mmLB5_LB_VLINE_START_END 0x101e
#define mmLB5_LB_VLINE_START_END_BASE_IDX 2
#define mmLB5_LB_VLINE2_START_END 0x101f
#define mmLB5_LB_VLINE2_START_END_BASE_IDX 2
#define mmLB5_LB_V_COUNTER 0x1020
#define mmLB5_LB_V_COUNTER_BASE_IDX 2
#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x1021
#define mmLB5_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
#define mmLB5_LB_INTERRUPT_MASK 0x1022
#define mmLB5_LB_INTERRUPT_MASK_BASE_IDX 2
#define mmLB5_LB_VLINE_STATUS 0x1023
#define mmLB5_LB_VLINE_STATUS_BASE_IDX 2
#define mmLB5_LB_VLINE2_STATUS 0x1024
#define mmLB5_LB_VLINE2_STATUS_BASE_IDX 2
#define mmLB5_LB_VBLANK_STATUS 0x1025
#define mmLB5_LB_VBLANK_STATUS_BASE_IDX 2
#define mmLB5_LB_SYNC_RESET_SEL 0x1026
#define mmLB5_LB_SYNC_RESET_SEL_BASE_IDX 2
#define mmLB5_LB_BLACK_KEYER_R_CR 0x1027
#define mmLB5_LB_BLACK_KEYER_R_CR_BASE_IDX 2
#define mmLB5_LB_BLACK_KEYER_G_Y 0x1028
#define mmLB5_LB_BLACK_KEYER_G_Y_BASE_IDX 2
#define mmLB5_LB_BLACK_KEYER_B_CB 0x1029
#define mmLB5_LB_BLACK_KEYER_B_CB_BASE_IDX 2
#define mmLB5_LB_KEYER_COLOR_CTRL 0x102a
#define mmLB5_LB_KEYER_COLOR_CTRL_BASE_IDX 2
#define mmLB5_LB_KEYER_COLOR_R_CR 0x102b
#define mmLB5_LB_KEYER_COLOR_R_CR_BASE_IDX 2
#define mmLB5_LB_KEYER_COLOR_G_Y 0x102c
#define mmLB5_LB_KEYER_COLOR_G_Y_BASE_IDX 2
#define mmLB5_LB_KEYER_COLOR_B_CB 0x102d
#define mmLB5_LB_KEYER_COLOR_B_CB_BASE_IDX 2
#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x102e
#define mmLB5_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x102f
#define mmLB5_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x1030
#define mmLB5_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x1031
#define mmLB5_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x1032
#define mmLB5_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x1033
#define mmLB5_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
#define mmLB5_LB_BUFFER_STATUS 0x1034
#define mmLB5_LB_BUFFER_STATUS_BASE_IDX 2
#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x1035
#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
#define mmLB5_MVP_AFR_FLIP_MODE 0x1036
#define mmLB5_MVP_AFR_FLIP_MODE_BASE_IDX 2
#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x1037
#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x1038
#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
#define mmLB5_DC_MVP_LB_CONTROL 0x1039
#define mmLB5_DC_MVP_LB_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dcfe5_dispdec
// base address: 0x2800
#define mmDCFE5_DCFE_CLOCK_CONTROL 0x105a
#define mmDCFE5_DCFE_CLOCK_CONTROL_BASE_IDX 2
#define mmDCFE5_DCFE_SOFT_RESET 0x105b
#define mmDCFE5_DCFE_SOFT_RESET_BASE_IDX 2
#define mmDCFE5_DCFE_MEM_PWR_CTRL 0x105d
#define mmDCFE5_DCFE_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x105e
#define mmDCFE5_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDCFE5_DCFE_MEM_PWR_STATUS 0x105f
#define mmDCFE5_DCFE_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCFE5_DCFE_MISC 0x1060
#define mmDCFE5_DCFE_MISC_BASE_IDX 2
#define mmDCFE5_DCFE_FLUSH 0x1061
#define mmDCFE5_DCFE_FLUSH_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon8_dispdec
// base address: 0x4138
#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x106e
#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x106f
#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x1070
#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CNTL 0x1071
#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CNTL2 0x1072
#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x1073
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x1074
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_HI 0x1075
#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_LOW 0x1076
#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmif_pg5_dispdec
// base address: 0x2800
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x107a
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x107b
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x107c
#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x107d
#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL 0x107e
#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x107f
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2 0x1080
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL 0x1081
#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x1082
#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_BASE_IDX 2
#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x1086
#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
#define mmDMIF_PG5_DPG_DVMM_STATUS 0x1087
#define mmDMIF_PG5_DPG_DVMM_STATUS_BASE_IDX 2
// addressBlock: dce_dc_scl5_dispdec
// base address: 0x2800
#define mmSCL5_SCL_COEF_RAM_SELECT 0x109a
#define mmSCL5_SCL_COEF_RAM_SELECT_BASE_IDX 2
#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x109b
#define mmSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmSCL5_SCL_MODE 0x109c
#define mmSCL5_SCL_MODE_BASE_IDX 2
#define mmSCL5_SCL_TAP_CONTROL 0x109d
#define mmSCL5_SCL_TAP_CONTROL_BASE_IDX 2
#define mmSCL5_SCL_CONTROL 0x109e
#define mmSCL5_SCL_CONTROL_BASE_IDX 2
#define mmSCL5_SCL_BYPASS_CONTROL 0x109f
#define mmSCL5_SCL_BYPASS_CONTROL_BASE_IDX 2
#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x10a0
#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x10a1
#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x10a2
#define mmSCL5_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x10a3
#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL5_SCL_HORZ_FILTER_INIT 0x10a4
#define mmSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x10a5
#define mmSCL5_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x10a6
#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCL5_SCL_VERT_FILTER_INIT 0x10a7
#define mmSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x10a8
#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmSCL5_SCL_ROUND_OFFSET 0x10a9
#define mmSCL5_SCL_ROUND_OFFSET_BASE_IDX 2
#define mmSCL5_SCL_UPDATE 0x10aa
#define mmSCL5_SCL_UPDATE_BASE_IDX 2
#define mmSCL5_SCL_F_SHARP_CONTROL 0x10ab
#define mmSCL5_SCL_F_SHARP_CONTROL_BASE_IDX 2
#define mmSCL5_SCL_ALU_CONTROL 0x10ac
#define mmSCL5_SCL_ALU_CONTROL_BASE_IDX 2
#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x10ad
#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
#define mmSCL5_VIEWPORT_START_SECONDARY 0x10ae
#define mmSCL5_VIEWPORT_START_SECONDARY_BASE_IDX 2
#define mmSCL5_VIEWPORT_START 0x10af
#define mmSCL5_VIEWPORT_START_BASE_IDX 2
#define mmSCL5_VIEWPORT_SIZE 0x10b0
#define mmSCL5_VIEWPORT_SIZE_BASE_IDX 2
#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x10b1
#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x10b2
#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmSCL5_SCL_MODE_CHANGE_DET1 0x10b3
#define mmSCL5_SCL_MODE_CHANGE_DET1_BASE_IDX 2
#define mmSCL5_SCL_MODE_CHANGE_DET2 0x10b4
#define mmSCL5_SCL_MODE_CHANGE_DET2_BASE_IDX 2
#define mmSCL5_SCL_MODE_CHANGE_DET3 0x10b5
#define mmSCL5_SCL_MODE_CHANGE_DET3_BASE_IDX 2
#define mmSCL5_SCL_MODE_CHANGE_MASK 0x10b6
#define mmSCL5_SCL_MODE_CHANGE_MASK_BASE_IDX 2
// addressBlock: dce_dc_blnd5_dispdec
// base address: 0x2800
#define mmBLND5_BLND_CONTROL 0x10c7
#define mmBLND5_BLND_CONTROL_BASE_IDX 2
#define mmBLND5_BLND_SM_CONTROL2 0x10c8
#define mmBLND5_BLND_SM_CONTROL2_BASE_IDX 2
#define mmBLND5_BLND_CONTROL2 0x10c9
#define mmBLND5_BLND_CONTROL2_BASE_IDX 2
#define mmBLND5_BLND_UPDATE 0x10ca
#define mmBLND5_BLND_UPDATE_BASE_IDX 2
#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x10cb
#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
#define mmBLND5_BLND_V_UPDATE_LOCK 0x10cc
#define mmBLND5_BLND_V_UPDATE_LOCK_BASE_IDX 2
#define mmBLND5_BLND_REG_UPDATE_STATUS 0x10cd
#define mmBLND5_BLND_REG_UPDATE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_crtc5_dispdec
// base address: 0x2800
#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x10d2
#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
#define mmCRTC5_CRTC_H_TOTAL 0x10d3
#define mmCRTC5_CRTC_H_TOTAL_BASE_IDX 2
#define mmCRTC5_CRTC_H_BLANK_START_END 0x10d4
#define mmCRTC5_CRTC_H_BLANK_START_END_BASE_IDX 2
#define mmCRTC5_CRTC_H_SYNC_A 0x10d5
#define mmCRTC5_CRTC_H_SYNC_A_BASE_IDX 2
#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x10d6
#define mmCRTC5_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC5_CRTC_H_SYNC_B 0x10d7
#define mmCRTC5_CRTC_H_SYNC_B_BASE_IDX 2
#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x10d8
#define mmCRTC5_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC5_CRTC_VBI_END 0x10d9
#define mmCRTC5_CRTC_VBI_END_BASE_IDX 2
#define mmCRTC5_CRTC_V_TOTAL 0x10da
#define mmCRTC5_CRTC_V_TOTAL_BASE_IDX 2
#define mmCRTC5_CRTC_V_TOTAL_MIN 0x10db
#define mmCRTC5_CRTC_V_TOTAL_MIN_BASE_IDX 2
#define mmCRTC5_CRTC_V_TOTAL_MAX 0x10dc
#define mmCRTC5_CRTC_V_TOTAL_MAX_BASE_IDX 2
#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x10dd
#define mmCRTC5_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x10de
#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x10df
#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmCRTC5_CRTC_V_BLANK_START_END 0x10e0
#define mmCRTC5_CRTC_V_BLANK_START_END_BASE_IDX 2
#define mmCRTC5_CRTC_V_SYNC_A 0x10e1
#define mmCRTC5_CRTC_V_SYNC_A_BASE_IDX 2
#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x10e2
#define mmCRTC5_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTC5_CRTC_V_SYNC_B 0x10e3
#define mmCRTC5_CRTC_V_SYNC_B_BASE_IDX 2
#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x10e4
#define mmCRTC5_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTC5_CRTC_DTMTEST_CNTL 0x10e5
#define mmCRTC5_CRTC_DTMTEST_CNTL_BASE_IDX 2
#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x10e6
#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
#define mmCRTC5_CRTC_TRIGA_CNTL 0x10e7
#define mmCRTC5_CRTC_TRIGA_CNTL_BASE_IDX 2
#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x10e8
#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC5_CRTC_TRIGB_CNTL 0x10e9
#define mmCRTC5_CRTC_TRIGB_CNTL_BASE_IDX 2
#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x10ea
#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x10eb
#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmCRTC5_CRTC_FLOW_CONTROL 0x10ec
#define mmCRTC5_CRTC_FLOW_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x10ed
#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x10ee
#define mmCRTC5_CRTC_AVSYNC_COUNTER_BASE_IDX 2
#define mmCRTC5_CRTC_CONTROL 0x10ef
#define mmCRTC5_CRTC_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_BLANK_CONTROL 0x10f0
#define mmCRTC5_CRTC_BLANK_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x10f1
#define mmCRTC5_CRTC_INTERLACE_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_INTERLACE_STATUS 0x10f2
#define mmCRTC5_CRTC_INTERLACE_STATUS_BASE_IDX 2
#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x10f3
#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x10f4
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x10f5
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmCRTC5_CRTC_STATUS 0x10f6
#define mmCRTC5_CRTC_STATUS_BASE_IDX 2
#define mmCRTC5_CRTC_STATUS_POSITION 0x10f7
#define mmCRTC5_CRTC_STATUS_POSITION_BASE_IDX 2
#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x10f8
#define mmCRTC5_CRTC_NOM_VERT_POSITION_BASE_IDX 2
#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x10f9
#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x10fa
#define mmCRTC5_CRTC_STATUS_VF_COUNT_BASE_IDX 2
#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x10fb
#define mmCRTC5_CRTC_STATUS_HV_COUNT_BASE_IDX 2
#define mmCRTC5_CRTC_COUNT_CONTROL 0x10fc
#define mmCRTC5_CRTC_COUNT_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_COUNT_RESET 0x10fd
#define mmCRTC5_CRTC_COUNT_RESET_BASE_IDX 2
#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x10fe
#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x10ff
#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_STEREO_STATUS 0x1100
#define mmCRTC5_CRTC_STEREO_STATUS_BASE_IDX 2
#define mmCRTC5_CRTC_STEREO_CONTROL 0x1101
#define mmCRTC5_CRTC_STEREO_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x1102
#define mmCRTC5_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x1103
#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x1104
#define mmCRTC5_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x1105
#define mmCRTC5_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
#define mmCRTC5_CRTC_START_LINE_CONTROL 0x1106
#define mmCRTC5_CRTC_START_LINE_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x1107
#define mmCRTC5_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_UPDATE_LOCK 0x1108
#define mmCRTC5_CRTC_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x1109
#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x110a
#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x110b
#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x110c
#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x110d
#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x110e
#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x110f
#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x1110
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1111
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
#define mmCRTC5_CRTC_MVP_STATUS 0x1112
#define mmCRTC5_CRTC_MVP_STATUS_BASE_IDX 2
#define mmCRTC5_CRTC_MASTER_EN 0x1113
#define mmCRTC5_CRTC_MASTER_EN_BASE_IDX 2
#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x1114
#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x1115
#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x1117
#define mmCRTC5_CRTC_OVERSCAN_COLOR_BASE_IDX 2
#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x1118
#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x1119
#define mmCRTC5_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x111a
#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmCRTC5_CRTC_BLACK_COLOR 0x111b
#define mmCRTC5_CRTC_BLACK_COLOR_BASE_IDX 2
#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x111c
#define mmCRTC5_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x111d
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x111e
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x111f
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1120
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1121
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1122
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_CRC_CNTL 0x1123
#define mmCRTC5_CRTC_CRC_CNTL_BASE_IDX 2
#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x1124
#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1125
#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x1126
#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1127
#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_CRC0_DATA_RG 0x1128
#define mmCRTC5_CRTC_CRC0_DATA_RG_BASE_IDX 2
#define mmCRTC5_CRTC_CRC0_DATA_B 0x1129
#define mmCRTC5_CRTC_CRC0_DATA_B_BASE_IDX 2
#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x112a
#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x112b
#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x112c
#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x112d
#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_CRC1_DATA_RG 0x112e
#define mmCRTC5_CRTC_CRC1_DATA_RG_BASE_IDX 2
#define mmCRTC5_CRTC_CRC1_DATA_B 0x112f
#define mmCRTC5_CRTC_CRC1_DATA_B_BASE_IDX 2
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x1130
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1131
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1132
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1133
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1134
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1135
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x1136
#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x1137
#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x1138
#define mmCRTC5_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
#define mmCRTC5_CRTC_GSL_WINDOW 0x1139
#define mmCRTC5_CRTC_GSL_WINDOW_BASE_IDX 2
#define mmCRTC5_CRTC_GSL_CONTROL 0x113a
#define mmCRTC5_CRTC_GSL_CONTROL_BASE_IDX 2
#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS 0x113d
#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmCRTC5_CRTC_DRR_CONTROL 0x113e
#define mmCRTC5_CRTC_DRR_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_fmt5_dispdec
// base address: 0x2800
#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x1142
#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x1143
#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1144
#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1145
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT5_FMT_CONTROL 0x1146
#define mmFMT5_FMT_CONTROL_BASE_IDX 2
#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1147
#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1148
#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1149
#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x114a
#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT5_FMT_CLAMP_CNTL 0x114e
#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT5_FMT_CRC_CNTL 0x114f
#define mmFMT5_FMT_CRC_CNTL_BASE_IDX 2
#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x1150
#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1151
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x1152
#define mmFMT5_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x1153
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1154
#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT5_FMT_420_HBLANK_EARLY_START 0x1155
#define mmFMT5_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
// addressBlock: dce_dc_unp0_dispdec
// base address: 0x0
#define mmUNP0_UNP_GRPH_ENABLE 0x115a
#define mmUNP0_UNP_GRPH_ENABLE_BASE_IDX 2
#define mmUNP0_UNP_GRPH_CONTROL 0x115b
#define mmUNP0_UNP_GRPH_CONTROL_BASE_IDX 2
#define mmUNP0_UNP_GRPH_CONTROL_C 0x115c
#define mmUNP0_UNP_GRPH_CONTROL_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_CONTROL_EXP 0x115d
#define mmUNP0_UNP_GRPH_CONTROL_EXP_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SWAP_CNTL 0x115e
#define mmUNP0_UNP_GRPH_SWAP_CNTL_BASE_IDX 2
#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x115f
#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1160
#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1161
#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1162
#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1163
#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1164
#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1165
#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1166
#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1167
#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1168
#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1169
#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x116a
#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x116b
#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x116c
#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x116d
#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x116e
#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_PITCH_L 0x116f
#define mmUNP0_UNP_GRPH_PITCH_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_PITCH_C 0x1170
#define mmUNP0_UNP_GRPH_PITCH_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L 0x1171
#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C 0x1172
#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1173
#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1174
#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_X_START_L 0x1175
#define mmUNP0_UNP_GRPH_X_START_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_X_START_C 0x1176
#define mmUNP0_UNP_GRPH_X_START_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_Y_START_L 0x1177
#define mmUNP0_UNP_GRPH_Y_START_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_Y_START_C 0x1178
#define mmUNP0_UNP_GRPH_Y_START_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_X_END_L 0x1179
#define mmUNP0_UNP_GRPH_X_END_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_X_END_C 0x117a
#define mmUNP0_UNP_GRPH_X_END_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_Y_END_L 0x117b
#define mmUNP0_UNP_GRPH_Y_END_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_Y_END_C 0x117c
#define mmUNP0_UNP_GRPH_Y_END_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_UPDATE 0x117d
#define mmUNP0_UNP_GRPH_UPDATE_BASE_IDX 2
#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x117e
#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x117f
#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1180
#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1181
#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2
#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1182
#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2
#define mmUNP0_UNP_DVMM_PTE_CONTROL 0x1183
#define mmUNP0_UNP_DVMM_PTE_CONTROL_BASE_IDX 2
#define mmUNP0_UNP_DVMM_PTE_CONTROL_C 0x1184
#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2
#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL 0x1185
#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C 0x1186
#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2
#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS 0x1187
#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2
#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL 0x1188
#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP 0x1189
#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
#define mmUNP0_UNP_FLIP_CONTROL 0x118a
#define mmUNP0_UNP_FLIP_CONTROL_BASE_IDX 2
#define mmUNP0_UNP_CRC_CONTROL 0x118b
#define mmUNP0_UNP_CRC_CONTROL_BASE_IDX 2
#define mmUNP0_UNP_CRC_MASK 0x118c
#define mmUNP0_UNP_CRC_MASK_BASE_IDX 2
#define mmUNP0_UNP_CRC_CURRENT 0x118d
#define mmUNP0_UNP_CRC_CURRENT_BASE_IDX 2
#define mmUNP0_UNP_CRC_LAST 0x118e
#define mmUNP0_UNP_CRC_LAST_BASE_IDX 2
#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x118f
#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
#define mmUNP0_UNP_HW_ROTATION 0x1190
#define mmUNP0_UNP_HW_ROTATION_BASE_IDX 2
// addressBlock: dce_dc_lbv0_dispdec
// base address: 0x0
#define mmLBV0_LBV_DATA_FORMAT 0x1196
#define mmLBV0_LBV_DATA_FORMAT_BASE_IDX 2
#define mmLBV0_LBV_MEMORY_CTRL 0x1197
#define mmLBV0_LBV_MEMORY_CTRL_BASE_IDX 2
#define mmLBV0_LBV_MEMORY_SIZE_STATUS 0x1198
#define mmLBV0_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2
#define mmLBV0_LBV_DESKTOP_HEIGHT 0x1199
#define mmLBV0_LBV_DESKTOP_HEIGHT_BASE_IDX 2
#define mmLBV0_LBV_VLINE_START_END 0x119a
#define mmLBV0_LBV_VLINE_START_END_BASE_IDX 2
#define mmLBV0_LBV_VLINE2_START_END 0x119b
#define mmLBV0_LBV_VLINE2_START_END_BASE_IDX 2
#define mmLBV0_LBV_V_COUNTER 0x119c
#define mmLBV0_LBV_V_COUNTER_BASE_IDX 2
#define mmLBV0_LBV_SNAPSHOT_V_COUNTER 0x119d
#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2
#define mmLBV0_LBV_V_COUNTER_CHROMA 0x119e
#define mmLBV0_LBV_V_COUNTER_CHROMA_BASE_IDX 2
#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x119f
#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2
#define mmLBV0_LBV_INTERRUPT_MASK 0x11a0
#define mmLBV0_LBV_INTERRUPT_MASK_BASE_IDX 2
#define mmLBV0_LBV_VLINE_STATUS 0x11a1
#define mmLBV0_LBV_VLINE_STATUS_BASE_IDX 2
#define mmLBV0_LBV_VLINE2_STATUS 0x11a2
#define mmLBV0_LBV_VLINE2_STATUS_BASE_IDX 2
#define mmLBV0_LBV_VBLANK_STATUS 0x11a3
#define mmLBV0_LBV_VBLANK_STATUS_BASE_IDX 2
#define mmLBV0_LBV_SYNC_RESET_SEL 0x11a4
#define mmLBV0_LBV_SYNC_RESET_SEL_BASE_IDX 2
#define mmLBV0_LBV_BLACK_KEYER_R_CR 0x11a5
#define mmLBV0_LBV_BLACK_KEYER_R_CR_BASE_IDX 2
#define mmLBV0_LBV_BLACK_KEYER_G_Y 0x11a6
#define mmLBV0_LBV_BLACK_KEYER_G_Y_BASE_IDX 2
#define mmLBV0_LBV_BLACK_KEYER_B_CB 0x11a7
#define mmLBV0_LBV_BLACK_KEYER_B_CB_BASE_IDX 2
#define mmLBV0_LBV_KEYER_COLOR_CTRL 0x11a8
#define mmLBV0_LBV_KEYER_COLOR_CTRL_BASE_IDX 2
#define mmLBV0_LBV_KEYER_COLOR_R_CR 0x11a9
#define mmLBV0_LBV_KEYER_COLOR_R_CR_BASE_IDX 2
#define mmLBV0_LBV_KEYER_COLOR_G_Y 0x11aa
#define mmLBV0_LBV_KEYER_COLOR_G_Y_BASE_IDX 2
#define mmLBV0_LBV_KEYER_COLOR_B_CB 0x11ab
#define mmLBV0_LBV_KEYER_COLOR_B_CB_BASE_IDX 2
#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR 0x11ac
#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2
#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y 0x11ad
#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2
#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB 0x11ae
#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2
#define mmLBV0_LBV_BUFFER_LEVEL_STATUS 0x11af
#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2
#define mmLBV0_LBV_BUFFER_URGENCY_CTRL 0x11b0
#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2
#define mmLBV0_LBV_BUFFER_URGENCY_STATUS 0x11b1
#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2
#define mmLBV0_LBV_BUFFER_STATUS 0x11b2
#define mmLBV0_LBV_BUFFER_STATUS_BASE_IDX 2
#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS 0x11b3
#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
// addressBlock: dce_dc_sclv0_dispdec
// base address: 0x0
#define mmSCLV0_SCLV_COEF_RAM_SELECT 0x11ca
#define mmSCLV0_SCLV_COEF_RAM_SELECT_BASE_IDX 2
#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA 0x11cb
#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmSCLV0_SCLV_MODE 0x11cc
#define mmSCLV0_SCLV_MODE_BASE_IDX 2
#define mmSCLV0_SCLV_TAP_CONTROL 0x11cd
#define mmSCLV0_SCLV_TAP_CONTROL_BASE_IDX 2
#define mmSCLV0_SCLV_CONTROL 0x11ce
#define mmSCLV0_SCLV_CONTROL_BASE_IDX 2
#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL 0x11cf
#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL 0x11d0
#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL 0x11d1
#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2
#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO 0x11d2
#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCLV0_SCLV_HORZ_FILTER_INIT 0x11d3
#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BASE_IDX 2
#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x11d4
#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C 0x11d5
#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmSCLV0_SCLV_VERT_FILTER_CONTROL 0x11d6
#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2
#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO 0x11d7
#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCLV0_SCLV_VERT_FILTER_INIT 0x11d8
#define mmSCLV0_SCLV_VERT_FILTER_INIT_BASE_IDX 2
#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT 0x11d9
#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C 0x11da
#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmSCLV0_SCLV_VERT_FILTER_INIT_C 0x11db
#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C 0x11dc
#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmSCLV0_SCLV_ROUND_OFFSET 0x11dd
#define mmSCLV0_SCLV_ROUND_OFFSET_BASE_IDX 2
#define mmSCLV0_SCLV_UPDATE 0x11de
#define mmSCLV0_SCLV_UPDATE_BASE_IDX 2
#define mmSCLV0_SCLV_ALU_CONTROL 0x11df
#define mmSCLV0_SCLV_ALU_CONTROL_BASE_IDX 2
#define mmSCLV0_SCLV_VIEWPORT_START 0x11e0
#define mmSCLV0_SCLV_VIEWPORT_START_BASE_IDX 2
#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY 0x11e1
#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2
#define mmSCLV0_SCLV_VIEWPORT_SIZE 0x11e2
#define mmSCLV0_SCLV_VIEWPORT_SIZE_BASE_IDX 2
#define mmSCLV0_SCLV_VIEWPORT_START_C 0x11e3
#define mmSCLV0_SCLV_VIEWPORT_START_C_BASE_IDX 2
#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C 0x11e4
#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2
#define mmSCLV0_SCLV_VIEWPORT_SIZE_C 0x11e5
#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2
#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x11e6
#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x11e7
#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmSCLV0_SCLV_MODE_CHANGE_DET1 0x11e8
#define mmSCLV0_SCLV_MODE_CHANGE_DET1_BASE_IDX 2
#define mmSCLV0_SCLV_MODE_CHANGE_DET2 0x11e9
#define mmSCLV0_SCLV_MODE_CHANGE_DET2_BASE_IDX 2
#define mmSCLV0_SCLV_MODE_CHANGE_DET3 0x11ea
#define mmSCLV0_SCLV_MODE_CHANGE_DET3_BASE_IDX 2
#define mmSCLV0_SCLV_MODE_CHANGE_MASK 0x11eb
#define mmSCLV0_SCLV_MODE_CHANGE_MASK_BASE_IDX 2
#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT 0x11ec
#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2
#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C 0x11ed
#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2
// addressBlock: dce_dc_col_man0_dispdec
// base address: 0x0
#define mmCOL_MAN0_COL_MAN_UPDATE 0x11fe
#define mmCOL_MAN0_COL_MAN_UPDATE_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL 0x11ff
#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C11_C12_A 0x1200
#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C13_C14_A 0x1201
#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C21_C22_A 0x1202
#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C23_C24_A 0x1203
#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C31_C32_A 0x1204
#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C33_C34_A 0x1205
#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C11_C12_B 0x1206
#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C13_C14_B 0x1207
#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C21_C22_B 0x1208
#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C23_C24_B 0x1209
#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C31_C32_B 0x120a
#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_BASE_IDX 2
#define mmCOL_MAN0_INPUT_CSC_C33_C34_B 0x120b
#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_BASE_IDX 2
#define mmCOL_MAN0_PRESCALE_CONTROL 0x120c
#define mmCOL_MAN0_PRESCALE_CONTROL_BASE_IDX 2
#define mmCOL_MAN0_PRESCALE_VALUES_R 0x120d
#define mmCOL_MAN0_PRESCALE_VALUES_R_BASE_IDX 2
#define mmCOL_MAN0_PRESCALE_VALUES_G 0x120e
#define mmCOL_MAN0_PRESCALE_VALUES_G_BASE_IDX 2
#define mmCOL_MAN0_PRESCALE_VALUES_B 0x120f
#define mmCOL_MAN0_PRESCALE_VALUES_B_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL 0x1210
#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A 0x1211
#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A 0x1212
#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A 0x1213
#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A 0x1214
#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A 0x1215
#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A 0x1216
#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B 0x1217
#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B 0x1218
#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B 0x1219
#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B 0x121a
#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B 0x121b
#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B 0x121c
#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_BASE_IDX 2
#define mmCOL_MAN0_DENORM_CLAMP_CONTROL 0x121d
#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_BASE_IDX 2
#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR 0x121e
#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2
#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y 0x121f
#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2
#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB 0x1220
#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD 0x1221
#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL 0x1222
#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX 0x1223
#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA 0x1224
#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1225
#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1226
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1227
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1228
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1229
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x122a
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x122b
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x122c
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x122d
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x122e
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x122f
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1230
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1231
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1232
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1233
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1234
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1235
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1236
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1237
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1238
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1239
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x123a
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x123b
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x123c
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x123d
#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
#define mmCOL_MAN0_PACK_FIFO_ERROR 0x123e
#define mmCOL_MAN0_PACK_FIFO_ERROR_BASE_IDX 2
#define mmCOL_MAN0_OUTPUT_FIFO_ERROR 0x123f
#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_BASE_IDX 2
#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL 0x1240
#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2
#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX 0x1241
#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2
#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR 0x1242
#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2
#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA 0x1243
#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2
#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR 0x1244
#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 0x1245
#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 0x1246
#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2
#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B 0x1247
#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2
#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G 0x1248
#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2
#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R 0x1249
#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL 0x124a
#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL 0x124b
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12 0x124c
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14 0x124d
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22 0x124e
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24 0x124f
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32 0x1250
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34 0x1251
#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2
// addressBlock: dce_dc_dcfev0_dispdec
// base address: 0x0
#define mmDCFEV0_DCFEV_CLOCK_CONTROL 0x127e
#define mmDCFEV0_DCFEV_CLOCK_CONTROL_BASE_IDX 2
#define mmDCFEV0_DCFEV_SOFT_RESET 0x127f
#define mmDCFEV0_DCFEV_SOFT_RESET_BASE_IDX 2
#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL 0x1280
#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2
#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL 0x1282
#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS 0x1283
#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCFEV0_DCFEV_MEM_PWR_CTRL 0x1284
#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2 0x1285
#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDCFEV0_DCFEV_MEM_PWR_STATUS 0x1286
#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCFEV0_DCFEV_L_FLUSH 0x1287
#define mmDCFEV0_DCFEV_L_FLUSH_BASE_IDX 2
#define mmDCFEV0_DCFEV_C_FLUSH 0x1288
#define mmDCFEV0_DCFEV_C_FLUSH_BASE_IDX 2
#define mmDCFEV0_DCFEV_MISC 0x128a
#define mmDCFEV0_DCFEV_MISC_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon11_dispdec
// base address: 0x49c8
#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x1292
#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x1293
#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x1294
#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CNTL 0x1295
#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CNTL2 0x1296
#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x1297
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x1298
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_HI 0x1299
#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_LOW 0x129a
#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmifv_pg0_dispdec
// base address: 0x0
#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 0x129e
#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 0x129f
#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL 0x12a0
#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL 0x12a1
#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL 0x12a2
#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL 0x12a3
#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12a4
#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x12a5
#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM 0x12a6
#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_BASE_IDX 2
#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL 0x12aa
#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 0x12ab
#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 0x12ac
#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL 0x12ad
#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL 0x12ae
#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL 0x12af
#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL 0x12b0
#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12b1
#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x12b2
#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM 0x12b3
#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_BASE_IDX 2
#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL 0x12b7
#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2
// addressBlock: dce_dc_blndv0_dispdec
// base address: 0x0
#define mmBLNDV0_BLNDV_CONTROL 0x12db
#define mmBLNDV0_BLNDV_CONTROL_BASE_IDX 2
#define mmBLNDV0_BLNDV_SM_CONTROL2 0x12dc
#define mmBLNDV0_BLNDV_SM_CONTROL2_BASE_IDX 2
#define mmBLNDV0_BLNDV_CONTROL2 0x12dd
#define mmBLNDV0_BLNDV_CONTROL2_BASE_IDX 2
#define mmBLNDV0_BLNDV_UPDATE 0x12de
#define mmBLNDV0_BLNDV_UPDATE_BASE_IDX 2
#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT 0x12df
#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2
#define mmBLNDV0_BLNDV_V_UPDATE_LOCK 0x12e0
#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_BASE_IDX 2
#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS 0x12e1
#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_crtcv0_dispdec
// base address: 0x0
#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM 0x12e6
#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2
#define mmCRTCV0_CRTCV_H_TOTAL 0x12e7
#define mmCRTCV0_CRTCV_H_TOTAL_BASE_IDX 2
#define mmCRTCV0_CRTCV_H_BLANK_START_END 0x12e8
#define mmCRTCV0_CRTCV_H_BLANK_START_END_BASE_IDX 2
#define mmCRTCV0_CRTCV_H_SYNC_A 0x12e9
#define mmCRTCV0_CRTCV_H_SYNC_A_BASE_IDX 2
#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL 0x12ea
#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTCV0_CRTCV_H_SYNC_B 0x12eb
#define mmCRTCV0_CRTCV_H_SYNC_B_BASE_IDX 2
#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL 0x12ec
#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTCV0_CRTCV_VBI_END 0x12ed
#define mmCRTCV0_CRTCV_VBI_END_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_TOTAL 0x12ee
#define mmCRTCV0_CRTCV_V_TOTAL_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_TOTAL_MIN 0x12ef
#define mmCRTCV0_CRTCV_V_TOTAL_MIN_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_TOTAL_MAX 0x12f0
#define mmCRTCV0_CRTCV_V_TOTAL_MAX_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL 0x12f1
#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS 0x12f2
#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS 0x12f3
#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_BLANK_START_END 0x12f4
#define mmCRTCV0_CRTCV_V_BLANK_START_END_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_SYNC_A 0x12f5
#define mmCRTCV0_CRTCV_V_SYNC_A_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL 0x12f6
#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_SYNC_B 0x12f7
#define mmCRTCV0_CRTCV_V_SYNC_B_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL 0x12f8
#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTCV0_CRTCV_DTMTEST_CNTL 0x12f9
#define mmCRTCV0_CRTCV_DTMTEST_CNTL_BASE_IDX 2
#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION 0x12fa
#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2
#define mmCRTCV0_CRTCV_TRIGA_CNTL 0x12fb
#define mmCRTCV0_CRTCV_TRIGA_CNTL_BASE_IDX 2
#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG 0x12fc
#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmCRTCV0_CRTCV_TRIGB_CNTL 0x12fd
#define mmCRTCV0_CRTCV_TRIGB_CNTL_BASE_IDX 2
#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG 0x12fe
#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL 0x12ff
#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmCRTCV0_CRTCV_FLOW_CONTROL 0x1300
#define mmCRTCV0_CRTCV_FLOW_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE 0x1301
#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmCRTCV0_CRTCV_AVSYNC_COUNTER 0x1302
#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_BASE_IDX 2
#define mmCRTCV0_CRTCV_CONTROL 0x1303
#define mmCRTCV0_CRTCV_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_BLANK_CONTROL 0x1304
#define mmCRTCV0_CRTCV_BLANK_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_INTERLACE_CONTROL 0x1305
#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_INTERLACE_STATUS 0x1306
#define mmCRTCV0_CRTCV_INTERLACE_STATUS_BASE_IDX 2
#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL 0x1307
#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0 0x1308
#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1 0x1309
#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmCRTCV0_CRTCV_STATUS 0x130a
#define mmCRTCV0_CRTCV_STATUS_BASE_IDX 2
#define mmCRTCV0_CRTCV_STATUS_POSITION 0x130b
#define mmCRTCV0_CRTCV_STATUS_POSITION_BASE_IDX 2
#define mmCRTCV0_CRTCV_NOM_VERT_POSITION 0x130c
#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_BASE_IDX 2
#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT 0x130d
#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmCRTCV0_CRTCV_STATUS_VF_COUNT 0x130e
#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_BASE_IDX 2
#define mmCRTCV0_CRTCV_STATUS_HV_COUNT 0x130f
#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_BASE_IDX 2
#define mmCRTCV0_CRTCV_COUNT_CONTROL 0x1310
#define mmCRTCV0_CRTCV_COUNT_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_COUNT_RESET 0x1311
#define mmCRTCV0_CRTCV_COUNT_RESET_BASE_IDX 2
#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1312
#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL 0x1313
#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_STEREO_STATUS 0x1314
#define mmCRTCV0_CRTCV_STEREO_STATUS_BASE_IDX 2
#define mmCRTCV0_CRTCV_STEREO_CONTROL 0x1315
#define mmCRTCV0_CRTCV_STEREO_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS 0x1316
#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2
#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL 0x1317
#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION 0x1318
#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2
#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME 0x1319
#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2
#define mmCRTCV0_CRTCV_START_LINE_CONTROL 0x131a
#define mmCRTCV0_CRTCV_START_LINE_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL 0x131b
#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_UPDATE_LOCK 0x131c
#define mmCRTCV0_CRTCV_UPDATE_LOCK_BASE_IDX 2
#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL 0x131d
#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x131e
#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL 0x131f
#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS 0x1320
#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR 0x1321
#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK 0x1322
#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE 0x1323
#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT 0x1324
#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1325
#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
#define mmCRTCV0_CRTCV_MVP_STATUS 0x1326
#define mmCRTCV0_CRTCV_MVP_STATUS_BASE_IDX 2
#define mmCRTCV0_CRTCV_MASTER_EN 0x1327
#define mmCRTCV0_CRTCV_MASTER_EN_BASE_IDX 2
#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1328
#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS 0x1329
#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2
#define mmCRTCV0_CRTCV_OVERSCAN_COLOR 0x132b
#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_BASE_IDX 2
#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT 0x132c
#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2
#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR 0x132d
#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2
#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT 0x132e
#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmCRTCV0_CRTCV_BLACK_COLOR 0x132f
#define mmCRTCV0_CRTCV_BLACK_COLOR_BASE_IDX 2
#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT 0x1330
#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1331
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1332
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1333
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1334
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1335
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1336
#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC_CNTL 0x1337
#define mmCRTCV0_CRTCV_CRC_CNTL_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1338
#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1339
#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL 0x133a
#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x133b
#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC0_DATA_RG 0x133c
#define mmCRTCV0_CRTCV_CRC0_DATA_RG_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC0_DATA_B 0x133d
#define mmCRTCV0_CRTCV_CRC0_DATA_B_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL 0x133e
#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x133f
#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1340
#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1341
#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC1_DATA_RG 0x1342
#define mmCRTCV0_CRTCV_CRC1_DATA_RG_BASE_IDX 2
#define mmCRTCV0_CRTCV_CRC1_DATA_B 0x1343
#define mmCRTCV0_CRTCV_CRC1_DATA_B_BASE_IDX 2
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1344
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1345
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1346
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1347
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1348
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1349
#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL 0x134a
#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL 0x134b
#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP 0x134c
#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2
#define mmCRTCV0_CRTCV_GSL_WINDOW 0x134d
#define mmCRTCV0_CRTCV_GSL_WINDOW_BASE_IDX 2
#define mmCRTCV0_CRTCV_GSL_CONTROL 0x134e
#define mmCRTCV0_CRTCV_GSL_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_unp1_dispdec
// base address: 0x800
#define mmUNP1_UNP_GRPH_ENABLE 0x135a
#define mmUNP1_UNP_GRPH_ENABLE_BASE_IDX 2
#define mmUNP1_UNP_GRPH_CONTROL 0x135b
#define mmUNP1_UNP_GRPH_CONTROL_BASE_IDX 2
#define mmUNP1_UNP_GRPH_CONTROL_C 0x135c
#define mmUNP1_UNP_GRPH_CONTROL_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_CONTROL_EXP 0x135d
#define mmUNP1_UNP_GRPH_CONTROL_EXP_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SWAP_CNTL 0x135e
#define mmUNP1_UNP_GRPH_SWAP_CNTL_BASE_IDX 2
#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x135f
#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1360
#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1361
#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1362
#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1363
#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1364
#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1365
#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1366
#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1367
#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1368
#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1369
#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x136a
#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x136b
#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x136c
#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x136d
#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x136e
#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_PITCH_L 0x136f
#define mmUNP1_UNP_GRPH_PITCH_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_PITCH_C 0x1370
#define mmUNP1_UNP_GRPH_PITCH_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L 0x1371
#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C 0x1372
#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1373
#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1374
#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_X_START_L 0x1375
#define mmUNP1_UNP_GRPH_X_START_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_X_START_C 0x1376
#define mmUNP1_UNP_GRPH_X_START_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_Y_START_L 0x1377
#define mmUNP1_UNP_GRPH_Y_START_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_Y_START_C 0x1378
#define mmUNP1_UNP_GRPH_Y_START_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_X_END_L 0x1379
#define mmUNP1_UNP_GRPH_X_END_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_X_END_C 0x137a
#define mmUNP1_UNP_GRPH_X_END_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_Y_END_L 0x137b
#define mmUNP1_UNP_GRPH_Y_END_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_Y_END_C 0x137c
#define mmUNP1_UNP_GRPH_Y_END_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_UPDATE 0x137d
#define mmUNP1_UNP_GRPH_UPDATE_BASE_IDX 2
#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x137e
#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x137f
#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1380
#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1381
#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2
#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1382
#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2
#define mmUNP1_UNP_DVMM_PTE_CONTROL 0x1383
#define mmUNP1_UNP_DVMM_PTE_CONTROL_BASE_IDX 2
#define mmUNP1_UNP_DVMM_PTE_CONTROL_C 0x1384
#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2
#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL 0x1385
#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C 0x1386
#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2
#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS 0x1387
#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2
#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL 0x1388
#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP 0x1389
#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
#define mmUNP1_UNP_FLIP_CONTROL 0x138a
#define mmUNP1_UNP_FLIP_CONTROL_BASE_IDX 2
#define mmUNP1_UNP_CRC_CONTROL 0x138b
#define mmUNP1_UNP_CRC_CONTROL_BASE_IDX 2
#define mmUNP1_UNP_CRC_MASK 0x138c
#define mmUNP1_UNP_CRC_MASK_BASE_IDX 2
#define mmUNP1_UNP_CRC_CURRENT 0x138d
#define mmUNP1_UNP_CRC_CURRENT_BASE_IDX 2
#define mmUNP1_UNP_CRC_LAST 0x138e
#define mmUNP1_UNP_CRC_LAST_BASE_IDX 2
#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x138f
#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
#define mmUNP1_UNP_HW_ROTATION 0x1390
#define mmUNP1_UNP_HW_ROTATION_BASE_IDX 2
// addressBlock: dce_dc_lbv1_dispdec
// base address: 0x800
#define mmLBV1_LBV_DATA_FORMAT 0x1396
#define mmLBV1_LBV_DATA_FORMAT_BASE_IDX 2
#define mmLBV1_LBV_MEMORY_CTRL 0x1397
#define mmLBV1_LBV_MEMORY_CTRL_BASE_IDX 2
#define mmLBV1_LBV_MEMORY_SIZE_STATUS 0x1398
#define mmLBV1_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2
#define mmLBV1_LBV_DESKTOP_HEIGHT 0x1399
#define mmLBV1_LBV_DESKTOP_HEIGHT_BASE_IDX 2
#define mmLBV1_LBV_VLINE_START_END 0x139a
#define mmLBV1_LBV_VLINE_START_END_BASE_IDX 2
#define mmLBV1_LBV_VLINE2_START_END 0x139b
#define mmLBV1_LBV_VLINE2_START_END_BASE_IDX 2
#define mmLBV1_LBV_V_COUNTER 0x139c
#define mmLBV1_LBV_V_COUNTER_BASE_IDX 2
#define mmLBV1_LBV_SNAPSHOT_V_COUNTER 0x139d
#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2
#define mmLBV1_LBV_V_COUNTER_CHROMA 0x139e
#define mmLBV1_LBV_V_COUNTER_CHROMA_BASE_IDX 2
#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x139f
#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2
#define mmLBV1_LBV_INTERRUPT_MASK 0x13a0
#define mmLBV1_LBV_INTERRUPT_MASK_BASE_IDX 2
#define mmLBV1_LBV_VLINE_STATUS 0x13a1
#define mmLBV1_LBV_VLINE_STATUS_BASE_IDX 2
#define mmLBV1_LBV_VLINE2_STATUS 0x13a2
#define mmLBV1_LBV_VLINE2_STATUS_BASE_IDX 2
#define mmLBV1_LBV_VBLANK_STATUS 0x13a3
#define mmLBV1_LBV_VBLANK_STATUS_BASE_IDX 2
#define mmLBV1_LBV_SYNC_RESET_SEL 0x13a4
#define mmLBV1_LBV_SYNC_RESET_SEL_BASE_IDX 2
#define mmLBV1_LBV_BLACK_KEYER_R_CR 0x13a5
#define mmLBV1_LBV_BLACK_KEYER_R_CR_BASE_IDX 2
#define mmLBV1_LBV_BLACK_KEYER_G_Y 0x13a6
#define mmLBV1_LBV_BLACK_KEYER_G_Y_BASE_IDX 2
#define mmLBV1_LBV_BLACK_KEYER_B_CB 0x13a7
#define mmLBV1_LBV_BLACK_KEYER_B_CB_BASE_IDX 2
#define mmLBV1_LBV_KEYER_COLOR_CTRL 0x13a8
#define mmLBV1_LBV_KEYER_COLOR_CTRL_BASE_IDX 2
#define mmLBV1_LBV_KEYER_COLOR_R_CR 0x13a9
#define mmLBV1_LBV_KEYER_COLOR_R_CR_BASE_IDX 2
#define mmLBV1_LBV_KEYER_COLOR_G_Y 0x13aa
#define mmLBV1_LBV_KEYER_COLOR_G_Y_BASE_IDX 2
#define mmLBV1_LBV_KEYER_COLOR_B_CB 0x13ab
#define mmLBV1_LBV_KEYER_COLOR_B_CB_BASE_IDX 2
#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR 0x13ac
#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2
#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y 0x13ad
#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2
#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB 0x13ae
#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2
#define mmLBV1_LBV_BUFFER_LEVEL_STATUS 0x13af
#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2
#define mmLBV1_LBV_BUFFER_URGENCY_CTRL 0x13b0
#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2
#define mmLBV1_LBV_BUFFER_URGENCY_STATUS 0x13b1
#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2
#define mmLBV1_LBV_BUFFER_STATUS 0x13b2
#define mmLBV1_LBV_BUFFER_STATUS_BASE_IDX 2
#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS 0x13b3
#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
// addressBlock: dce_dc_sclv1_dispdec
// base address: 0x800
#define mmSCLV1_SCLV_COEF_RAM_SELECT 0x13ca
#define mmSCLV1_SCLV_COEF_RAM_SELECT_BASE_IDX 2
#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA 0x13cb
#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmSCLV1_SCLV_MODE 0x13cc
#define mmSCLV1_SCLV_MODE_BASE_IDX 2
#define mmSCLV1_SCLV_TAP_CONTROL 0x13cd
#define mmSCLV1_SCLV_TAP_CONTROL_BASE_IDX 2
#define mmSCLV1_SCLV_CONTROL 0x13ce
#define mmSCLV1_SCLV_CONTROL_BASE_IDX 2
#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL 0x13cf
#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL 0x13d0
#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL 0x13d1
#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2
#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO 0x13d2
#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCLV1_SCLV_HORZ_FILTER_INIT 0x13d3
#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BASE_IDX 2
#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x13d4
#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C 0x13d5
#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmSCLV1_SCLV_VERT_FILTER_CONTROL 0x13d6
#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2
#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO 0x13d7
#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmSCLV1_SCLV_VERT_FILTER_INIT 0x13d8
#define mmSCLV1_SCLV_VERT_FILTER_INIT_BASE_IDX 2
#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT 0x13d9
#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C 0x13da
#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmSCLV1_SCLV_VERT_FILTER_INIT_C 0x13db
#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C 0x13dc
#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmSCLV1_SCLV_ROUND_OFFSET 0x13dd
#define mmSCLV1_SCLV_ROUND_OFFSET_BASE_IDX 2
#define mmSCLV1_SCLV_UPDATE 0x13de
#define mmSCLV1_SCLV_UPDATE_BASE_IDX 2
#define mmSCLV1_SCLV_ALU_CONTROL 0x13df
#define mmSCLV1_SCLV_ALU_CONTROL_BASE_IDX 2
#define mmSCLV1_SCLV_VIEWPORT_START 0x13e0
#define mmSCLV1_SCLV_VIEWPORT_START_BASE_IDX 2
#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY 0x13e1
#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2
#define mmSCLV1_SCLV_VIEWPORT_SIZE 0x13e2
#define mmSCLV1_SCLV_VIEWPORT_SIZE_BASE_IDX 2
#define mmSCLV1_SCLV_VIEWPORT_START_C 0x13e3
#define mmSCLV1_SCLV_VIEWPORT_START_C_BASE_IDX 2
#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C 0x13e4
#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2
#define mmSCLV1_SCLV_VIEWPORT_SIZE_C 0x13e5
#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2
#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x13e6
#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x13e7
#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmSCLV1_SCLV_MODE_CHANGE_DET1 0x13e8
#define mmSCLV1_SCLV_MODE_CHANGE_DET1_BASE_IDX 2
#define mmSCLV1_SCLV_MODE_CHANGE_DET2 0x13e9
#define mmSCLV1_SCLV_MODE_CHANGE_DET2_BASE_IDX 2
#define mmSCLV1_SCLV_MODE_CHANGE_DET3 0x13ea
#define mmSCLV1_SCLV_MODE_CHANGE_DET3_BASE_IDX 2
#define mmSCLV1_SCLV_MODE_CHANGE_MASK 0x13eb
#define mmSCLV1_SCLV_MODE_CHANGE_MASK_BASE_IDX 2
#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT 0x13ec
#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2
#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C 0x13ed
#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2
// addressBlock: dce_dc_col_man1_dispdec
// base address: 0x800
#define mmCOL_MAN1_COL_MAN_UPDATE 0x13fe
#define mmCOL_MAN1_COL_MAN_UPDATE_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL 0x13ff
#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C11_C12_A 0x1400
#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C13_C14_A 0x1401
#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C21_C22_A 0x1402
#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C23_C24_A 0x1403
#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C31_C32_A 0x1404
#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C33_C34_A 0x1405
#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C11_C12_B 0x1406
#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C13_C14_B 0x1407
#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C21_C22_B 0x1408
#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C23_C24_B 0x1409
#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C31_C32_B 0x140a
#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_BASE_IDX 2
#define mmCOL_MAN1_INPUT_CSC_C33_C34_B 0x140b
#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_BASE_IDX 2
#define mmCOL_MAN1_PRESCALE_CONTROL 0x140c
#define mmCOL_MAN1_PRESCALE_CONTROL_BASE_IDX 2
#define mmCOL_MAN1_PRESCALE_VALUES_R 0x140d
#define mmCOL_MAN1_PRESCALE_VALUES_R_BASE_IDX 2
#define mmCOL_MAN1_PRESCALE_VALUES_G 0x140e
#define mmCOL_MAN1_PRESCALE_VALUES_G_BASE_IDX 2
#define mmCOL_MAN1_PRESCALE_VALUES_B 0x140f
#define mmCOL_MAN1_PRESCALE_VALUES_B_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL 0x1410
#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A 0x1411
#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A 0x1412
#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A 0x1413
#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A 0x1414
#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A 0x1415
#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A 0x1416
#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B 0x1417
#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B 0x1418
#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B 0x1419
#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B 0x141a
#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B 0x141b
#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B 0x141c
#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_BASE_IDX 2
#define mmCOL_MAN1_DENORM_CLAMP_CONTROL 0x141d
#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_BASE_IDX 2
#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR 0x141e
#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2
#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y 0x141f
#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2
#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB 0x1420
#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD 0x1421
#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL 0x1422
#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX 0x1423
#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA 0x1424
#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1425
#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1426
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1427
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1428
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1429
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x142a
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x142b
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x142c
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x142d
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x142e
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x142f
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1430
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1431
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1432
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1433
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1434
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1435
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1436
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1437
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1438
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1439
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x143a
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x143b
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x143c
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x143d
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
#define mmCOL_MAN1_PACK_FIFO_ERROR 0x143e
#define mmCOL_MAN1_PACK_FIFO_ERROR_BASE_IDX 2
#define mmCOL_MAN1_OUTPUT_FIFO_ERROR 0x143f
#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_BASE_IDX 2
#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL 0x1440
#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2
#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX 0x1441
#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2
#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR 0x1442
#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2
#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA 0x1443
#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2
#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR 0x1444
#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 0x1445
#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 0x1446
#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2
#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B 0x1447
#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2
#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G 0x1448
#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2
#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R 0x1449
#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL 0x144a
#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL 0x144b
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12 0x144c
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14 0x144d
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22 0x144e
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24 0x144f
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32 0x1450
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34 0x1451
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2
// addressBlock: dce_dc_dcfev1_dispdec
// base address: 0x800
#define mmDCFEV1_DCFEV_CLOCK_CONTROL 0x147e
#define mmDCFEV1_DCFEV_CLOCK_CONTROL_BASE_IDX 2
#define mmDCFEV1_DCFEV_SOFT_RESET 0x147f
#define mmDCFEV1_DCFEV_SOFT_RESET_BASE_IDX 2
#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL 0x1480
#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2
#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL 0x1482
#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS 0x1483
#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCFEV1_DCFEV_MEM_PWR_CTRL 0x1484
#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2 0x1485
#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDCFEV1_DCFEV_MEM_PWR_STATUS 0x1486
#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCFEV1_DCFEV_L_FLUSH 0x1487
#define mmDCFEV1_DCFEV_L_FLUSH_BASE_IDX 2
#define mmDCFEV1_DCFEV_C_FLUSH 0x1488
#define mmDCFEV1_DCFEV_C_FLUSH_BASE_IDX 2
#define mmDCFEV1_DCFEV_MISC 0x148a
#define mmDCFEV1_DCFEV_MISC_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon12_dispdec
// base address: 0x51c8
#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x1492
#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x1493
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x1494
#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CNTL 0x1495
#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CNTL2 0x1496
#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x1497
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x1498
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_HI 0x1499
#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_LOW 0x149a
#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmifv_pg1_dispdec
// base address: 0x800
#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 0x149e
#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 0x149f
#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL 0x14a0
#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL 0x14a1
#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL 0x14a2
#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL 0x14a3
#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14a4
#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x14a5
#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM 0x14a6
#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_BASE_IDX 2
#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL 0x14aa
#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 0x14ab
#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 0x14ac
#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL 0x14ad
#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL 0x14ae
#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL 0x14af
#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL 0x14b0
#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14b1
#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x14b2
#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM 0x14b3
#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_BASE_IDX 2
#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL 0x14b7
#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2
// addressBlock: dce_dc_blndv1_dispdec
// base address: 0x800
#define mmBLNDV1_BLNDV_CONTROL 0x14db
#define mmBLNDV1_BLNDV_CONTROL_BASE_IDX 2
#define mmBLNDV1_BLNDV_SM_CONTROL2 0x14dc
#define mmBLNDV1_BLNDV_SM_CONTROL2_BASE_IDX 2
#define mmBLNDV1_BLNDV_CONTROL2 0x14dd
#define mmBLNDV1_BLNDV_CONTROL2_BASE_IDX 2
#define mmBLNDV1_BLNDV_UPDATE 0x14de
#define mmBLNDV1_BLNDV_UPDATE_BASE_IDX 2
#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT 0x14df
#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2
#define mmBLNDV1_BLNDV_V_UPDATE_LOCK 0x14e0
#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_BASE_IDX 2
#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS 0x14e1
#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_crtcv1_dispdec
// base address: 0x800
#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM 0x14e6
#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2
#define mmCRTCV1_CRTCV_H_TOTAL 0x14e7
#define mmCRTCV1_CRTCV_H_TOTAL_BASE_IDX 2
#define mmCRTCV1_CRTCV_H_BLANK_START_END 0x14e8
#define mmCRTCV1_CRTCV_H_BLANK_START_END_BASE_IDX 2
#define mmCRTCV1_CRTCV_H_SYNC_A 0x14e9
#define mmCRTCV1_CRTCV_H_SYNC_A_BASE_IDX 2
#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL 0x14ea
#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTCV1_CRTCV_H_SYNC_B 0x14eb
#define mmCRTCV1_CRTCV_H_SYNC_B_BASE_IDX 2
#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL 0x14ec
#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTCV1_CRTCV_VBI_END 0x14ed
#define mmCRTCV1_CRTCV_VBI_END_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_TOTAL 0x14ee
#define mmCRTCV1_CRTCV_V_TOTAL_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_TOTAL_MIN 0x14ef
#define mmCRTCV1_CRTCV_V_TOTAL_MIN_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_TOTAL_MAX 0x14f0
#define mmCRTCV1_CRTCV_V_TOTAL_MAX_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL 0x14f1
#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS 0x14f2
#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS 0x14f3
#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_BLANK_START_END 0x14f4
#define mmCRTCV1_CRTCV_V_BLANK_START_END_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_SYNC_A 0x14f5
#define mmCRTCV1_CRTCV_V_SYNC_A_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL 0x14f6
#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_SYNC_B 0x14f7
#define mmCRTCV1_CRTCV_V_SYNC_B_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL 0x14f8
#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2
#define mmCRTCV1_CRTCV_DTMTEST_CNTL 0x14f9
#define mmCRTCV1_CRTCV_DTMTEST_CNTL_BASE_IDX 2
#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION 0x14fa
#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2
#define mmCRTCV1_CRTCV_TRIGA_CNTL 0x14fb
#define mmCRTCV1_CRTCV_TRIGA_CNTL_BASE_IDX 2
#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG 0x14fc
#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmCRTCV1_CRTCV_TRIGB_CNTL 0x14fd
#define mmCRTCV1_CRTCV_TRIGB_CNTL_BASE_IDX 2
#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG 0x14fe
#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL 0x14ff
#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmCRTCV1_CRTCV_FLOW_CONTROL 0x1500
#define mmCRTCV1_CRTCV_FLOW_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE 0x1501
#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmCRTCV1_CRTCV_AVSYNC_COUNTER 0x1502
#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_BASE_IDX 2
#define mmCRTCV1_CRTCV_CONTROL 0x1503
#define mmCRTCV1_CRTCV_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_BLANK_CONTROL 0x1504
#define mmCRTCV1_CRTCV_BLANK_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_INTERLACE_CONTROL 0x1505
#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_INTERLACE_STATUS 0x1506
#define mmCRTCV1_CRTCV_INTERLACE_STATUS_BASE_IDX 2
#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL 0x1507
#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0 0x1508
#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1 0x1509
#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmCRTCV1_CRTCV_STATUS 0x150a
#define mmCRTCV1_CRTCV_STATUS_BASE_IDX 2
#define mmCRTCV1_CRTCV_STATUS_POSITION 0x150b
#define mmCRTCV1_CRTCV_STATUS_POSITION_BASE_IDX 2
#define mmCRTCV1_CRTCV_NOM_VERT_POSITION 0x150c
#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_BASE_IDX 2
#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT 0x150d
#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmCRTCV1_CRTCV_STATUS_VF_COUNT 0x150e
#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_BASE_IDX 2
#define mmCRTCV1_CRTCV_STATUS_HV_COUNT 0x150f
#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_BASE_IDX 2
#define mmCRTCV1_CRTCV_COUNT_CONTROL 0x1510
#define mmCRTCV1_CRTCV_COUNT_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_COUNT_RESET 0x1511
#define mmCRTCV1_CRTCV_COUNT_RESET_BASE_IDX 2
#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1512
#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL 0x1513
#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_STEREO_STATUS 0x1514
#define mmCRTCV1_CRTCV_STEREO_STATUS_BASE_IDX 2
#define mmCRTCV1_CRTCV_STEREO_CONTROL 0x1515
#define mmCRTCV1_CRTCV_STEREO_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS 0x1516
#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2
#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL 0x1517
#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION 0x1518
#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2
#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME 0x1519
#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2
#define mmCRTCV1_CRTCV_START_LINE_CONTROL 0x151a
#define mmCRTCV1_CRTCV_START_LINE_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL 0x151b
#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_UPDATE_LOCK 0x151c
#define mmCRTCV1_CRTCV_UPDATE_LOCK_BASE_IDX 2
#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL 0x151d
#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x151e
#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL 0x151f
#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS 0x1520
#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR 0x1521
#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK 0x1522
#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE 0x1523
#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT 0x1524
#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1525
#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
#define mmCRTCV1_CRTCV_MVP_STATUS 0x1526
#define mmCRTCV1_CRTCV_MVP_STATUS_BASE_IDX 2
#define mmCRTCV1_CRTCV_MASTER_EN 0x1527
#define mmCRTCV1_CRTCV_MASTER_EN_BASE_IDX 2
#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1528
#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS 0x1529
#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2
#define mmCRTCV1_CRTCV_OVERSCAN_COLOR 0x152b
#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_BASE_IDX 2
#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT 0x152c
#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2
#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR 0x152d
#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2
#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT 0x152e
#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmCRTCV1_CRTCV_BLACK_COLOR 0x152f
#define mmCRTCV1_CRTCV_BLACK_COLOR_BASE_IDX 2
#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT 0x1530
#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1531
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1532
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1533
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1534
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1535
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1536
#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC_CNTL 0x1537
#define mmCRTCV1_CRTCV_CRC_CNTL_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1538
#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1539
#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL 0x153a
#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x153b
#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC0_DATA_RG 0x153c
#define mmCRTCV1_CRTCV_CRC0_DATA_RG_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC0_DATA_B 0x153d
#define mmCRTCV1_CRTCV_CRC0_DATA_B_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL 0x153e
#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x153f
#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1540
#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1541
#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC1_DATA_RG 0x1542
#define mmCRTCV1_CRTCV_CRC1_DATA_RG_BASE_IDX 2
#define mmCRTCV1_CRTCV_CRC1_DATA_B 0x1543
#define mmCRTCV1_CRTCV_CRC1_DATA_B_BASE_IDX 2
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1544
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1545
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1546
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1547
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1548
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1549
#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL 0x154a
#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL 0x154b
#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP 0x154c
#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2
#define mmCRTCV1_CRTCV_GSL_WINDOW 0x154d
#define mmCRTCV1_CRTCV_GSL_WINDOW_BASE_IDX 2
#define mmCRTCV1_CRTCV_GSL_CONTROL 0x154e
#define mmCRTCV1_CRTCV_GSL_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_hpd0_dispdec
// base address: 0x0
#define mmHPD0_DC_HPD_INT_STATUS 0x1600
#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD0_DC_HPD_INT_CONTROL 0x1601
#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD0_DC_HPD_CONTROL 0x1602
#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1603
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1604
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_hpd1_dispdec
// base address: 0x20
#define mmHPD1_DC_HPD_INT_STATUS 0x1608
#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD1_DC_HPD_INT_CONTROL 0x1609
#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD1_DC_HPD_CONTROL 0x160a
#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x160b
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x160c
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_hpd2_dispdec
// base address: 0x40
#define mmHPD2_DC_HPD_INT_STATUS 0x1610
#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD2_DC_HPD_INT_CONTROL 0x1611
#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD2_DC_HPD_CONTROL 0x1612
#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1613
#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1614
#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_hpd3_dispdec
// base address: 0x60
#define mmHPD3_DC_HPD_INT_STATUS 0x1618
#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD3_DC_HPD_INT_CONTROL 0x1619
#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD3_DC_HPD_CONTROL 0x161a
#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x161b
#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x161c
#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_hpd4_dispdec
// base address: 0x80
#define mmHPD4_DC_HPD_INT_STATUS 0x1620
#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD4_DC_HPD_INT_CONTROL 0x1621
#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD4_DC_HPD_CONTROL 0x1622
#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1623
#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1624
#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_hpd5_dispdec
// base address: 0xa0
#define mmHPD5_DC_HPD_INT_STATUS 0x1628
#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD5_DC_HPD_INT_CONTROL 0x1629
#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD5_DC_HPD_CONTROL 0x162a
#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x162b
#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x162c
#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon2_dispdec
// base address: 0x5840
#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1630
#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x1631
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1632
#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CNTL 0x1633
#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CNTL2 0x1634
#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1635
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1636
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_HI 0x1637
#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_LOW 0x1638
#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dp_aux0_dispdec
// base address: 0x0
#define mmDP_AUX0_AUX_CONTROL 0x1766
#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_CONTROL 0x1767
#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_ARB_CONTROL 0x1768
#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1769
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_STATUS 0x176a
#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_LS_STATUS 0x176b
#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_DATA 0x176c
#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX0_AUX_LS_DATA 0x176d
#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x176e
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x176f
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1770
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1771
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1772
#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1773
#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1775
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1776
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1777
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dp_aux1_dispdec
// base address: 0x70
#define mmDP_AUX1_AUX_CONTROL 0x1782
#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_CONTROL 0x1783
#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_ARB_CONTROL 0x1784
#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1785
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_STATUS 0x1786
#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_LS_STATUS 0x1787
#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_DATA 0x1788
#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX1_AUX_LS_DATA 0x1789
#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x178a
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x178b
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x178c
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x178d
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x178e
#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x178f
#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1791
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1792
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1793
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dp_aux2_dispdec
// base address: 0xe0
#define mmDP_AUX2_AUX_CONTROL 0x179e
#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_SW_CONTROL 0x179f
#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_ARB_CONTROL 0x17a0
#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x17a1
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_SW_STATUS 0x17a2
#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_LS_STATUS 0x17a3
#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_SW_DATA 0x17a4
#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX2_AUX_LS_DATA 0x17a5
#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x17a6
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x17a7
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x17a8
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x17a9
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x17aa
#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x17ab
#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x17ad
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ae
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x17af
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dp_aux3_dispdec
// base address: 0x150
#define mmDP_AUX3_AUX_CONTROL 0x17ba
#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_SW_CONTROL 0x17bb
#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_ARB_CONTROL 0x17bc
#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x17bd
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_SW_STATUS 0x17be
#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_LS_STATUS 0x17bf
#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_SW_DATA 0x17c0
#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX3_AUX_LS_DATA 0x17c1
#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x17c2
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x17c3
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x17c4
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x17c5
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x17c6
#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x17c7
#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x17c9
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ca
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x17cb
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dp_aux4_dispdec
// base address: 0x1c0
#define mmDP_AUX4_AUX_CONTROL 0x17d6
#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_SW_CONTROL 0x17d7
#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_ARB_CONTROL 0x17d8
#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x17d9
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_SW_STATUS 0x17da
#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_LS_STATUS 0x17db
#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_SW_DATA 0x17dc
#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX4_AUX_LS_DATA 0x17dd
#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x17de
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x17df
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x17e0
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x17e1
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x17e2
#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x17e3
#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x17e5
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17e6
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x17e7
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dp_aux5_dispdec
// base address: 0x230
#define mmDP_AUX5_AUX_CONTROL 0x17f2
#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_SW_CONTROL 0x17f3
#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_ARB_CONTROL 0x17f4
#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x17f5
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_SW_STATUS 0x17f6
#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX5_AUX_LS_STATUS 0x17f7
#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX5_AUX_SW_DATA 0x17f8
#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX5_AUX_LS_DATA 0x17f9
#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x17fa
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x17fb
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x17fc
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x17fd
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x17fe
#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x17ff
#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1801
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1802
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1803
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dig0_dispdec
// base address: 0x0
#define mmDIG0_DIG_FE_CNTL 0x187e
#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x187f
#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1880
#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG0_DIG_CLOCK_PATTERN 0x1881
#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG0_DIG_TEST_PATTERN 0x1882
#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1883
#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG0_DIG_FIFO_STATUS 0x1884
#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_CONTROL 0x1887
#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_STATUS 0x1888
#define mmDIG0_HDMI_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1889
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x188a
#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x188b
#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x188c
#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x188d
#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x188e
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG0_AFMT_INTERRUPT_STATUS 0x188f
#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_GC 0x1891
#define mmDIG0_HDMI_GC_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1892
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_0 0x1893
#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_1 0x1894
#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_2 0x1895
#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_3 0x1896
#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_4 0x1897
#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_0 0x1898
#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_1 0x1899
#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_2 0x189a
#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_3 0x189b
#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG0_AFMT_AVI_INFO0 0x189c
#define mmDIG0_AFMT_AVI_INFO0_BASE_IDX 2
#define mmDIG0_AFMT_AVI_INFO1 0x189d
#define mmDIG0_AFMT_AVI_INFO1_BASE_IDX 2
#define mmDIG0_AFMT_AVI_INFO2 0x189e
#define mmDIG0_AFMT_AVI_INFO2_BASE_IDX 2
#define mmDIG0_AFMT_AVI_INFO3 0x189f
#define mmDIG0_AFMT_AVI_INFO3_BASE_IDX 2
#define mmDIG0_AFMT_MPEG_INFO0 0x18a0
#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG0_AFMT_MPEG_INFO1 0x18a1
#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_HDR 0x18a2
#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_0 0x18a3
#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_1 0x18a4
#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_2 0x18a5
#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_3 0x18a6
#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_4 0x18a7
#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_5 0x18a8
#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_6 0x18a9
#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_7 0x18aa
#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x18ab
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_32_0 0x18ac
#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_32_1 0x18ad
#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_44_0 0x18ae
#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_44_1 0x18af
#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_48_0 0x18b0
#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_48_1 0x18b1
#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_STATUS_0 0x18b2
#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_STATUS_1 0x18b3
#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_INFO0 0x18b4
#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_INFO1 0x18b5
#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG0_AFMT_60958_0 0x18b6
#define mmDIG0_AFMT_60958_0_BASE_IDX 2
#define mmDIG0_AFMT_60958_1 0x18b7
#define mmDIG0_AFMT_60958_1_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x18b8
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL0 0x18b9
#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL1 0x18ba
#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL2 0x18bb
#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL3 0x18bc
#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG0_AFMT_60958_2 0x18bd
#define mmDIG0_AFMT_60958_2_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x18be
#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG0_AFMT_STATUS 0x18bf
#define mmDIG0_AFMT_STATUS_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x18c0
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x18c1
#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x18c2
#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x18c3
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG0_DIG_BE_CNTL 0x18c5
#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG0_DIG_BE_EN_CNTL 0x18c6
#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CNTL 0x18e9
#define mmDIG0_TMDS_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CONTROL_CHAR 0x18ea
#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x18eb
#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x18ec
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x18ed
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x18ee
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG0_TMDS_CTL_BITS 0x18f0
#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x18f1
#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x18f3
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x18f4
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG0_DIG_VERSION 0x18f6
#define mmDIG0_DIG_VERSION_BASE_IDX 2
#define mmDIG0_DIG_LANE_ENABLE 0x18f7
#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG0_AFMT_CNTL 0x18fc
#define mmDIG0_AFMT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dp0_dispdec
// base address: 0x0
#define mmDP0_DP_LINK_CNTL 0x191e
#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
#define mmDP0_DP_PIXEL_FORMAT 0x191f
#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP0_DP_MSA_COLORIMETRY 0x1920
#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP0_DP_CONFIG 0x1921
#define mmDP0_DP_CONFIG_BASE_IDX 2
#define mmDP0_DP_VID_STREAM_CNTL 0x1922
#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP0_DP_STEER_FIFO 0x1923
#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
#define mmDP0_DP_MSA_MISC 0x1924
#define mmDP0_DP_MSA_MISC_BASE_IDX 2
#define mmDP0_DP_VID_TIMING 0x1926
#define mmDP0_DP_VID_TIMING_BASE_IDX 2
#define mmDP0_DP_VID_N 0x1927
#define mmDP0_DP_VID_N_BASE_IDX 2
#define mmDP0_DP_VID_M 0x1928
#define mmDP0_DP_VID_M_BASE_IDX 2
#define mmDP0_DP_LINK_FRAMING_CNTL 0x1929
#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP0_DP_HBR2_EYE_PATTERN 0x192a
#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP0_DP_VID_MSA_VBID 0x192b
#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP0_DP_VID_INTERRUPT_CNTL 0x192c
#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CNTL 0x192d
#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x192e
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM0 0x192f
#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM1 0x1930
#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM2 0x1931
#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP0_DP_DPHY_8B10B_CNTL 0x1932
#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_PRBS_CNTL 0x1933
#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_SCRAM_CNTL 0x1934
#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_EN 0x1935
#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_CNTL 0x1936
#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_RESULT 0x1937
#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1938
#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1939
#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP0_DP_DPHY_FAST_TRAINING 0x193a
#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x193b
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x193c
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x193d
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL 0x1941
#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL1 0x1942
#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING1 0x1943
#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING2 0x1944
#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING3 0x1945
#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING4 0x1946
#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_N 0x1947
#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_N_READBACK 0x1948
#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_M 0x1949
#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_M_READBACK 0x194a
#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP0_DP_SEC_TIMESTAMP 0x194b
#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP0_DP_SEC_PACKET_CNTL 0x194c
#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP0_DP_MSE_RATE_CNTL 0x194d
#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP0_DP_MSE_RATE_UPDATE 0x194f
#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP0_DP_MSE_SAT0 0x1950
#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
#define mmDP0_DP_MSE_SAT1 0x1951
#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
#define mmDP0_DP_MSE_SAT2 0x1952
#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
#define mmDP0_DP_MSE_SAT_UPDATE 0x1953
#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP0_DP_MSE_LINK_TIMING 0x1954
#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP0_DP_MSE_MISC_CNTL 0x1955
#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x195a
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x195b
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP0_DP_MSE_SAT0_STATUS 0x195d
#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP0_DP_MSE_SAT1_STATUS 0x195e
#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP0_DP_MSE_SAT2_STATUS 0x195f
#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dig1_dispdec
// base address: 0x400
#define mmDIG1_DIG_FE_CNTL 0x197e
#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x197f
#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1980
#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG1_DIG_CLOCK_PATTERN 0x1981
#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG1_DIG_TEST_PATTERN 0x1982
#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1983
#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG1_DIG_FIFO_STATUS 0x1984
#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_CONTROL 0x1987
#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_STATUS 0x1988
#define mmDIG1_HDMI_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1989
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x198a
#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x198b
#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x198c
#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x198d
#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x198e
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG1_AFMT_INTERRUPT_STATUS 0x198f
#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_GC 0x1991
#define mmDIG1_HDMI_GC_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1992
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_0 0x1993
#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_1 0x1994
#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_2 0x1995
#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_3 0x1996
#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_4 0x1997
#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_0 0x1998
#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_1 0x1999
#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_2 0x199a
#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_3 0x199b
#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG1_AFMT_AVI_INFO0 0x199c
#define mmDIG1_AFMT_AVI_INFO0_BASE_IDX 2
#define mmDIG1_AFMT_AVI_INFO1 0x199d
#define mmDIG1_AFMT_AVI_INFO1_BASE_IDX 2
#define mmDIG1_AFMT_AVI_INFO2 0x199e
#define mmDIG1_AFMT_AVI_INFO2_BASE_IDX 2
#define mmDIG1_AFMT_AVI_INFO3 0x199f
#define mmDIG1_AFMT_AVI_INFO3_BASE_IDX 2
#define mmDIG1_AFMT_MPEG_INFO0 0x19a0
#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG1_AFMT_MPEG_INFO1 0x19a1
#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_HDR 0x19a2
#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_0 0x19a3
#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_1 0x19a4
#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_2 0x19a5
#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_3 0x19a6
#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_4 0x19a7
#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_5 0x19a8
#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_6 0x19a9
#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_7 0x19aa
#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x19ab
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_32_0 0x19ac
#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_32_1 0x19ad
#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_44_0 0x19ae
#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_44_1 0x19af
#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_48_0 0x19b0
#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_48_1 0x19b1
#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_STATUS_0 0x19b2
#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_STATUS_1 0x19b3
#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_INFO0 0x19b4
#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_INFO1 0x19b5
#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG1_AFMT_60958_0 0x19b6
#define mmDIG1_AFMT_60958_0_BASE_IDX 2
#define mmDIG1_AFMT_60958_1 0x19b7
#define mmDIG1_AFMT_60958_1_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x19b8
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL0 0x19b9
#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL1 0x19ba
#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL2 0x19bb
#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL3 0x19bc
#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG1_AFMT_60958_2 0x19bd
#define mmDIG1_AFMT_60958_2_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x19be
#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG1_AFMT_STATUS 0x19bf
#define mmDIG1_AFMT_STATUS_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x19c0
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x19c1
#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x19c2
#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x19c3
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG1_DIG_BE_CNTL 0x19c5
#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG1_DIG_BE_EN_CNTL 0x19c6
#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CNTL 0x19e9
#define mmDIG1_TMDS_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CONTROL_CHAR 0x19ea
#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x19eb
#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x19ec
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x19ed
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x19ee
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG1_TMDS_CTL_BITS 0x19f0
#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x19f1
#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x19f3
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x19f4
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG1_DIG_VERSION 0x19f6
#define mmDIG1_DIG_VERSION_BASE_IDX 2
#define mmDIG1_DIG_LANE_ENABLE 0x19f7
#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG1_AFMT_CNTL 0x19fc
#define mmDIG1_AFMT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dp1_dispdec
// base address: 0x400
#define mmDP1_DP_LINK_CNTL 0x1a1e
#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
#define mmDP1_DP_PIXEL_FORMAT 0x1a1f
#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP1_DP_MSA_COLORIMETRY 0x1a20
#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP1_DP_CONFIG 0x1a21
#define mmDP1_DP_CONFIG_BASE_IDX 2
#define mmDP1_DP_VID_STREAM_CNTL 0x1a22
#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP1_DP_STEER_FIFO 0x1a23
#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
#define mmDP1_DP_MSA_MISC 0x1a24
#define mmDP1_DP_MSA_MISC_BASE_IDX 2
#define mmDP1_DP_VID_TIMING 0x1a26
#define mmDP1_DP_VID_TIMING_BASE_IDX 2
#define mmDP1_DP_VID_N 0x1a27
#define mmDP1_DP_VID_N_BASE_IDX 2
#define mmDP1_DP_VID_M 0x1a28
#define mmDP1_DP_VID_M_BASE_IDX 2
#define mmDP1_DP_LINK_FRAMING_CNTL 0x1a29
#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP1_DP_HBR2_EYE_PATTERN 0x1a2a
#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP1_DP_VID_MSA_VBID 0x1a2b
#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1a2c
#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CNTL 0x1a2d
#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1a2e
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM0 0x1a2f
#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM1 0x1a30
#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM2 0x1a31
#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP1_DP_DPHY_8B10B_CNTL 0x1a32
#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_PRBS_CNTL 0x1a33
#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x1a34
#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_EN 0x1a35
#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_CNTL 0x1a36
#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_RESULT 0x1a37
#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1a38
#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1a39
#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP1_DP_DPHY_FAST_TRAINING 0x1a3a
#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1a3b
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1a3c
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1a3d
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL 0x1a41
#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL1 0x1a42
#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING1 0x1a43
#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING2 0x1a44
#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING3 0x1a45
#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING4 0x1a46
#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_N 0x1a47
#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_N_READBACK 0x1a48
#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_M 0x1a49
#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_M_READBACK 0x1a4a
#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP1_DP_SEC_TIMESTAMP 0x1a4b
#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP1_DP_SEC_PACKET_CNTL 0x1a4c
#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP1_DP_MSE_RATE_CNTL 0x1a4d
#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP1_DP_MSE_RATE_UPDATE 0x1a4f
#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP1_DP_MSE_SAT0 0x1a50
#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
#define mmDP1_DP_MSE_SAT1 0x1a51
#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
#define mmDP1_DP_MSE_SAT2 0x1a52
#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
#define mmDP1_DP_MSE_SAT_UPDATE 0x1a53
#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP1_DP_MSE_LINK_TIMING 0x1a54
#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP1_DP_MSE_MISC_CNTL 0x1a55
#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x1a5a
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x1a5b
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP1_DP_MSE_SAT0_STATUS 0x1a5d
#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP1_DP_MSE_SAT1_STATUS 0x1a5e
#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP1_DP_MSE_SAT2_STATUS 0x1a5f
#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dig2_dispdec
// base address: 0x800
#define mmDIG2_DIG_FE_CNTL 0x1a7e
#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x1a7f
#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x1a80
#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG2_DIG_CLOCK_PATTERN 0x1a81
#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG2_DIG_TEST_PATTERN 0x1a82
#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x1a83
#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG2_DIG_FIFO_STATUS 0x1a84
#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG2_HDMI_CONTROL 0x1a87
#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_STATUS 0x1a88
#define mmDIG2_HDMI_STATUS_BASE_IDX 2
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x1a89
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x1a8a
#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x1a8b
#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x1a8c
#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x1a8d
#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x1a8e
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG2_AFMT_INTERRUPT_STATUS 0x1a8f
#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG2_HDMI_GC 0x1a91
#define mmDIG2_HDMI_GC_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x1a92
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG2_AFMT_ISRC1_0 0x1a93
#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG2_AFMT_ISRC1_1 0x1a94
#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG2_AFMT_ISRC1_2 0x1a95
#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG2_AFMT_ISRC1_3 0x1a96
#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG2_AFMT_ISRC1_4 0x1a97
#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG2_AFMT_ISRC2_0 0x1a98
#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG2_AFMT_ISRC2_1 0x1a99
#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG2_AFMT_ISRC2_2 0x1a9a
#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG2_AFMT_ISRC2_3 0x1a9b
#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG2_AFMT_AVI_INFO0 0x1a9c
#define mmDIG2_AFMT_AVI_INFO0_BASE_IDX 2
#define mmDIG2_AFMT_AVI_INFO1 0x1a9d
#define mmDIG2_AFMT_AVI_INFO1_BASE_IDX 2
#define mmDIG2_AFMT_AVI_INFO2 0x1a9e
#define mmDIG2_AFMT_AVI_INFO2_BASE_IDX 2
#define mmDIG2_AFMT_AVI_INFO3 0x1a9f
#define mmDIG2_AFMT_AVI_INFO3_BASE_IDX 2
#define mmDIG2_AFMT_MPEG_INFO0 0x1aa0
#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG2_AFMT_MPEG_INFO1 0x1aa1
#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_HDR 0x1aa2
#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_0 0x1aa3
#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_1 0x1aa4
#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_2 0x1aa5
#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_3 0x1aa6
#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_4 0x1aa7
#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_5 0x1aa8
#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_6 0x1aa9
#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_7 0x1aaa
#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x1aab
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_32_0 0x1aac
#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_32_1 0x1aad
#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_44_0 0x1aae
#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_44_1 0x1aaf
#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_48_0 0x1ab0
#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_48_1 0x1ab1
#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_STATUS_0 0x1ab2
#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_STATUS_1 0x1ab3
#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_INFO0 0x1ab4
#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_INFO1 0x1ab5
#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG2_AFMT_60958_0 0x1ab6
#define mmDIG2_AFMT_60958_0_BASE_IDX 2
#define mmDIG2_AFMT_60958_1 0x1ab7
#define mmDIG2_AFMT_60958_1_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x1ab8
#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG2_AFMT_RAMP_CONTROL0 0x1ab9
#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG2_AFMT_RAMP_CONTROL1 0x1aba
#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG2_AFMT_RAMP_CONTROL2 0x1abb
#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG2_AFMT_RAMP_CONTROL3 0x1abc
#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG2_AFMT_60958_2 0x1abd
#define mmDIG2_AFMT_60958_2_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x1abe
#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG2_AFMT_STATUS 0x1abf
#define mmDIG2_AFMT_STATUS_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x1ac0
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x1ac1
#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x1ac2
#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x1ac3
#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG2_DIG_BE_CNTL 0x1ac5
#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG2_DIG_BE_EN_CNTL 0x1ac6
#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG2_TMDS_CNTL 0x1ae9
#define mmDIG2_TMDS_CNTL_BASE_IDX 2
#define mmDIG2_TMDS_CONTROL_CHAR 0x1aea
#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x1aeb
#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x1aec
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x1aed
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x1aee
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG2_TMDS_CTL_BITS 0x1af0
#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x1af1
#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x1af3
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x1af4
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG2_DIG_VERSION 0x1af6
#define mmDIG2_DIG_VERSION_BASE_IDX 2
#define mmDIG2_DIG_LANE_ENABLE 0x1af7
#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG2_AFMT_CNTL 0x1afc
#define mmDIG2_AFMT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dp2_dispdec
// base address: 0x800
#define mmDP2_DP_LINK_CNTL 0x1b1e
#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
#define mmDP2_DP_PIXEL_FORMAT 0x1b1f
#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP2_DP_MSA_COLORIMETRY 0x1b20
#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP2_DP_CONFIG 0x1b21
#define mmDP2_DP_CONFIG_BASE_IDX 2
#define mmDP2_DP_VID_STREAM_CNTL 0x1b22
#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP2_DP_STEER_FIFO 0x1b23
#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
#define mmDP2_DP_MSA_MISC 0x1b24
#define mmDP2_DP_MSA_MISC_BASE_IDX 2
#define mmDP2_DP_VID_TIMING 0x1b26
#define mmDP2_DP_VID_TIMING_BASE_IDX 2
#define mmDP2_DP_VID_N 0x1b27
#define mmDP2_DP_VID_N_BASE_IDX 2
#define mmDP2_DP_VID_M 0x1b28
#define mmDP2_DP_VID_M_BASE_IDX 2
#define mmDP2_DP_LINK_FRAMING_CNTL 0x1b29
#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP2_DP_HBR2_EYE_PATTERN 0x1b2a
#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP2_DP_VID_MSA_VBID 0x1b2b
#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP2_DP_VID_INTERRUPT_CNTL 0x1b2c
#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CNTL 0x1b2d
#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x1b2e
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP2_DP_DPHY_SYM0 0x1b2f
#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP2_DP_DPHY_SYM1 0x1b30
#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP2_DP_DPHY_SYM2 0x1b31
#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP2_DP_DPHY_8B10B_CNTL 0x1b32
#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_PRBS_CNTL 0x1b33
#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_SCRAM_CNTL 0x1b34
#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_EN 0x1b35
#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_CNTL 0x1b36
#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_RESULT 0x1b37
#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x1b38
#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x1b39
#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP2_DP_DPHY_FAST_TRAINING 0x1b3a
#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x1b3b
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x1b3c
#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x1b3d
#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL 0x1b41
#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL1 0x1b42
#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING1 0x1b43
#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING2 0x1b44
#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING3 0x1b45
#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING4 0x1b46
#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_N 0x1b47
#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_N_READBACK 0x1b48
#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_M 0x1b49
#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_M_READBACK 0x1b4a
#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP2_DP_SEC_TIMESTAMP 0x1b4b
#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP2_DP_SEC_PACKET_CNTL 0x1b4c
#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP2_DP_MSE_RATE_CNTL 0x1b4d
#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP2_DP_MSE_RATE_UPDATE 0x1b4f
#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP2_DP_MSE_SAT0 0x1b50
#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
#define mmDP2_DP_MSE_SAT1 0x1b51
#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
#define mmDP2_DP_MSE_SAT2 0x1b52
#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
#define mmDP2_DP_MSE_SAT_UPDATE 0x1b53
#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP2_DP_MSE_LINK_TIMING 0x1b54
#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP2_DP_MSE_MISC_CNTL 0x1b55
#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x1b5a
#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x1b5b
#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP2_DP_MSE_SAT0_STATUS 0x1b5d
#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP2_DP_MSE_SAT1_STATUS 0x1b5e
#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP2_DP_MSE_SAT2_STATUS 0x1b5f
#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dig3_dispdec
// base address: 0xc00
#define mmDIG3_DIG_FE_CNTL 0x1b7e
#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x1b7f
#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x1b80
#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG3_DIG_CLOCK_PATTERN 0x1b81
#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG3_DIG_TEST_PATTERN 0x1b82
#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x1b83
#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG3_DIG_FIFO_STATUS 0x1b84
#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG3_HDMI_CONTROL 0x1b87
#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_STATUS 0x1b88
#define mmDIG3_HDMI_STATUS_BASE_IDX 2
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x1b89
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x1b8a
#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x1b8b
#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x1b8c
#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x1b8d
#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x1b8e
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG3_AFMT_INTERRUPT_STATUS 0x1b8f
#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG3_HDMI_GC 0x1b91
#define mmDIG3_HDMI_GC_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x1b92
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG3_AFMT_ISRC1_0 0x1b93
#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG3_AFMT_ISRC1_1 0x1b94
#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG3_AFMT_ISRC1_2 0x1b95
#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG3_AFMT_ISRC1_3 0x1b96
#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG3_AFMT_ISRC1_4 0x1b97
#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG3_AFMT_ISRC2_0 0x1b98
#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG3_AFMT_ISRC2_1 0x1b99
#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG3_AFMT_ISRC2_2 0x1b9a
#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG3_AFMT_ISRC2_3 0x1b9b
#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG3_AFMT_AVI_INFO0 0x1b9c
#define mmDIG3_AFMT_AVI_INFO0_BASE_IDX 2
#define mmDIG3_AFMT_AVI_INFO1 0x1b9d
#define mmDIG3_AFMT_AVI_INFO1_BASE_IDX 2
#define mmDIG3_AFMT_AVI_INFO2 0x1b9e
#define mmDIG3_AFMT_AVI_INFO2_BASE_IDX 2
#define mmDIG3_AFMT_AVI_INFO3 0x1b9f
#define mmDIG3_AFMT_AVI_INFO3_BASE_IDX 2
#define mmDIG3_AFMT_MPEG_INFO0 0x1ba0
#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG3_AFMT_MPEG_INFO1 0x1ba1
#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_HDR 0x1ba2
#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_0 0x1ba3
#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_1 0x1ba4
#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_2 0x1ba5
#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_3 0x1ba6
#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_4 0x1ba7
#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_5 0x1ba8
#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_6 0x1ba9
#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_7 0x1baa
#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x1bab
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_32_0 0x1bac
#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_32_1 0x1bad
#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_44_0 0x1bae
#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_44_1 0x1baf
#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_48_0 0x1bb0
#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_48_1 0x1bb1
#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_STATUS_0 0x1bb2
#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_STATUS_1 0x1bb3
#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_INFO0 0x1bb4
#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_INFO1 0x1bb5
#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG3_AFMT_60958_0 0x1bb6
#define mmDIG3_AFMT_60958_0_BASE_IDX 2
#define mmDIG3_AFMT_60958_1 0x1bb7
#define mmDIG3_AFMT_60958_1_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x1bb8
#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG3_AFMT_RAMP_CONTROL0 0x1bb9
#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG3_AFMT_RAMP_CONTROL1 0x1bba
#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG3_AFMT_RAMP_CONTROL2 0x1bbb
#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG3_AFMT_RAMP_CONTROL3 0x1bbc
#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG3_AFMT_60958_2 0x1bbd
#define mmDIG3_AFMT_60958_2_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x1bbe
#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG3_AFMT_STATUS 0x1bbf
#define mmDIG3_AFMT_STATUS_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x1bc0
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x1bc1
#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x1bc2
#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x1bc3
#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG3_DIG_BE_CNTL 0x1bc5
#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG3_DIG_BE_EN_CNTL 0x1bc6
#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG3_TMDS_CNTL 0x1be9
#define mmDIG3_TMDS_CNTL_BASE_IDX 2
#define mmDIG3_TMDS_CONTROL_CHAR 0x1bea
#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x1beb
#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x1bec
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x1bed
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x1bee
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG3_TMDS_CTL_BITS 0x1bf0
#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x1bf1
#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x1bf3
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x1bf4
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG3_DIG_VERSION 0x1bf6
#define mmDIG3_DIG_VERSION_BASE_IDX 2
#define mmDIG3_DIG_LANE_ENABLE 0x1bf7
#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG3_AFMT_CNTL 0x1bfc
#define mmDIG3_AFMT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dp3_dispdec
// base address: 0xc00
#define mmDP3_DP_LINK_CNTL 0x1c1e
#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
#define mmDP3_DP_PIXEL_FORMAT 0x1c1f
#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP3_DP_MSA_COLORIMETRY 0x1c20
#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP3_DP_CONFIG 0x1c21
#define mmDP3_DP_CONFIG_BASE_IDX 2
#define mmDP3_DP_VID_STREAM_CNTL 0x1c22
#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP3_DP_STEER_FIFO 0x1c23
#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
#define mmDP3_DP_MSA_MISC 0x1c24
#define mmDP3_DP_MSA_MISC_BASE_IDX 2
#define mmDP3_DP_VID_TIMING 0x1c26
#define mmDP3_DP_VID_TIMING_BASE_IDX 2
#define mmDP3_DP_VID_N 0x1c27
#define mmDP3_DP_VID_N_BASE_IDX 2
#define mmDP3_DP_VID_M 0x1c28
#define mmDP3_DP_VID_M_BASE_IDX 2
#define mmDP3_DP_LINK_FRAMING_CNTL 0x1c29
#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP3_DP_HBR2_EYE_PATTERN 0x1c2a
#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP3_DP_VID_MSA_VBID 0x1c2b
#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP3_DP_VID_INTERRUPT_CNTL 0x1c2c
#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CNTL 0x1c2d
#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x1c2e
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP3_DP_DPHY_SYM0 0x1c2f
#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP3_DP_DPHY_SYM1 0x1c30
#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP3_DP_DPHY_SYM2 0x1c31
#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP3_DP_DPHY_8B10B_CNTL 0x1c32
#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_PRBS_CNTL 0x1c33
#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_SCRAM_CNTL 0x1c34
#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_EN 0x1c35
#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_CNTL 0x1c36
#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_RESULT 0x1c37
#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x1c38
#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x1c39
#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP3_DP_DPHY_FAST_TRAINING 0x1c3a
#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x1c3b
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x1c3c
#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x1c3d
#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL 0x1c41
#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL1 0x1c42
#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING1 0x1c43
#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING2 0x1c44
#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING3 0x1c45
#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING4 0x1c46
#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_N 0x1c47
#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_N_READBACK 0x1c48
#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_M 0x1c49
#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_M_READBACK 0x1c4a
#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP3_DP_SEC_TIMESTAMP 0x1c4b
#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP3_DP_SEC_PACKET_CNTL 0x1c4c
#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP3_DP_MSE_RATE_CNTL 0x1c4d
#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP3_DP_MSE_RATE_UPDATE 0x1c4f
#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP3_DP_MSE_SAT0 0x1c50
#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
#define mmDP3_DP_MSE_SAT1 0x1c51
#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
#define mmDP3_DP_MSE_SAT2 0x1c52
#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
#define mmDP3_DP_MSE_SAT_UPDATE 0x1c53
#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP3_DP_MSE_LINK_TIMING 0x1c54
#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP3_DP_MSE_MISC_CNTL 0x1c55
#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x1c5a
#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x1c5b
#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP3_DP_MSE_SAT0_STATUS 0x1c5d
#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP3_DP_MSE_SAT1_STATUS 0x1c5e
#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP3_DP_MSE_SAT2_STATUS 0x1c5f
#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dig4_dispdec
// base address: 0x1000
#define mmDIG4_DIG_FE_CNTL 0x1c7e
#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x1c7f
#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x1c80
#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG4_DIG_CLOCK_PATTERN 0x1c81
#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG4_DIG_TEST_PATTERN 0x1c82
#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x1c83
#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG4_DIG_FIFO_STATUS 0x1c84
#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG4_HDMI_CONTROL 0x1c87
#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_STATUS 0x1c88
#define mmDIG4_HDMI_STATUS_BASE_IDX 2
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x1c89
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x1c8a
#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x1c8b
#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x1c8c
#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x1c8d
#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x1c8e
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG4_AFMT_INTERRUPT_STATUS 0x1c8f
#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG4_HDMI_GC 0x1c91
#define mmDIG4_HDMI_GC_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x1c92
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG4_AFMT_ISRC1_0 0x1c93
#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG4_AFMT_ISRC1_1 0x1c94
#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG4_AFMT_ISRC1_2 0x1c95
#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG4_AFMT_ISRC1_3 0x1c96
#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG4_AFMT_ISRC1_4 0x1c97
#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG4_AFMT_ISRC2_0 0x1c98
#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG4_AFMT_ISRC2_1 0x1c99
#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG4_AFMT_ISRC2_2 0x1c9a
#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG4_AFMT_ISRC2_3 0x1c9b
#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG4_AFMT_AVI_INFO0 0x1c9c
#define mmDIG4_AFMT_AVI_INFO0_BASE_IDX 2
#define mmDIG4_AFMT_AVI_INFO1 0x1c9d
#define mmDIG4_AFMT_AVI_INFO1_BASE_IDX 2
#define mmDIG4_AFMT_AVI_INFO2 0x1c9e
#define mmDIG4_AFMT_AVI_INFO2_BASE_IDX 2
#define mmDIG4_AFMT_AVI_INFO3 0x1c9f
#define mmDIG4_AFMT_AVI_INFO3_BASE_IDX 2
#define mmDIG4_AFMT_MPEG_INFO0 0x1ca0
#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG4_AFMT_MPEG_INFO1 0x1ca1
#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_HDR 0x1ca2
#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_0 0x1ca3
#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_1 0x1ca4
#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_2 0x1ca5
#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_3 0x1ca6
#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_4 0x1ca7
#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_5 0x1ca8
#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_6 0x1ca9
#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_7 0x1caa
#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x1cab
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_32_0 0x1cac
#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_32_1 0x1cad
#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_44_0 0x1cae
#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_44_1 0x1caf
#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_48_0 0x1cb0
#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_48_1 0x1cb1
#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_STATUS_0 0x1cb2
#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_STATUS_1 0x1cb3
#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_INFO0 0x1cb4
#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_INFO1 0x1cb5
#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG4_AFMT_60958_0 0x1cb6
#define mmDIG4_AFMT_60958_0_BASE_IDX 2
#define mmDIG4_AFMT_60958_1 0x1cb7
#define mmDIG4_AFMT_60958_1_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x1cb8
#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG4_AFMT_RAMP_CONTROL0 0x1cb9
#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG4_AFMT_RAMP_CONTROL1 0x1cba
#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG4_AFMT_RAMP_CONTROL2 0x1cbb
#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG4_AFMT_RAMP_CONTROL3 0x1cbc
#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG4_AFMT_60958_2 0x1cbd
#define mmDIG4_AFMT_60958_2_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x1cbe
#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG4_AFMT_STATUS 0x1cbf
#define mmDIG4_AFMT_STATUS_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x1cc0
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x1cc1
#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x1cc2
#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x1cc3
#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG4_DIG_BE_CNTL 0x1cc5
#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG4_DIG_BE_EN_CNTL 0x1cc6
#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG4_TMDS_CNTL 0x1ce9
#define mmDIG4_TMDS_CNTL_BASE_IDX 2
#define mmDIG4_TMDS_CONTROL_CHAR 0x1cea
#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x1ceb
#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x1cec
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ced
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x1cee
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG4_TMDS_CTL_BITS 0x1cf0
#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x1cf1
#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x1cf3
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x1cf4
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG4_DIG_VERSION 0x1cf6
#define mmDIG4_DIG_VERSION_BASE_IDX 2
#define mmDIG4_DIG_LANE_ENABLE 0x1cf7
#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG4_AFMT_CNTL 0x1cfc
#define mmDIG4_AFMT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dp4_dispdec
// base address: 0x1000
#define mmDP4_DP_LINK_CNTL 0x1d1e
#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
#define mmDP4_DP_PIXEL_FORMAT 0x1d1f
#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP4_DP_MSA_COLORIMETRY 0x1d20
#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP4_DP_CONFIG 0x1d21
#define mmDP4_DP_CONFIG_BASE_IDX 2
#define mmDP4_DP_VID_STREAM_CNTL 0x1d22
#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP4_DP_STEER_FIFO 0x1d23
#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
#define mmDP4_DP_MSA_MISC 0x1d24
#define mmDP4_DP_MSA_MISC_BASE_IDX 2
#define mmDP4_DP_VID_TIMING 0x1d26
#define mmDP4_DP_VID_TIMING_BASE_IDX 2
#define mmDP4_DP_VID_N 0x1d27
#define mmDP4_DP_VID_N_BASE_IDX 2
#define mmDP4_DP_VID_M 0x1d28
#define mmDP4_DP_VID_M_BASE_IDX 2
#define mmDP4_DP_LINK_FRAMING_CNTL 0x1d29
#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP4_DP_HBR2_EYE_PATTERN 0x1d2a
#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP4_DP_VID_MSA_VBID 0x1d2b
#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP4_DP_VID_INTERRUPT_CNTL 0x1d2c
#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CNTL 0x1d2d
#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x1d2e
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP4_DP_DPHY_SYM0 0x1d2f
#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP4_DP_DPHY_SYM1 0x1d30
#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP4_DP_DPHY_SYM2 0x1d31
#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP4_DP_DPHY_8B10B_CNTL 0x1d32
#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_PRBS_CNTL 0x1d33
#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_SCRAM_CNTL 0x1d34
#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_EN 0x1d35
#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_CNTL 0x1d36
#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_RESULT 0x1d37
#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x1d38
#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x1d39
#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP4_DP_DPHY_FAST_TRAINING 0x1d3a
#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x1d3b
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x1d3c
#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x1d3d
#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL 0x1d41
#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL1 0x1d42
#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING1 0x1d43
#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING2 0x1d44
#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING3 0x1d45
#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING4 0x1d46
#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_N 0x1d47
#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_N_READBACK 0x1d48
#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_M 0x1d49
#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_M_READBACK 0x1d4a
#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP4_DP_SEC_TIMESTAMP 0x1d4b
#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP4_DP_SEC_PACKET_CNTL 0x1d4c
#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP4_DP_MSE_RATE_CNTL 0x1d4d
#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP4_DP_MSE_RATE_UPDATE 0x1d4f
#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP4_DP_MSE_SAT0 0x1d50
#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
#define mmDP4_DP_MSE_SAT1 0x1d51
#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
#define mmDP4_DP_MSE_SAT2 0x1d52
#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
#define mmDP4_DP_MSE_SAT_UPDATE 0x1d53
#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP4_DP_MSE_LINK_TIMING 0x1d54
#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP4_DP_MSE_MISC_CNTL 0x1d55
#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x1d5a
#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x1d5b
#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP4_DP_MSE_SAT0_STATUS 0x1d5d
#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP4_DP_MSE_SAT1_STATUS 0x1d5e
#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP4_DP_MSE_SAT2_STATUS 0x1d5f
#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dig5_dispdec
// base address: 0x1400
#define mmDIG5_DIG_FE_CNTL 0x1d7e
#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x1d7f
#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x1d80
#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG5_DIG_CLOCK_PATTERN 0x1d81
#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG5_DIG_TEST_PATTERN 0x1d82
#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x1d83
#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG5_DIG_FIFO_STATUS 0x1d84
#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG5_HDMI_CONTROL 0x1d87
#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_STATUS 0x1d88
#define mmDIG5_HDMI_STATUS_BASE_IDX 2
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x1d89
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x1d8a
#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x1d8b
#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x1d8c
#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x1d8d
#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x1d8e
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG5_AFMT_INTERRUPT_STATUS 0x1d8f
#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG5_HDMI_GC 0x1d91
#define mmDIG5_HDMI_GC_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x1d92
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG5_AFMT_ISRC1_0 0x1d93
#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG5_AFMT_ISRC1_1 0x1d94
#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG5_AFMT_ISRC1_2 0x1d95
#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG5_AFMT_ISRC1_3 0x1d96
#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG5_AFMT_ISRC1_4 0x1d97
#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG5_AFMT_ISRC2_0 0x1d98
#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG5_AFMT_ISRC2_1 0x1d99
#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG5_AFMT_ISRC2_2 0x1d9a
#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG5_AFMT_ISRC2_3 0x1d9b
#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG5_AFMT_AVI_INFO0 0x1d9c
#define mmDIG5_AFMT_AVI_INFO0_BASE_IDX 2
#define mmDIG5_AFMT_AVI_INFO1 0x1d9d
#define mmDIG5_AFMT_AVI_INFO1_BASE_IDX 2
#define mmDIG5_AFMT_AVI_INFO2 0x1d9e
#define mmDIG5_AFMT_AVI_INFO2_BASE_IDX 2
#define mmDIG5_AFMT_AVI_INFO3 0x1d9f
#define mmDIG5_AFMT_AVI_INFO3_BASE_IDX 2
#define mmDIG5_AFMT_MPEG_INFO0 0x1da0
#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG5_AFMT_MPEG_INFO1 0x1da1
#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_HDR 0x1da2
#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_0 0x1da3
#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_1 0x1da4
#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_2 0x1da5
#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_3 0x1da6
#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_4 0x1da7
#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_5 0x1da8
#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_6 0x1da9
#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_7 0x1daa
#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x1dab
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_32_0 0x1dac
#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_32_1 0x1dad
#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_44_0 0x1dae
#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_44_1 0x1daf
#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_48_0 0x1db0
#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_48_1 0x1db1
#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_STATUS_0 0x1db2
#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_STATUS_1 0x1db3
#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_INFO0 0x1db4
#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_INFO1 0x1db5
#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG5_AFMT_60958_0 0x1db6
#define mmDIG5_AFMT_60958_0_BASE_IDX 2
#define mmDIG5_AFMT_60958_1 0x1db7
#define mmDIG5_AFMT_60958_1_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x1db8
#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG5_AFMT_RAMP_CONTROL0 0x1db9
#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG5_AFMT_RAMP_CONTROL1 0x1dba
#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG5_AFMT_RAMP_CONTROL2 0x1dbb
#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG5_AFMT_RAMP_CONTROL3 0x1dbc
#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG5_AFMT_60958_2 0x1dbd
#define mmDIG5_AFMT_60958_2_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x1dbe
#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG5_AFMT_STATUS 0x1dbf
#define mmDIG5_AFMT_STATUS_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x1dc0
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x1dc1
#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x1dc2
#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x1dc3
#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG5_DIG_BE_CNTL 0x1dc5
#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG5_DIG_BE_EN_CNTL 0x1dc6
#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG5_TMDS_CNTL 0x1de9
#define mmDIG5_TMDS_CNTL_BASE_IDX 2
#define mmDIG5_TMDS_CONTROL_CHAR 0x1dea
#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x1deb
#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x1dec
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ded
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x1dee
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG5_TMDS_CTL_BITS 0x1df0
#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x1df1
#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x1df3
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x1df4
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG5_DIG_VERSION 0x1df6
#define mmDIG5_DIG_VERSION_BASE_IDX 2
#define mmDIG5_DIG_LANE_ENABLE 0x1df7
#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG5_AFMT_CNTL 0x1dfc
#define mmDIG5_AFMT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dp5_dispdec
// base address: 0x1400
#define mmDP5_DP_LINK_CNTL 0x1e1e
#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
#define mmDP5_DP_PIXEL_FORMAT 0x1e1f
#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP5_DP_MSA_COLORIMETRY 0x1e20
#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP5_DP_CONFIG 0x1e21
#define mmDP5_DP_CONFIG_BASE_IDX 2
#define mmDP5_DP_VID_STREAM_CNTL 0x1e22
#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP5_DP_STEER_FIFO 0x1e23
#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
#define mmDP5_DP_MSA_MISC 0x1e24
#define mmDP5_DP_MSA_MISC_BASE_IDX 2
#define mmDP5_DP_VID_TIMING 0x1e26
#define mmDP5_DP_VID_TIMING_BASE_IDX 2
#define mmDP5_DP_VID_N 0x1e27
#define mmDP5_DP_VID_N_BASE_IDX 2
#define mmDP5_DP_VID_M 0x1e28
#define mmDP5_DP_VID_M_BASE_IDX 2
#define mmDP5_DP_LINK_FRAMING_CNTL 0x1e29
#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP5_DP_HBR2_EYE_PATTERN 0x1e2a
#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP5_DP_VID_MSA_VBID 0x1e2b
#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP5_DP_VID_INTERRUPT_CNTL 0x1e2c
#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CNTL 0x1e2d
#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x1e2e
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP5_DP_DPHY_SYM0 0x1e2f
#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP5_DP_DPHY_SYM1 0x1e30
#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP5_DP_DPHY_SYM2 0x1e31
#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP5_DP_DPHY_8B10B_CNTL 0x1e32
#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_PRBS_CNTL 0x1e33
#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x1e34
#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_EN 0x1e35
#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_CNTL 0x1e36
#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_RESULT 0x1e37
#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x1e38
#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x1e39
#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP5_DP_DPHY_FAST_TRAINING 0x1e3a
#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x1e3b
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x1e3c
#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x1e3d
#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL 0x1e41
#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL1 0x1e42
#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING1 0x1e43
#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING2 0x1e44
#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING3 0x1e45
#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING4 0x1e46
#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_N 0x1e47
#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_N_READBACK 0x1e48
#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_M 0x1e49
#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_M_READBACK 0x1e4a
#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP5_DP_SEC_TIMESTAMP 0x1e4b
#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP5_DP_SEC_PACKET_CNTL 0x1e4c
#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP5_DP_MSE_RATE_CNTL 0x1e4d
#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP5_DP_MSE_RATE_UPDATE 0x1e4f
#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP5_DP_MSE_SAT0 0x1e50
#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
#define mmDP5_DP_MSE_SAT1 0x1e51
#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
#define mmDP5_DP_MSE_SAT2 0x1e52
#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
#define mmDP5_DP_MSE_SAT_UPDATE 0x1e53
#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP5_DP_MSE_LINK_TIMING 0x1e54
#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP5_DP_MSE_MISC_CNTL 0x1e55
#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x1e5a
#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x1e5b
#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP5_DP_MSE_SAT0_STATUS 0x1e5d
#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP5_DP_MSE_SAT1_STATUS 0x1e5e
#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP5_DP_MSE_SAT2_STATUS 0x1e5f
#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dig6_dispdec
// base address: 0x1800
#define mmDIG6_DIG_FE_CNTL 0x1e7e
#define mmDIG6_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x1e7f
#define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x1e80
#define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG6_DIG_CLOCK_PATTERN 0x1e81
#define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG6_DIG_TEST_PATTERN 0x1e82
#define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x1e83
#define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG6_DIG_FIFO_STATUS 0x1e84
#define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG6_HDMI_CONTROL 0x1e87
#define mmDIG6_HDMI_CONTROL_BASE_IDX 2
#define mmDIG6_HDMI_STATUS 0x1e88
#define mmDIG6_HDMI_STATUS_BASE_IDX 2
#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x1e89
#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x1e8a
#define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x1e8b
#define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x1e8c
#define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x1e8d
#define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x1e8e
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG6_AFMT_INTERRUPT_STATUS 0x1e8f
#define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG6_HDMI_GC 0x1e91
#define mmDIG6_HDMI_GC_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x1e92
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG6_AFMT_ISRC1_0 0x1e93
#define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG6_AFMT_ISRC1_1 0x1e94
#define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG6_AFMT_ISRC1_2 0x1e95
#define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG6_AFMT_ISRC1_3 0x1e96
#define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG6_AFMT_ISRC1_4 0x1e97
#define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG6_AFMT_ISRC2_0 0x1e98
#define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG6_AFMT_ISRC2_1 0x1e99
#define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG6_AFMT_ISRC2_2 0x1e9a
#define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG6_AFMT_ISRC2_3 0x1e9b
#define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG6_AFMT_AVI_INFO0 0x1e9c
#define mmDIG6_AFMT_AVI_INFO0_BASE_IDX 2
#define mmDIG6_AFMT_AVI_INFO1 0x1e9d
#define mmDIG6_AFMT_AVI_INFO1_BASE_IDX 2
#define mmDIG6_AFMT_AVI_INFO2 0x1e9e
#define mmDIG6_AFMT_AVI_INFO2_BASE_IDX 2
#define mmDIG6_AFMT_AVI_INFO3 0x1e9f
#define mmDIG6_AFMT_AVI_INFO3_BASE_IDX 2
#define mmDIG6_AFMT_MPEG_INFO0 0x1ea0
#define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG6_AFMT_MPEG_INFO1 0x1ea1
#define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_HDR 0x1ea2
#define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_0 0x1ea3
#define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_1 0x1ea4
#define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_2 0x1ea5
#define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_3 0x1ea6
#define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_4 0x1ea7
#define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_5 0x1ea8
#define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_6 0x1ea9
#define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_7 0x1eaa
#define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x1eab
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG6_HDMI_ACR_32_0 0x1eac
#define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG6_HDMI_ACR_32_1 0x1ead
#define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG6_HDMI_ACR_44_0 0x1eae
#define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG6_HDMI_ACR_44_1 0x1eaf
#define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG6_HDMI_ACR_48_0 0x1eb0
#define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG6_HDMI_ACR_48_1 0x1eb1
#define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG6_HDMI_ACR_STATUS_0 0x1eb2
#define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG6_HDMI_ACR_STATUS_1 0x1eb3
#define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_INFO0 0x1eb4
#define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_INFO1 0x1eb5
#define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG6_AFMT_60958_0 0x1eb6
#define mmDIG6_AFMT_60958_0_BASE_IDX 2
#define mmDIG6_AFMT_60958_1 0x1eb7
#define mmDIG6_AFMT_60958_1_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x1eb8
#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG6_AFMT_RAMP_CONTROL0 0x1eb9
#define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG6_AFMT_RAMP_CONTROL1 0x1eba
#define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG6_AFMT_RAMP_CONTROL2 0x1ebb
#define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG6_AFMT_RAMP_CONTROL3 0x1ebc
#define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG6_AFMT_60958_2 0x1ebd
#define mmDIG6_AFMT_60958_2_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x1ebe
#define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG6_AFMT_STATUS 0x1ebf
#define mmDIG6_AFMT_STATUS_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x1ec0
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x1ec1
#define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x1ec2
#define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x1ec3
#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG6_DIG_BE_CNTL 0x1ec5
#define mmDIG6_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG6_DIG_BE_EN_CNTL 0x1ec6
#define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG6_TMDS_CNTL 0x1ee9
#define mmDIG6_TMDS_CNTL_BASE_IDX 2
#define mmDIG6_TMDS_CONTROL_CHAR 0x1eea
#define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x1eeb
#define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x1eec
#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x1eed
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x1eee
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG6_TMDS_CTL_BITS 0x1ef0
#define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x1ef1
#define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x1ef3
#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x1ef4
#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG6_DIG_VERSION 0x1ef6
#define mmDIG6_DIG_VERSION_BASE_IDX 2
#define mmDIG6_DIG_LANE_ENABLE 0x1ef7
#define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG6_AFMT_CNTL 0x1efc
#define mmDIG6_AFMT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dp6_dispdec
// base address: 0x1800
#define mmDP6_DP_LINK_CNTL 0x1f1e
#define mmDP6_DP_LINK_CNTL_BASE_IDX 2
#define mmDP6_DP_PIXEL_FORMAT 0x1f1f
#define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP6_DP_MSA_COLORIMETRY 0x1f20
#define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP6_DP_CONFIG 0x1f21
#define mmDP6_DP_CONFIG_BASE_IDX 2
#define mmDP6_DP_VID_STREAM_CNTL 0x1f22
#define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP6_DP_STEER_FIFO 0x1f23
#define mmDP6_DP_STEER_FIFO_BASE_IDX 2
#define mmDP6_DP_MSA_MISC 0x1f24
#define mmDP6_DP_MSA_MISC_BASE_IDX 2
#define mmDP6_DP_VID_TIMING 0x1f26
#define mmDP6_DP_VID_TIMING_BASE_IDX 2
#define mmDP6_DP_VID_N 0x1f27
#define mmDP6_DP_VID_N_BASE_IDX 2
#define mmDP6_DP_VID_M 0x1f28
#define mmDP6_DP_VID_M_BASE_IDX 2
#define mmDP6_DP_LINK_FRAMING_CNTL 0x1f29
#define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP6_DP_HBR2_EYE_PATTERN 0x1f2a
#define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP6_DP_VID_MSA_VBID 0x1f2b
#define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP6_DP_VID_INTERRUPT_CNTL 0x1f2c
#define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_CNTL 0x1f2d
#define mmDP6_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x1f2e
#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP6_DP_DPHY_SYM0 0x1f2f
#define mmDP6_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP6_DP_DPHY_SYM1 0x1f30
#define mmDP6_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP6_DP_DPHY_SYM2 0x1f31
#define mmDP6_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP6_DP_DPHY_8B10B_CNTL 0x1f32
#define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_PRBS_CNTL 0x1f33
#define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_SCRAM_CNTL 0x1f34
#define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_CRC_EN 0x1f35
#define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP6_DP_DPHY_CRC_CNTL 0x1f36
#define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_CRC_RESULT 0x1f37
#define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x1f38
#define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x1f39
#define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP6_DP_DPHY_FAST_TRAINING 0x1f3a
#define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x1f3b
#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x1f3c
#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x1f3d
#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
#define mmDP6_DP_SEC_CNTL 0x1f41
#define mmDP6_DP_SEC_CNTL_BASE_IDX 2
#define mmDP6_DP_SEC_CNTL1 0x1f42
#define mmDP6_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP6_DP_SEC_FRAMING1 0x1f43
#define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP6_DP_SEC_FRAMING2 0x1f44
#define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP6_DP_SEC_FRAMING3 0x1f45
#define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP6_DP_SEC_FRAMING4 0x1f46
#define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP6_DP_SEC_AUD_N 0x1f47
#define mmDP6_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP6_DP_SEC_AUD_N_READBACK 0x1f48
#define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP6_DP_SEC_AUD_M 0x1f49
#define mmDP6_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP6_DP_SEC_AUD_M_READBACK 0x1f4a
#define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP6_DP_SEC_TIMESTAMP 0x1f4b
#define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP6_DP_SEC_PACKET_CNTL 0x1f4c
#define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP6_DP_MSE_RATE_CNTL 0x1f4d
#define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP6_DP_MSE_RATE_UPDATE 0x1f4f
#define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP6_DP_MSE_SAT0 0x1f50
#define mmDP6_DP_MSE_SAT0_BASE_IDX 2
#define mmDP6_DP_MSE_SAT1 0x1f51
#define mmDP6_DP_MSE_SAT1_BASE_IDX 2
#define mmDP6_DP_MSE_SAT2 0x1f52
#define mmDP6_DP_MSE_SAT2_BASE_IDX 2
#define mmDP6_DP_MSE_SAT_UPDATE 0x1f53
#define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP6_DP_MSE_LINK_TIMING 0x1f54
#define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP6_DP_MSE_MISC_CNTL 0x1f55
#define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x1f5a
#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x1f5b
#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP6_DP_MSE_SAT0_STATUS 0x1f5d
#define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP6_DP_MSE_SAT1_STATUS 0x1f5e
#define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP6_DP_MSE_SAT2_STATUS 0x1f5f
#define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcio_uniphy0_dispdec
// base address: 0x0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x213e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x213f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x2140
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x2141
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x2142
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x2143
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x2144
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x2145
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2146
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2147
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2148
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2149
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x214a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x214b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x214c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x214d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x214e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x214f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x2150
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x2151
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x2152
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x2153
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x2154
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x2155
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2156
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2157
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2158
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2159
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x215a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x215b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x215c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x215d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x215e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x215f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x2160
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x2161
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x2162
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x2163
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x2164
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x2165
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2166
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2167
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2168
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2169
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x216a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x216b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x216c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x216d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x216e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x216f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x2170
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x2171
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x2172
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x2173
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x2174
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x2175
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2176
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2177
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2178
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2179
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x217a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x217b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x217c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x217d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x217e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x217f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x2180
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x2181
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x2182
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x2183
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x2184
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x2185
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2186
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2187
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2188
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2189
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x218a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x218b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x218c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x218d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x218e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x218f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x2190
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x2191
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x2192
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x2193
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x2194
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x2195
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2196
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2197
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2198
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2199
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x219a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x219b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x219c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x219d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x219e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x219f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x21a0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x21a1
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x21a2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x21a3
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x21a4
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x21a5
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x21a6
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x21a7
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x21a8
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x21a9
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x21aa
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x21ab
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x21ac
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x21ad
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x21ae
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x21af
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x21b0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x21b1
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x21b2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x21b3
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x21b4
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x21b5
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x21b6
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x21b7
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x21b8
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x21b9
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x21ba
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x21bb
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x21bc
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x21bd
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x21be
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x21bf
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x21c0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x21c1
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x21c2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x21c3
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x21c4
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x21c5
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x21c6
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x21c7
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x21c8
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x21c9
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x21ca
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x21cb
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x21cc
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x21cd
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x21ce
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x21cf
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x21d0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x21d1
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x21d2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x21d3
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x21d4
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x21d5
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x21d6
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x21d7
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x21d8
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x21d9
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x21da
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x21db
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x21dc
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x21dd
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_dc_combophycmregs0_dispdec
// base address: 0x0
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x213e
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x213f
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x2140
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x2141
#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x2142
#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x2143
#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x2144
#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x2145
#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2146
#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2147
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2148
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2149
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x214a
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x214b
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x214c
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x214d
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_dc_combophytxregs0_dispdec
// base address: 0x0
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x215e
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x215f
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2160
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x2161
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x2162
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x2163
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x2164
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x2165
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2166
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2167
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2168
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2169
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x216a
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x216b
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x216c
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x216d
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x216e
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x216f
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2170
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x2171
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x2172
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x2173
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x2174
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x2175
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2176
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2177
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2178
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2179
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x217a
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x217b
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x217c
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x217d
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x217e
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x217f
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2180
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x2181
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x2182
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x2183
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x2184
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x2185
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2186
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2187
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2188
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2189
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x218a
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x218b
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x218c
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x218d
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x218e
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x218f
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2190
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x2191
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x2192
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x2193
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x2194
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x2195
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2196
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2197
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2198
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2199
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x219a
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x219b
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x219c
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x219d
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_dc_combophypllregs0_dispdec
// base address: 0x0
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x219e
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x219f
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x21a0
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x21a1
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x21a2
#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x21a3
#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x21a4
#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x21a5
#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x21a7
#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x21a8
#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x21a9
#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x21aa
#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2
// addressBlock: dce_dc_dcio_uniphy1_dispdec
// base address: 0x320
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2206
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2207
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2208
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2209
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x220a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x220b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x220c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x220d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x220e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x220f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2210
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2211
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2212
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2213
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2214
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2215
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2216
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2217
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2218
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2219
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x221a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x221b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x221c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x221d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x221e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x221f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2220
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2221
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2222
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2223
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2224
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2225
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2226
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2227
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2228
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2229
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x222a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x222b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x222c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x222d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x222e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x222f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2230
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2231
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2232
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2233
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2234
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2235
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2236
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2237
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2238
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2239
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x223a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x223b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x223c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x223d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x223e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x223f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2240
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2241
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2242
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2243
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2244
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2245
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2246
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2247
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2248
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2249
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x224a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x224b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x224c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x224d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x224e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x224f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2250
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2251
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2252
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2253
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2254
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2255
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2256
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2257
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2258
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2259
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x225a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x225b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x225c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x225d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x225e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x225f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2260
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2261
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2262
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2263
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2264
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2265
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2266
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2267
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2268
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2269
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x226a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x226b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x226c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x226d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x226e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x226f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2270
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2271
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2272
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2273
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2274
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2275
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2276
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2277
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2278
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2279
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x227a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x227b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x227c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x227d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x227e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x227f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2280
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2281
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2282
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2283
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2284
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2285
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2286
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2287
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2288
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2289
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x228a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x228b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x228c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x228d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x228e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x228f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2290
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2291
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2292
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2293
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2294
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2295
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2296
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2297
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2298
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2299
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x229a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x229b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x229c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x229d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x229e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x229f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x22a0
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x22a1
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x22a2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x22a3
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x22a4
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x22a5
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_dc_combophycmregs1_dispdec
// base address: 0x320
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2206
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2207
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2208
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2209
#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x220a
#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x220b
#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x220c
#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x220d
#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x220e
#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x220f
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2210
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2211
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2212
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2213
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2214
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2215
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_dc_combophytxregs1_dispdec
// base address: 0x320
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2226
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2227
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2228
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2229
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x222a
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x222b
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x222c
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x222d
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x222e
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x222f
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2230
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2231
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2232
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2233
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2234
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2235
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2236
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2237
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2238
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2239
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x223a
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x223b
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x223c
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x223d
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x223e
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x223f
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2240
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2241
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2242
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2243
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2244
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2245
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2246
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2247
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2248
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2249
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x224a
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x224b
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x224c
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x224d
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x224e
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x224f
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2250
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2251
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2252
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2253
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2254
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2255
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2256
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2257
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2258
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2259
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x225a
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x225b
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x225c
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x225d
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x225e
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x225f
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2260
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2261
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2262
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2263
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2264
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2265
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_dc_combophypllregs1_dispdec
// base address: 0x320
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2266
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2267
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2268
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2269
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x226a
#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x226b
#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x226c
#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x226d
#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x226f
#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2270
#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2271
#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2272
#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2
// addressBlock: dce_dc_dcio_uniphy2_dispdec
// base address: 0x640
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x22ce
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x22cf
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x22d0
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x22d1
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x22d2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x22d3
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x22d4
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x22d5
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x22d6
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x22d7
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x22d8
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x22d9
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x22da
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x22db
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x22dc
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x22dd
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x22de
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x22df
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x22e0
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x22e1
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x22e2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x22e3
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x22e4
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x22e5
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x22e6
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x22e7
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x22e8
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x22e9
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x22ea
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x22eb
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x22ec
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x22ed
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x22ee
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x22ef
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x22f0
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x22f1
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x22f2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x22f3
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x22f4
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x22f5
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x22f6
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x22f7
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x22f8
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x22f9
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x22fa
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x22fb
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x22fc
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x22fd
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x22fe
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x22ff
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2300
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2301
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2302
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2303
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2304
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2305
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2306
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2307
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2308
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2309
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x230a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x230b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x230c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x230d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x230e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x230f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2310
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2311
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2312
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2313
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2314
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2315
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2316
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2317
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2318
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2319
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x231a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x231b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x231c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x231d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x231e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x231f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2320
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2321
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2322
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2323
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2324
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2325
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2326
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2327
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2328
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2329
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x232a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x232b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x232c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x232d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x232e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x232f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2330
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2331
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2332
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2333
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2334
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2335
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2336
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2337
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2338
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2339
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x233a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x233b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x233c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x233d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x233e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x233f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2340
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2341
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2342
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2343
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2344
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2345
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2346
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2347
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2348
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2349
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x234a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x234b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x234c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x234d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x234e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x234f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2350
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2351
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2352
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2353
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2354
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2355
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2356
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2357
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2358
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2359
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x235a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x235b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x235c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x235d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x235e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x235f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2360
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2361
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2362
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2363
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2364
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2365
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2366
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2367
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2368
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2369
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x236a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x236b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x236c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x236d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_dc_combophycmregs2_dispdec
// base address: 0x640
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x22ce
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x22cf
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x22d0
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x22d1
#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x22d2
#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x22d3
#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x22d4
#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x22d5
#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x22d6
#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x22d7
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x22d8
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x22d9
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x22da
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x22db
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x22dc
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x22dd
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_dc_combophytxregs2_dispdec
// base address: 0x640
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x22ee
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x22ef
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x22f0
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x22f1
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x22f2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x22f3
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x22f4
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x22f5
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x22f6
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x22f7
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x22f8
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x22f9
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x22fa
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x22fb
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x22fc
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x22fd
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x22fe
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x22ff
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2300
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2301
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2302
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2303
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2304
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2305
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2306
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2307
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2308
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2309
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x230a
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x230b
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x230c
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x230d
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x230e
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x230f
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2310
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2311
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2312
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2313
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2314
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2315
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2316
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2317
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2318
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2319
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x231a
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x231b
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x231c
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x231d
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x231e
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x231f
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2320
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2321
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2322
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2323
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2324
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2325
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2326
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2327
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2328
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2329
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x232a
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x232b
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x232c
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x232d
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_dc_combophypllregs2_dispdec
// base address: 0x640
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x232e
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x232f
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2330
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2331
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2332
#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2333
#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2334
#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2335
#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2337
#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2338
#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2339
#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x233a
#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2
// addressBlock: dce_dc_dcio_uniphy3_dispdec
// base address: 0x960
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2396
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2397
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2398
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2399
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x239a
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x239b
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x239c
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x239d
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x239e
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x239f
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x23a0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x23a1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x23a2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x23a3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x23a4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x23a5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x23a6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x23a7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x23a8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x23a9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x23aa
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x23ab
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x23ac
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x23ad
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x23ae
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x23af
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x23b0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x23b1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x23b2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x23b3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x23b4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x23b5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x23b6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x23b7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x23b8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x23b9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x23ba
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x23bb
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x23bc
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x23bd
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x23be
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x23bf
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x23c0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x23c1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x23c2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x23c3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x23c4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x23c5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x23c6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x23c7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x23c8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x23c9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x23ca
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x23cb
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x23cc
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x23cd
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x23ce
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x23cf
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x23d0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x23d1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x23d2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x23d3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x23d4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x23d5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x23d6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x23d7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x23d8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x23d9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x23da
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x23db
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x23dc
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x23dd
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x23de
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x23df
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x23e0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x23e1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x23e2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x23e3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x23e4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x23e5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x23e6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x23e7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x23e8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x23e9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x23ea
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x23eb
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x23ec
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x23ed
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x23ee
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x23ef
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x23f0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x23f1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x23f2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x23f3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x23f4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x23f5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x23f6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x23f7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x23f8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x23f9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x23fa
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x23fb
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x23fc
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x23fd
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x23fe
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x23ff
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2400
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2401
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2402
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2403
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2404
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2405
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2406
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2407
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2408
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2409
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x240a
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x240b
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x240c
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x240d
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x240e
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x240f
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2410
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2411
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2412
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2413
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2414
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2415
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2416
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2417
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2418
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2419
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x241a
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x241b
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x241c
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x241d
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x241e
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x241f
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2420
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2421
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2422
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2423
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2424
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2425
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2426
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2427
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2428
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2429
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x242a
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x242b
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x242c
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x242d
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x242e
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x242f
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2430
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2431
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2432
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2433
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2434
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2435
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_dc_combophycmregs3_dispdec
// base address: 0x960
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2396
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2397
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2398
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2399
#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x239a
#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x239b
#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x239c
#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x239d
#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x239e
#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x239f
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x23a0
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x23a1
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x23a2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x23a3
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x23a4
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x23a5
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_dc_combophytxregs3_dispdec
// base address: 0x960
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x23b6
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x23b7
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x23b8
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x23b9
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x23ba
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x23bb
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x23bc
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x23bd
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x23be
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x23bf
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x23c0
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x23c1
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x23c2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x23c3
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x23c4
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x23c5
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x23c6
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x23c7
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x23c8
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x23c9
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x23ca
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x23cb
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x23cc
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x23cd
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x23ce
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x23cf
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x23d0
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x23d1
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x23d2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x23d3
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x23d4
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x23d5
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x23d6
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x23d7
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x23d8
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x23d9
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x23da
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x23db
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x23dc
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x23dd
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x23de
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x23df
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x23e0
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x23e1
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x23e2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x23e3
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x23e4
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x23e5
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x23e6
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x23e7
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x23e8
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x23e9
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x23ea
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x23eb
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x23ec
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x23ed
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x23ee
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x23ef
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x23f0
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x23f1
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x23f2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x23f3
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x23f4
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x23f5
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_dc_combophypllregs3_dispdec
// base address: 0x960
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x23f6
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x23f7
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x23f8
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x23f9
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x23fa
#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x23fb
#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x23fc
#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x23fd
#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x23ff
#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2400
#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2401
#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2402
#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2
// addressBlock: dce_dc_dcio_uniphy4_dispdec
// base address: 0xc80
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x245e
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x245f
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2460
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2461
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2462
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2463
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2464
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2465
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2466
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2467
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2468
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2469
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x246a
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x246b
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x246c
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x246d
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x246e
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x246f
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2470
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2471
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2472
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2473
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2474
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2475
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2476
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2477
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2478
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2479
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x247a
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x247b
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x247c
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x247d
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x247e
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x247f
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2480
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2481
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2482
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2483
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2484
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2485
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2486
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2487
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2488
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2489
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x248a
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x248b
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x248c
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x248d
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x248e
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x248f
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2490
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2491
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2492
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2493
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2494
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2495
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2496
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2497
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 0x2498
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 0x2499
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 0x249a
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 0x249b
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 0x249c
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 0x249d
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 0x249e
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 0x249f
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 0x24a0
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 0x24a1
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 0x24a2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 0x24a3
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 0x24a4
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 0x24a5
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 0x24a6
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 0x24a7
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 0x24a8
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 0x24a9
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 0x24aa
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 0x24ab
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 0x24ac
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 0x24ad
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 0x24ae
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 0x24af
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 0x24b0
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 0x24b1
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 0x24b2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 0x24b3
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 0x24b4
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 0x24b5
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 0x24b6
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 0x24b7
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 0x24b8
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 0x24b9
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 0x24ba
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 0x24bb
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 0x24bc
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 0x24bd
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 0x24be
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 0x24bf
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 0x24c0
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 0x24c1
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 0x24c2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 0x24c3
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 0x24c4
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 0x24c5
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 0x24c6
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 0x24c7
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 0x24c8
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 0x24c9
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 0x24ca
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 0x24cb
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 0x24cc
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 0x24cd
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 0x24ce
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 0x24cf
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 0x24d0
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 0x24d1
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 0x24d2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 0x24d3
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 0x24d4
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 0x24d5
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 0x24d6
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 0x24d7
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 0x24d8
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 0x24d9
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 0x24da
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 0x24db
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 0x24dc
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 0x24dd
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 0x24de
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 0x24df
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 0x24e0
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 0x24e1
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 0x24e2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 0x24e3
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 0x24e4
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 0x24e5
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 0x24e6
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 0x24e7
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 0x24e8
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 0x24e9
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 0x24ea
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 0x24eb
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 0x24ec
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 0x24ed
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 0x24ee
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 0x24ef
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 0x24f0
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 0x24f1
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 0x24f2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 0x24f3
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 0x24f4
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 0x24f5
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 0x24f6
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 0x24f7
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 0x24f8
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 0x24f9
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 0x24fa
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 0x24fb
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 0x24fc
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 0x24fd
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_dc_combophycmregs4_dispdec
// base address: 0xc80
#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1 0x245e
#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2 0x245f
#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3 0x2460
#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM 0x2461
#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT 0x2462
#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL 0x2463
#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP 0x2464
#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS 0x2465
#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL 0x2466
#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 0x2467
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 0x2468
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 0x2469
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 0x246a
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 0x246b
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 0x246c
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 0x246d
#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_dc_combophytxregs4_dispdec
// base address: 0xc80
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 0x247e
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 0x247f
#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2480
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 0x2481
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 0x2482
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 0x2483
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 0x2484
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 0x2485
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 0x2486
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 0x2487
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 0x2488
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 0x2489
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 0x248a
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 0x248b
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 0x248c
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 0x248d
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 0x248e
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 0x248f
#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2490
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 0x2491
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 0x2492
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 0x2493
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 0x2494
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 0x2495
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 0x2496
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 0x2497
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 0x2498
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 0x2499
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 0x249a
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 0x249b
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 0x249c
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 0x249d
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 0x249e
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 0x249f
#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x24a0
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 0x24a1
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 0x24a2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 0x24a3
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 0x24a4
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 0x24a5
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 0x24a6
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 0x24a7
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 0x24a8
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 0x24a9
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 0x24aa
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 0x24ab
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 0x24ac
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 0x24ad
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 0x24ae
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 0x24af
#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x24b0
#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 0x24b1
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 0x24b2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 0x24b3
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 0x24b4
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 0x24b5
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 0x24b6
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 0x24b7
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 0x24b8
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 0x24b9
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 0x24ba
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 0x24bb
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 0x24bc
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 0x24bd
#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_dc_combophypllregs4_dispdec
// base address: 0xc80
#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 0x24be
#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 0x24bf
#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 0x24c0
#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 0x24c1
#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE 0x24c2
#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE 0x24c3
#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL 0x24c4
#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL 0x24c5
#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_VREG_CFG 0x24c7
#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_OBSERVE0 0x24c8
#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_OBSERVE1 0x24c9
#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS4_DFT_OUT 0x24ca
#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_BASE_IDX 2
// addressBlock: dce_dc_dcio_uniphy5_dispdec
// base address: 0xfa0
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2526
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2527
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2528
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2529
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x252a
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x252b
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x252c
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x252d
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x252e
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x252f
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2530
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2531
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2532
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2533
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2534
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2535
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2536
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2537
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2538
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2539
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x253a
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x253b
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x253c
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x253d
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x253e
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x253f
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2540
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2541
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2542
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2543
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2544
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2545
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2546
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2547
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2548
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2549
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x254a
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x254b
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x254c
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x254d
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x254e
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x254f
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2550
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2551
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2552
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2553
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2554
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2555
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0x2556
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0x2557
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0x2558
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0x2559
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0x255a
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0x255b
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0x255c
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0x255d
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0x255e
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0x255f
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 0x2560
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 0x2561
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 0x2562
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 0x2563
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 0x2564
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 0x2565
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 0x2566
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 0x2567
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 0x2568
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 0x2569
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 0x256a
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 0x256b
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 0x256c
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 0x256d
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 0x256e
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 0x256f
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 0x2570
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 0x2571
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 0x2572
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 0x2573
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 0x2574
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 0x2575
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 0x2576
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 0x2577
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 0x2578
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 0x2579
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 0x257a
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 0x257b
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 0x257c
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 0x257d
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 0x257e
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 0x257f
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 0x2580
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 0x2581
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 0x2582
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 0x2583
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 0x2584
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 0x2585
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 0x2586
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 0x2587
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 0x2588
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 0x2589
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 0x258a
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 0x258b
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 0x258c
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 0x258d
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 0x258e
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 0x258f
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 0x2590
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 0x2591
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 0x2592
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 0x2593
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 0x2594
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 0x2595
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 0x2596
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 0x2597
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 0x2598
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 0x2599
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 0x259a
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 0x259b
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 0x259c
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 0x259d
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 0x259e
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 0x259f
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 0x25a0
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 0x25a1
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 0x25a2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 0x25a3
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 0x25a4
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 0x25a5
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 0x25a6
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 0x25a7
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 0x25a8
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 0x25a9
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 0x25aa
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 0x25ab
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 0x25ac
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 0x25ad
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 0x25ae
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 0x25af
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 0x25b0
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 0x25b1
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 0x25b2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 0x25b3
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 0x25b4
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 0x25b5
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 0x25b6
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 0x25b7
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 0x25b8
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 0x25b9
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 0x25ba
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 0x25bb
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 0x25bc
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 0x25bd
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 0x25be
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 0x25bf
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 0x25c0
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 0x25c1
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 0x25c2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 0x25c3
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 0x25c4
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 0x25c5
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_dc_combophycmregs5_dispdec
// base address: 0xfa0
#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1 0x2526
#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2 0x2527
#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3 0x2528
#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM 0x2529
#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT 0x252a
#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL 0x252b
#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP 0x252c
#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS 0x252d
#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL 0x252e
#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 0x252f
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 0x2530
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 0x2531
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 0x2532
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 0x2533
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 0x2534
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 0x2535
#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_dc_combophytxregs5_dispdec
// base address: 0xfa0
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 0x2546
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 0x2547
#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2548
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 0x2549
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 0x254a
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 0x254b
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 0x254c
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 0x254d
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 0x254e
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 0x254f
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 0x2550
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 0x2551
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 0x2552
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 0x2553
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 0x2554
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 0x2555
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 0x2556
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 0x2557
#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2558
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 0x2559
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 0x255a
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 0x255b
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 0x255c
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 0x255d
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 0x255e
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 0x255f
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 0x2560
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 0x2561
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 0x2562
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 0x2563
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 0x2564
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 0x2565
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 0x2566
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 0x2567
#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2568
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 0x2569
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 0x256a
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 0x256b
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 0x256c
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 0x256d
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 0x256e
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 0x256f
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 0x2570
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 0x2571
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 0x2572
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 0x2573
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 0x2574
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 0x2575
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 0x2576
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 0x2577
#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2578
#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 0x2579
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 0x257a
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 0x257b
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 0x257c
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 0x257d
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 0x257e
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 0x257f
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 0x2580
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 0x2581
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 0x2582
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 0x2583
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 0x2584
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 0x2585
#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_dc_combophypllregs5_dispdec
// base address: 0xfa0
#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 0x2586
#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 0x2587
#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 0x2588
#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 0x2589
#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE 0x258a
#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE 0x258b
#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL 0x258c
#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL 0x258d
#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_VREG_CFG 0x258f
#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_OBSERVE0 0x2590
#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_OBSERVE1 0x2591
#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS5_DFT_OUT 0x2592
#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_BASE_IDX 2
// addressBlock: dce_dc_dcio_uniphy6_dispdec
// base address: 0x12c0
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x25ee
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x25ef
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x25f0
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x25f1
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x25f2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x25f3
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x25f4
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x25f5
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x25f6
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x25f7
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x25f8
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x25f9
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x25fa
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x25fb
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x25fc
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x25fd
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x25fe
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x25ff
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x2600
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x2601
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x2602
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x2603
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x2604
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x2605
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x2606
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x2607
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x2608
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x2609
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x260a
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x260b
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x260c
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x260d
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x260e
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x260f
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x2610
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x2611
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x2612
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x2613
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x2614
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x2615
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x2616
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x2617
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x2618
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x2619
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x261a
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x261b
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x261c
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x261d
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 0x261e
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 0x261f
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 0x2620
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 0x2621
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 0x2622
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 0x2623
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 0x2624
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 0x2625
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 0x2626
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 0x2627
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58 0x2628
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59 0x2629
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60 0x262a
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61 0x262b
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62 0x262c
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63 0x262d
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64 0x262e
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65 0x262f
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66 0x2630
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67 0x2631
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68 0x2632
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69 0x2633
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70 0x2634
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71 0x2635
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72 0x2636
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73 0x2637
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74 0x2638
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75 0x2639
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76 0x263a
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77 0x263b
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78 0x263c
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79 0x263d
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80 0x263e
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81 0x263f
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82 0x2640
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83 0x2641
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84 0x2642
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85 0x2643
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86 0x2644
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87 0x2645
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88 0x2646
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89 0x2647
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90 0x2648
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91 0x2649
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92 0x264a
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93 0x264b
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94 0x264c
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95 0x264d
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96 0x264e
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97 0x264f
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98 0x2650
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99 0x2651
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100 0x2652
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101 0x2653
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102 0x2654
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103 0x2655
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104 0x2656
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105 0x2657
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106 0x2658
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107 0x2659
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108 0x265a
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109 0x265b
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110 0x265c
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111 0x265d
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112 0x265e
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113 0x265f
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114 0x2660
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115 0x2661
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116 0x2662
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117 0x2663
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118 0x2664
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119 0x2665
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120 0x2666
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121 0x2667
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122 0x2668
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123 0x2669
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124 0x266a
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125 0x266b
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126 0x266c
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127 0x266d
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128 0x266e
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129 0x266f
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130 0x2670
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131 0x2671
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132 0x2672
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133 0x2673
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134 0x2674
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135 0x2675
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136 0x2676
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137 0x2677
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138 0x2678
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139 0x2679
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140 0x267a
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141 0x267b
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142 0x267c
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143 0x267d
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144 0x267e
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145 0x267f
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146 0x2680
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147 0x2681
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148 0x2682
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149 0x2683
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150 0x2684
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151 0x2685
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152 0x2686
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153 0x2687
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154 0x2688
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155 0x2689
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156 0x268a
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157 0x268b
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158 0x268c
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159 0x268d
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_dc_combophycmregs6_dispdec
// base address: 0x12c0
#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1 0x25ee
#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2 0x25ef
#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3 0x25f0
#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM 0x25f1
#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT 0x25f2
#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL 0x25f3
#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP 0x25f4
#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS 0x25f5
#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL 0x25f6
#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1 0x25f7
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2 0x25f8
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3 0x25f9
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4 0x25fa
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5 0x25fb
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6 0x25fc
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7 0x25fd
#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_dc_combophytxregs6_dispdec
// base address: 0x12c0
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0 0x260e
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0 0x260f
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2610
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0 0x2611
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0 0x2612
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0 0x2613
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0 0x2614
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0 0x2615
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0 0x2616
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0 0x2617
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0 0x2618
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0 0x2619
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0 0x261a
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0 0x261b
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0 0x261c
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0 0x261d
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1 0x261e
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1 0x261f
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2620
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1 0x2621
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1 0x2622
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1 0x2623
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1 0x2624
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1 0x2625
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1 0x2626
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1 0x2627
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1 0x2628
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1 0x2629
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1 0x262a
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1 0x262b
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1 0x262c
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1 0x262d
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2 0x262e
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2 0x262f
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2630
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2 0x2631
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2 0x2632
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2 0x2633
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2 0x2634
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2 0x2635
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2 0x2636
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2 0x2637
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2 0x2638
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2 0x2639
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2 0x263a
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2 0x263b
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2 0x263c
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2 0x263d
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3 0x263e
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3 0x263f
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2640
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3 0x2641
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3 0x2642
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3 0x2643
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3 0x2644
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3 0x2645
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3 0x2646
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3 0x2647
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3 0x2648
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3 0x2649
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3 0x264a
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3 0x264b
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3 0x264c
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3 0x264d
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_dc_combophypllregs6_dispdec
// base address: 0x12c0
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0 0x264e
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1 0x264f
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2 0x2650
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3 0x2651
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE 0x2652
#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE 0x2653
#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL 0x2654
#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL 0x2655
#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_VREG_CFG 0x2657
#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_OBSERVE0 0x2658
#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_OBSERVE1 0x2659
#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS6_DFT_OUT 0x265a
#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_BASE_IDX 2
// addressBlock: dce_dc_dcio_uniphy8_dispdec
// base address: 0x15e0
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x26b6
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x26b7
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x26b8
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x26b9
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x26ba
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x26bb
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x26bc
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x26bd
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x26be
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x26bf
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x26c0
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x26c1
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x26c2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x26c3
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x26c4
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x26c5
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x26c6
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x26c7
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x26c8
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x26c9
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x26ca
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x26cb
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x26cc
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x26cd
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x26ce
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x26cf
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x26d0
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x26d1
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x26d2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x26d3
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x26d4
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x26d5
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32 0x26d6
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33 0x26d7
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34 0x26d8
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35 0x26d9
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36 0x26da
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37 0x26db
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38 0x26dc
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39 0x26dd
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40 0x26de
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41 0x26df
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42 0x26e0
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43 0x26e1
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44 0x26e2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45 0x26e3
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46 0x26e4
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47 0x26e5
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48 0x26e6
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49 0x26e7
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50 0x26e8
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51 0x26e9
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52 0x26ea
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53 0x26eb
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54 0x26ec
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55 0x26ed
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56 0x26ee
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57 0x26ef
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58 0x26f0
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59 0x26f1
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60 0x26f2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61 0x26f3
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62 0x26f4
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63 0x26f5
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64 0x26f6
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65 0x26f7
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66 0x26f8
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67 0x26f9
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68 0x26fa
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69 0x26fb
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70 0x26fc
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71 0x26fd
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72 0x26fe
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73 0x26ff
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74 0x2700
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75 0x2701
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76 0x2702
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77 0x2703
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78 0x2704
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79 0x2705
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80 0x2706
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81 0x2707
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82 0x2708
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83 0x2709
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84 0x270a
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85 0x270b
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86 0x270c
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87 0x270d
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88 0x270e
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89 0x270f
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90 0x2710
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91 0x2711
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92 0x2712
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93 0x2713
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94 0x2714
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95 0x2715
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96 0x2716
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97 0x2717
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98 0x2718
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99 0x2719
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100 0x271a
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101 0x271b
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102 0x271c
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103 0x271d
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104 0x271e
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105 0x271f
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106 0x2720
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107 0x2721
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108 0x2722
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109 0x2723
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110 0x2724
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111 0x2725
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112 0x2726
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113 0x2727
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114 0x2728
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115 0x2729
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116 0x272a
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117 0x272b
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118 0x272c
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119 0x272d
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120 0x272e
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121 0x272f
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122 0x2730
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123 0x2731
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124 0x2732
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125 0x2733
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126 0x2734
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127 0x2735
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128 0x2736
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129 0x2737
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130 0x2738
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131 0x2739
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132 0x273a
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133 0x273b
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134 0x273c
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135 0x273d
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136 0x273e
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137 0x273f
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138 0x2740
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139 0x2741
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140 0x2742
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141 0x2743
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142 0x2744
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143 0x2745
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144 0x2746
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145 0x2747
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146 0x2748
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147 0x2749
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148 0x274a
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149 0x274b
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150 0x274c
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151 0x274d
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152 0x274e
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153 0x274f
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154 0x2750
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155 0x2751
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156 0x2752
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157 0x2753
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158 0x2754
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159 0x2755
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_dc_combophycmregs8_dispdec
// base address: 0x15e0
#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1 0x26b6
#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2 0x26b7
#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3 0x26b8
#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM 0x26b9
#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT 0x26ba
#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL 0x26bb
#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP 0x26bc
#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS 0x26bd
#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL 0x26be
#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1 0x26bf
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2 0x26c0
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3 0x26c1
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4 0x26c2
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5 0x26c3
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6 0x26c4
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7 0x26c5
#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_dc_combophytxregs8_dispdec
// base address: 0x15e0
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0 0x26d6
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0 0x26d7
#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x26d8
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0 0x26d9
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0 0x26da
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0 0x26db
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0 0x26dc
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0 0x26dd
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0 0x26de
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0 0x26df
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0 0x26e0
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0 0x26e1
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0 0x26e2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0 0x26e3
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0 0x26e4
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0 0x26e5
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1 0x26e6
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1 0x26e7
#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x26e8
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1 0x26e9
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1 0x26ea
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1 0x26eb
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1 0x26ec
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1 0x26ed
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1 0x26ee
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1 0x26ef
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1 0x26f0
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1 0x26f1
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1 0x26f2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1 0x26f3
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1 0x26f4
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1 0x26f5
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2 0x26f6
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2 0x26f7
#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x26f8
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2 0x26f9
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2 0x26fa
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2 0x26fb
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2 0x26fc
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2 0x26fd
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2 0x26fe
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2 0x26ff
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2 0x2700
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2 0x2701
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2 0x2702
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2 0x2703
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2 0x2704
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2 0x2705
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3 0x2706
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3 0x2707
#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2708
#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3 0x2709
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3 0x270a
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3 0x270b
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3 0x270c
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3 0x270d
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3 0x270e
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3 0x270f
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3 0x2710
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3 0x2711
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3 0x2712
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3 0x2713
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3 0x2714
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3 0x2715
#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_dc_combophypllregs8_dispdec
// base address: 0x15e0
#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0 0x2716
#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1 0x2717
#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2 0x2718
#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3 0x2719
#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE 0x271a
#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE 0x271b
#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL 0x271c
#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL 0x271d
#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_VREG_CFG 0x271f
#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_OBSERVE0 0x2720
#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_OBSERVE1 0x2721
#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS8_DFT_OUT 0x2722
#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_BASE_IDX 2
// addressBlock: dce_dc_dsi0_dispdec
// base address: 0x0
#define mmDSI0_DISP_DSI_CTRL 0x27be
#define mmDSI0_DISP_DSI_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_STATUS 0x27bf
#define mmDSI0_DISP_DSI_STATUS_BASE_IDX 2
#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL 0x27c0
#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x27c1
#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2
#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x27c2
#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2
#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x27c3
#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2
#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x27c4
#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2
#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x27c5
#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2
#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x27c6
#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL 0x27c7
#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x27c8
#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x27c9
#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET 0x27ca
#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2
#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH 0x27cb
#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2
#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0 0x27cc
#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2
#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1 0x27cd
#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2
#define mmDSI0_DISP_DSI_DMA_DATA_PITCH 0x27ce
#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2
#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH 0x27cf
#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2
#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT 0x27d0
#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2
#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL 0x27d1
#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA 0x27d2
#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2
#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH 0x27d3
#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2
#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT 0x27d4
#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2
#define mmDSI0_DISP_DSI_RDBK_DATA0 0x27d5
#define mmDSI0_DISP_DSI_RDBK_DATA0_BASE_IDX 2
#define mmDSI0_DISP_DSI_RDBK_DATA1 0x27d6
#define mmDSI0_DISP_DSI_RDBK_DATA1_BASE_IDX 2
#define mmDSI0_DISP_DSI_RDBK_DATA2 0x27d7
#define mmDSI0_DISP_DSI_RDBK_DATA2_BASE_IDX 2
#define mmDSI0_DISP_DSI_RDBK_DATA3 0x27d8
#define mmDSI0_DISP_DSI_RDBK_DATA3_BASE_IDX 2
#define mmDSI0_DISP_DSI_RDBK_DATATYPE0 0x27d9
#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2
#define mmDSI0_DISP_DSI_RDBK_DATATYPE1 0x27da
#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2
#define mmDSI0_DISP_DSI_TRIG_CTRL 0x27db
#define mmDSI0_DISP_DSI_TRIG_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_EXT_MUX 0x27dc
#define mmDSI0_DISP_DSI_EXT_MUX_BASE_IDX 2
#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x27dd
#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x27de
#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2
#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x27df
#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2
#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x27e0
#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2
#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER 0x27e1
#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2
#define mmDSI0_DISP_DSI_EXT_RESET 0x27e2
#define mmDSI0_DISP_DSI_EXT_RESET_BASE_IDX 2
#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE 0x27e3
#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2
#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE 0x27e4
#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2
#define mmDSI0_DISP_DSI_LANE_CRC_CTRL 0x27e5
#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL 0x27e6
#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_LANE_CTRL 0x27e7
#define mmDSI0_DISP_DSI_LANE_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR 0x27e8
#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2
#define mmDSI0_DISP_DSI_LP_TIMER_CTRL 0x27e9
#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_HS_TIMER_CTRL 0x27ea
#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_TIMEOUT_STATUS 0x27eb
#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2
#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL 0x27ec
#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x27ed
#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2
#define mmDSI0_DISP_DSI_EOT_PACKET 0x27ee
#define mmDSI0_DISP_DSI_EOT_PACKET_BASE_IDX 2
#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL 0x27ef
#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x27f0
#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2
#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL 0x27f1
#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x27f2
#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2
#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x27f3
#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2
#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x27f4
#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2
#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x27f5
#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT 0x27f6
#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2
#define mmDSI0_DISP_DSI_MIPI_BIST_START 0x27f7
#define mmDSI0_DISP_DSI_MIPI_BIST_START_BASE_IDX 2
#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS 0x27f8
#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2
#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK 0x27f9
#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2
#define mmDSI0_DISP_DSI_INTERRUPT_CTRL 0x27fa
#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_CLK_CTRL 0x27fb
#define mmDSI0_DISP_DSI_CLK_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_CLK_STATUS 0x27fc
#define mmDSI0_DISP_DSI_CLK_STATUS_BASE_IDX 2
#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS 0x27fd
#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2
#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL 0x27fe
#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_CMD_FIFO_DATA 0x27ff
#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2
#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL 0x2800
#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_TE_CTRL 0x2801
#define mmDSI0_DISP_DSI_TE_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_LANE_STATUS 0x2805
#define mmDSI0_DISP_DSI_LANE_STATUS_BASE_IDX 2
#define mmDSI0_DISP_DSI_PERF_CTRL 0x2806
#define mmDSI0_DISP_DSI_PERF_CTRL_BASE_IDX 2
#define mmDSI0_DISP_DSI_HSYNC_LENGTH 0x2807
#define mmDSI0_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2
#define mmDSI0_DISP_DSI_RDBK_NUM 0x2808
#define mmDSI0_DISP_DSI_RDBK_NUM_BASE_IDX 2
#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL 0x2809
#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dsi1_dispdec
// base address: 0x400
#define mmDSI1_DISP_DSI_CTRL 0x28be
#define mmDSI1_DISP_DSI_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_STATUS 0x28bf
#define mmDSI1_DISP_DSI_STATUS_BASE_IDX 2
#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL 0x28c0
#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x28c1
#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2
#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x28c2
#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2
#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x28c3
#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2
#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x28c4
#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2
#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x28c5
#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2
#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x28c6
#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL 0x28c7
#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x28c8
#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x28c9
#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET 0x28ca
#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2
#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH 0x28cb
#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2
#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0 0x28cc
#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2
#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1 0x28cd
#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2
#define mmDSI1_DISP_DSI_DMA_DATA_PITCH 0x28ce
#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2
#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH 0x28cf
#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2
#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT 0x28d0
#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2
#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL 0x28d1
#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA 0x28d2
#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2
#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH 0x28d3
#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2
#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT 0x28d4
#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2
#define mmDSI1_DISP_DSI_RDBK_DATA0 0x28d5
#define mmDSI1_DISP_DSI_RDBK_DATA0_BASE_IDX 2
#define mmDSI1_DISP_DSI_RDBK_DATA1 0x28d6
#define mmDSI1_DISP_DSI_RDBK_DATA1_BASE_IDX 2
#define mmDSI1_DISP_DSI_RDBK_DATA2 0x28d7
#define mmDSI1_DISP_DSI_RDBK_DATA2_BASE_IDX 2
#define mmDSI1_DISP_DSI_RDBK_DATA3 0x28d8
#define mmDSI1_DISP_DSI_RDBK_DATA3_BASE_IDX 2
#define mmDSI1_DISP_DSI_RDBK_DATATYPE0 0x28d9
#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2
#define mmDSI1_DISP_DSI_RDBK_DATATYPE1 0x28da
#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2
#define mmDSI1_DISP_DSI_TRIG_CTRL 0x28db
#define mmDSI1_DISP_DSI_TRIG_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_EXT_MUX 0x28dc
#define mmDSI1_DISP_DSI_EXT_MUX_BASE_IDX 2
#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x28dd
#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x28de
#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2
#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x28df
#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2
#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x28e0
#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2
#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER 0x28e1
#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2
#define mmDSI1_DISP_DSI_EXT_RESET 0x28e2
#define mmDSI1_DISP_DSI_EXT_RESET_BASE_IDX 2
#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE 0x28e3
#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2
#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE 0x28e4
#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2
#define mmDSI1_DISP_DSI_LANE_CRC_CTRL 0x28e5
#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL 0x28e6
#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_LANE_CTRL 0x28e7
#define mmDSI1_DISP_DSI_LANE_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR 0x28e8
#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2
#define mmDSI1_DISP_DSI_LP_TIMER_CTRL 0x28e9
#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_HS_TIMER_CTRL 0x28ea
#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_TIMEOUT_STATUS 0x28eb
#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2
#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL 0x28ec
#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x28ed
#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2
#define mmDSI1_DISP_DSI_EOT_PACKET 0x28ee
#define mmDSI1_DISP_DSI_EOT_PACKET_BASE_IDX 2
#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL 0x28ef
#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x28f0
#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2
#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL 0x28f1
#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x28f2
#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2
#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x28f3
#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2
#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x28f4
#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2
#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x28f5
#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT 0x28f6
#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2
#define mmDSI1_DISP_DSI_MIPI_BIST_START 0x28f7
#define mmDSI1_DISP_DSI_MIPI_BIST_START_BASE_IDX 2
#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS 0x28f8
#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2
#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK 0x28f9
#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2
#define mmDSI1_DISP_DSI_INTERRUPT_CTRL 0x28fa
#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_CLK_CTRL 0x28fb
#define mmDSI1_DISP_DSI_CLK_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_CLK_STATUS 0x28fc
#define mmDSI1_DISP_DSI_CLK_STATUS_BASE_IDX 2
#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS 0x28fd
#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2
#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL 0x28fe
#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_CMD_FIFO_DATA 0x28ff
#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2
#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL 0x2900
#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_TE_CTRL 0x2901
#define mmDSI1_DISP_DSI_TE_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_LANE_STATUS 0x2905
#define mmDSI1_DISP_DSI_LANE_STATUS_BASE_IDX 2
#define mmDSI1_DISP_DSI_PERF_CTRL 0x2906
#define mmDSI1_DISP_DSI_PERF_CTRL_BASE_IDX 2
#define mmDSI1_DISP_DSI_HSYNC_LENGTH 0x2907
#define mmDSI1_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2
#define mmDSI1_DISP_DSI_RDBK_NUM 0x2908
#define mmDSI1_DISP_DSI_RDBK_NUM_BASE_IDX 2
#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL 0x2909
#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dprx_sd0_dispdec
// base address: 0x0
#define mmDPRX_SD0_DPRX_SD_CONTROL 0x29be
#define mmDPRX_SD0_DPRX_SD_CONTROL_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE 0x29bf
#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSA0 0x29c0
#define mmDPRX_SD0_DPRX_SD_MSA0_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSA1 0x29c1
#define mmDPRX_SD0_DPRX_SD_MSA1_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSA2 0x29c2
#define mmDPRX_SD0_DPRX_SD_MSA2_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSA3 0x29c3
#define mmDPRX_SD0_DPRX_SD_MSA3_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSA4 0x29c4
#define mmDPRX_SD0_DPRX_SD_MSA4_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSA5 0x29c5
#define mmDPRX_SD0_DPRX_SD_MSA5_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSA6 0x29c6
#define mmDPRX_SD0_DPRX_SD_MSA6_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSA7 0x29c7
#define mmDPRX_SD0_DPRX_SD_MSA7_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSA8 0x29c8
#define mmDPRX_SD0_DPRX_SD_MSA8_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_VBID 0x29c9
#define mmDPRX_SD0_DPRX_SD_VBID_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE 0x29ca
#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x29cb
#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE 0x29cc
#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSE_SAT 0x29ce
#define mmDPRX_SD0_DPRX_SD_MSE_SAT_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE 0x29cf
#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE 0x29d0
#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_V_PARAMETER 0x29d1
#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT 0x29d2
#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS 0x29d3
#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x29d4
#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS 0x29d5
#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL 0x29d6
#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS 0x29d7
#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL 0x29d8
#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR 0x29d9
#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE 0x29da
#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x29db
#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED 0x29dc
#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR 0x29dd
#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR 0x29de
#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR 0x29df
#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x29e1
#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_SDP_STEER 0x29e3
#define mmDPRX_SD0_DPRX_SD_SDP_STEER_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS 0x29e4
#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL 0x29e5
#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_SDP_DATA 0x29e6
#define mmDPRX_SD0_DPRX_SD_SDP_DATA_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_SDP_ERROR 0x29e7
#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER 0x29e8
#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR 0x29e9
#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL 0x29ea
#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED 0x29eb
#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED 0x29ec
#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_BS_COUNTER 0x29ed
#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_BASE_IDX 2
#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED 0x29ee
#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2
// addressBlock: dce_dc_dprx_sd1_dispdec
// base address: 0x180
#define mmDPRX_SD1_DPRX_SD_CONTROL 0x2a1e
#define mmDPRX_SD1_DPRX_SD_CONTROL_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE 0x2a1f
#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSA0 0x2a20
#define mmDPRX_SD1_DPRX_SD_MSA0_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSA1 0x2a21
#define mmDPRX_SD1_DPRX_SD_MSA1_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSA2 0x2a22
#define mmDPRX_SD1_DPRX_SD_MSA2_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSA3 0x2a23
#define mmDPRX_SD1_DPRX_SD_MSA3_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSA4 0x2a24
#define mmDPRX_SD1_DPRX_SD_MSA4_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSA5 0x2a25
#define mmDPRX_SD1_DPRX_SD_MSA5_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSA6 0x2a26
#define mmDPRX_SD1_DPRX_SD_MSA6_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSA7 0x2a27
#define mmDPRX_SD1_DPRX_SD_MSA7_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSA8 0x2a28
#define mmDPRX_SD1_DPRX_SD_MSA8_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_VBID 0x2a29
#define mmDPRX_SD1_DPRX_SD_VBID_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE 0x2a2a
#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x2a2b
#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE 0x2a2c
#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSE_SAT 0x2a2e
#define mmDPRX_SD1_DPRX_SD_MSE_SAT_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE 0x2a2f
#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE 0x2a30
#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_V_PARAMETER 0x2a31
#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT 0x2a32
#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS 0x2a33
#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x2a34
#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS 0x2a35
#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL 0x2a36
#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS 0x2a37
#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL 0x2a38
#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR 0x2a39
#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE 0x2a3a
#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x2a3b
#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED 0x2a3c
#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR 0x2a3d
#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR 0x2a3e
#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR 0x2a3f
#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x2a41
#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_SDP_STEER 0x2a43
#define mmDPRX_SD1_DPRX_SD_SDP_STEER_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS 0x2a44
#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL 0x2a45
#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_SDP_DATA 0x2a46
#define mmDPRX_SD1_DPRX_SD_SDP_DATA_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_SDP_ERROR 0x2a47
#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER 0x2a48
#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR 0x2a49
#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL 0x2a4a
#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED 0x2a4b
#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED 0x2a4c
#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_BS_COUNTER 0x2a4d
#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_BASE_IDX 2
#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED 0x2a4e
#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon10_dispdec
// base address: 0xacf8
#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x2b5e
#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x2b5f
#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x2b60
#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CNTL 0x2b61
#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CNTL2 0x2b62
#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x2b63
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x2b64
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_HI 0x2b65
#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_LOW 0x2b66
#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dc_zcalregs_dispdec
// base address: 0x0
#define mmCOMP_EN_CTL 0x2d96
#define mmCOMP_EN_CTL_BASE_IDX 2
#define mmCOMP_EN_DFX 0x2d97
#define mmCOMP_EN_DFX_BASE_IDX 2
#define mmZCAL_FUSES 0x2d98
#define mmZCAL_FUSES_BASE_IDX 2
// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
// base address: 0x48
//#define mmVGA_dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
// base address: 0x4c
//#define mmVGA_dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
// addressBlock: dce_dc_dispdec[948..986]
// base address: 0x3b4
//#define mmVGA_CRTC8_IDX 0x002d
//#define mmVGA_CRTC8_DATA 0x002d
//#define mmVGA_GENFC_WT 0x002e
//#define mmVGA_GENS1 0x002e
//#define mmVGA_ATTRDW 0x0030
//#define mmVGA_ATTRX 0x0030
//#define mmVGA_ATTRDR 0x0030
//#define mmVGA_GENMO_WT 0x0030
//#define mmVGA_GENS0 0x0030
//#define mmVGA_GENENB 0x0030
//#define mmVGA_SEQ8_IDX 0x0031
//#define mmVGA_SEQ8_DATA 0x0031
//#define mmVGA_DAC_MASK 0x0031
//#define mmVGA_DAC_R_INDEX 0x0031
//#define mmVGA_DAC_W_INDEX 0x0032
//#define mmVGA_DAC_DATA 0x0032
//#define mmVGA_GENFC_RD 0x0032
//#define mmVGA_GENMO_RD 0x0033
//#define mmVGA_GRPH8_IDX 0x0033
//#define mmVGA_GRPH8_DATA 0x0033
//#define mmVGA_CRTC8_IDX_1 0x0035
//#define mmVGA_CRTC8_DATA_1 0x0035
//#define mmVGA_GENFC_WT_1 0x0036
//#define mmVGA_GENS1_1 0x0036
// addressBlock: dce_dc_azdec
// base address: 0x0
#define mmCORB_WRITE_POINTER 0x0000
#define mmCORB_WRITE_POINTER_BASE_IDX 0
#define mmCORB_READ_POINTER 0x0000
#define mmCORB_READ_POINTER_BASE_IDX 0
#define mmCORB_CONTROL 0x0001
#define mmCORB_CONTROL_BASE_IDX 0
#define mmCORB_STATUS 0x0001
#define mmCORB_STATUS_BASE_IDX 0
#define mmCORB_SIZE 0x0001
#define mmCORB_SIZE_BASE_IDX 0
#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmRIRB_WRITE_POINTER 0x0004
#define mmRIRB_WRITE_POINTER_BASE_IDX 0
#define mmRESPONSE_INTERRUPT_COUNT 0x0004
#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
#define mmRIRB_CONTROL 0x0005
#define mmRIRB_CONTROL_BASE_IDX 0
#define mmRIRB_STATUS 0x0005
#define mmRIRB_STATUS_BASE_IDX 0
#define mmRIRB_SIZE 0x0005
#define mmRIRB_SIZE_BASE_IDX 0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_STATUS 0x0008
#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_azstream0_azdec
// base address: 0x0
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_azstream1_azdec
// base address: 0x20
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_azstream2_azdec
// base address: 0x40
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_azstream3_azdec
// base address: 0x60
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_azstream4_azdec
// base address: 0x80
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_azstream5_azdec
// base address: 0xa0
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_azstream6_azdec
// base address: 0xc0
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_azstream7_azdec
// base address: 0xe0
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: azf0stream0_streamind
// base address: 0x0
#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream1_streamind
// base address: 0x0
#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream2_streamind
// base address: 0x0
#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream3_streamind
// base address: 0x0
#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream4_streamind
// base address: 0x0
#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream5_streamind
// base address: 0x0
#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream6_streamind
// base address: 0x0
#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream7_streamind
// base address: 0x0
#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream8_streamind
// base address: 0x0
#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream9_streamind
// base address: 0x0
#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream10_streamind
// base address: 0x0
#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream11_streamind
// base address: 0x0
#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream12_streamind
// base address: 0x0
#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream13_streamind
// base address: 0x0
#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream14_streamind
// base address: 0x0
#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream15_streamind
// base address: 0x0
#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0endpoint0_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint1_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint2_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint3_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint4_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint5_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint6_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint7_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0inputendpoint0_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint1_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint2_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint3_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint4_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint5_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint6_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint7_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
// addressBlock: descriptorind
// base address: 0x0
#define ixAUDIO_DESCRIPTOR0 0x0001
#define ixAUDIO_DESCRIPTOR1 0x0002
#define ixAUDIO_DESCRIPTOR2 0x0003
#define ixAUDIO_DESCRIPTOR3 0x0004
#define ixAUDIO_DESCRIPTOR4 0x0005
#define ixAUDIO_DESCRIPTOR5 0x0006
#define ixAUDIO_DESCRIPTOR6 0x0007
#define ixAUDIO_DESCRIPTOR7 0x0008
#define ixAUDIO_DESCRIPTOR8 0x0009
#define ixAUDIO_DESCRIPTOR9 0x000a
#define ixAUDIO_DESCRIPTOR10 0x000b
#define ixAUDIO_DESCRIPTOR11 0x000c
#define ixAUDIO_DESCRIPTOR12 0x000d
#define ixAUDIO_DESCRIPTOR13 0x000e
// addressBlock: sinkinfoind
// base address: 0x0
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
#define ixSINK_DESCRIPTION0 0x0005
#define ixSINK_DESCRIPTION1 0x0006
#define ixSINK_DESCRIPTION2 0x0007
#define ixSINK_DESCRIPTION3 0x0008
#define ixSINK_DESCRIPTION4 0x0009
#define ixSINK_DESCRIPTION5 0x000a
#define ixSINK_DESCRIPTION6 0x000b
#define ixSINK_DESCRIPTION7 0x000c
#define ixSINK_DESCRIPTION8 0x000d
#define ixSINK_DESCRIPTION9 0x000e
#define ixSINK_DESCRIPTION10 0x000f
#define ixSINK_DESCRIPTION11 0x0010
#define ixSINK_DESCRIPTION12 0x0011
#define ixSINK_DESCRIPTION13 0x0012
#define ixSINK_DESCRIPTION14 0x0013
#define ixSINK_DESCRIPTION15 0x0014
#define ixSINK_DESCRIPTION16 0x0015
#define ixSINK_DESCRIPTION17 0x0016
// addressBlock: azinputcrc0resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
// addressBlock: azinputcrc1resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
// addressBlock: azcrc0resultind
// base address: 0x0
#define ixAZALIA_CRC0_CHANNEL0 0x0000
#define ixAZALIA_CRC0_CHANNEL1 0x0001
#define ixAZALIA_CRC0_CHANNEL2 0x0002
#define ixAZALIA_CRC0_CHANNEL3 0x0003
#define ixAZALIA_CRC0_CHANNEL4 0x0004
#define ixAZALIA_CRC0_CHANNEL5 0x0005
#define ixAZALIA_CRC0_CHANNEL6 0x0006
#define ixAZALIA_CRC0_CHANNEL7 0x0007
// addressBlock: azcrc1resultind
// base address: 0x0
#define ixAZALIA_CRC1_CHANNEL0 0x0000
#define ixAZALIA_CRC1_CHANNEL1 0x0001
#define ixAZALIA_CRC1_CHANNEL2 0x0002
#define ixAZALIA_CRC1_CHANNEL3 0x0003
#define ixAZALIA_CRC1_CHANNEL4 0x0004
#define ixAZALIA_CRC1_CHANNEL5 0x0005
#define ixAZALIA_CRC1_CHANNEL6 0x0006
#define ixAZALIA_CRC1_CHANNEL7 0x0007
// addressBlock: vgaseqind
// base address: 0x0
#define ixSEQ00 0x0000
#define ixSEQ01 0x0001
#define ixSEQ02 0x0002
#define ixSEQ03 0x0003
#define ixSEQ04 0x0004
// addressBlock: vgacrtind
// base address: 0x0
#define ixCRT00 0x0000
#define ixCRT01 0x0001
#define ixCRT02 0x0002
#define ixCRT03 0x0003
#define ixCRT04 0x0004
#define ixCRT05 0x0005
#define ixCRT06 0x0006
#define ixCRT07 0x0007
#define ixCRT08 0x0008
#define ixCRT09 0x0009
#define ixCRT0A 0x000a
#define ixCRT0B 0x000b
#define ixCRT0C 0x000c
#define ixCRT0D 0x000d
#define ixCRT0E 0x000e
#define ixCRT0F 0x000f
#define ixCRT10 0x0010
#define ixCRT11 0x0011
#define ixCRT12 0x0012
#define ixCRT13 0x0013
#define ixCRT14 0x0014
#define ixCRT15 0x0015
#define ixCRT16 0x0016
#define ixCRT17 0x0017
#define ixCRT18 0x0018
#define ixCRT1E 0x001e
#define ixCRT1F 0x001f
#define ixCRT22 0x0022
// addressBlock: vgagrphind
// base address: 0x0
#define ixGRA00 0x0000
#define ixGRA01 0x0001
#define ixGRA02 0x0002
#define ixGRA03 0x0003
#define ixGRA04 0x0004
#define ixGRA05 0x0005
#define ixGRA06 0x0006
#define ixGRA07 0x0007
#define ixGRA08 0x0008
// addressBlock: vgaattrind
// base address: 0x0
#define ixATTR00 0x0000
#define ixATTR01 0x0001
#define ixATTR02 0x0002
#define ixATTR03 0x0003
#define ixATTR04 0x0004
#define ixATTR05 0x0005
#define ixATTR06 0x0006
#define ixATTR07 0x0007
#define ixATTR08 0x0008
#define ixATTR09 0x0009
#define ixATTR0A 0x000a
#define ixATTR0B 0x000b
#define ixATTR0C 0x000c
#define ixATTR0D 0x000d
#define ixATTR0E 0x000e
#define ixATTR0F 0x000f
#define ixATTR10 0x0010
#define ixATTR11 0x0011
#define ixATTR12 0x0012
#define ixATTR13 0x0013
#define ixATTR14 0x0014
#endif