Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DesignWare based PCIe controller on Rockchip SoCs

maintainers:
  - Shawn Lin <shawn.lin@rock-chips.com>
  - Simon Xue <xxm@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |+
  RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
  PCIe IP and thus inherits all the common properties defined in
  designware-pcie.txt.

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

# We need a select here so we don't match all nodes with 'snps,dw-pcie'
select:
  properties:
    compatible:
      contains:
        const: rockchip,rk3568-pcie
  required:
    - compatible

properties:
  compatible:
    items:
      - const: rockchip,rk3568-pcie
      - const: snps,dw-pcie

  reg:
    items:
      - description: Data Bus Interface (DBI) registers
      - description: Rockchip designed configuration registers
      - description: Config registers

  reg-names:
    items:
      - const: dbi
      - const: apb
      - const: config

  clocks:
    items:
      - description: AHB clock for PCIe master
      - description: AHB clock for PCIe slave
      - description: AHB clock for PCIe dbi
      - description: APB clock for PCIe
      - description: Auxiliary clock for PCIe

  clock-names:
    items:
      - const: aclk_mst
      - const: aclk_slv
      - const: aclk_dbi
      - const: pclk
      - const: aux

  msi-map: true

  num-lanes: true

  phys:
    maxItems: 1

  phy-names:
    const: pcie-phy

  power-domains:
    maxItems: 1

  ranges:
    maxItems: 2

  resets:
    maxItems: 1

  reset-names:
    const: pipe

  vpcie3v3-supply: true

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - msi-map
  - num-lanes
  - phys
  - phy-names
  - power-domains
  - resets
  - reset-names

unevaluatedProperties: false

examples:
  - |

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie3x2: pcie@fe280000 {
            compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
            reg = <0x3 0xc0800000 0x0 0x390000>,
                  <0x0 0xfe280000 0x0 0x10000>,
                  <0x3 0x80000000 0x0 0x100000>;
            reg-names = "dbi", "apb", "config";
            bus-range = <0x20 0x2f>;
            clocks = <&cru 143>, <&cru 144>,
                     <&cru 145>, <&cru 146>,
                     <&cru 147>;
            clock-names = "aclk_mst", "aclk_slv",
                          "aclk_dbi", "pclk",
                          "aux";
            device_type = "pci";
            linux,pci-domain = <2>;
            max-link-speed = <2>;
            msi-map = <0x2000 &its 0x2000 0x1000>;
            num-lanes = <2>;
            phys = <&pcie30phy>;
            phy-names = "pcie-phy";
            power-domains = <&power 15>;
            ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
                     <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
            resets = <&cru 193>;
            reset-names = "pipe";
            #address-cells = <3>;
            #size-cells = <2>;
        };
    };
...