tree cb6cef33f5133fdd55028cf2d054e248a10d61a9
parent 9495898ffd2075d0fd42b573cb40c23eaea7b18e
author Gregory CLEMENT <gregory.clement@free-electrons.com> 1404913214 +0200
committer Jason Cooper <jason@lakedaemon.net> 1405514062 +0000

ARM: mvebu: add CA9 MPcore SoC Controller node

The CA9 MPcore SoC Control block is a set of registers that allows to
configure certain internal aspects of the core blocks of the SoC
(Cortex-A9, L2 cache controller, etc.). In most cases, the default
values are fine so they aren't many reasons to touch those registers,
but there is one exception: to support cpuidle on Armada 38x, we need
to modify the value of the CA9 MPcore Reset Control register.

Therefore, this commit adds a new Device Tree binding for this
hardware block, and uses this new binding for the Armada 38x Device
Tree file.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree@vger.kernel.org
Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>