)]}'
{
  "commit": "33893757d5f40af69e9a1f80ffffee00a2eb0221",
  "tree": "50d80b953a22d018a1a82395ae12b1e472638121",
  "parents": [
    "8146be04908d3efbe3c6e130f551edbfd7a9dab8",
    "87b88b658b9b983b119f59396c08e4df1a211d59"
  ],
  "author": {
    "name": "Jakub Kicinski",
    "email": "kuba@kernel.org",
    "time": "Wed Oct 28 17:29:40 2026 -0700"
  },
  "committer": {
    "name": "Jakub Kicinski",
    "email": "kuba@kernel.org",
    "time": "Wed Oct 28 17:29:41 2026 -0700"
  },
  "message": "Merge branch \u0027net-pcs-xpcs-fix-runtime-pm-and-clock-lifecycle\u0027\n\nCoia Prant says:\n\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nnet: pcs: xpcs: fix runtime PM and clock lifecycle\n\nThis series fixes the runtime PM and CSR clock lifecycle in the DW XPCS\nplatform driver, a misleading error message in the Rockchip glue driver,\nand the MAINTAINERS coverage for the platform driver and its binding.\n\nThe issue was found while using pcs-xpcs-plat.c as a reference for the\nRockchip XPCS glue driver (pcs-xpcs-rk.c). On Rockchip the CSR clock\n(PCLK_XPCS) is required for register access, which exposed two problems\nin the generic platform driver:\n\n  - it calls pm_runtime_set_active() before runtime PM is enabled and\n    before the clock is prepared/enabled, so a later suspend tries to\n    disable a clock that was never enabled;\n\n  - with CONFIG_PM disabled, the runtime resume path is compiled out\n    and the CSR clock is never enabled at all.\n\nPatch 1 fixes the initial runtime PM status and registers a devm action\nthat force-suspends the device on teardown, so the clock does not leak\nwhen the driver is removed while runtime-active.\n\nPatch 2 handles !CONFIG_PM builds by preparing/enabling the CSR clock\nmanually and disabling it in the cleanup action. It also switches to\nRUNTIME_PM_OPS() and pm_ptr(), which are no-ops when CONFIG_PM is\nenabled, so that the runtime callbacks stay referenced and .pm is NULL\nin !CONFIG_PM builds. Because the CSR clock is optional and both cases\nare handled in the driver, Kconfig is left untouched and no PM\ndependency is added.\n\nPatch 3 rewords the cleanup action error message in the Rockchip glue\ndriver, which was merged into mainline today and currently mentions only\nthe EEE clock even though the action also tears down runtime PM.\n\nPatch 4 lists pcs-xpcs-plat.c and its DT binding under the DW XPCS\nentry. pcs-xpcs-plat.c currently only matches the ETHERNET PHY LIBRARY\nentry, and the binding is only matched by the generic DT and networking\nrules, so the entry does not cover the whole driver.\n\nNo upstream platform currently enables pcs-xpcs-plat with a real CSR\nclock dependency, so neither runtime issue is reachable in mainline\ntoday. Because of that, no Fixes: or Cc: stable tags are included, as\ndiscussed in the v1 thread.\n\nThe patches touch code that is already in mainline: the platform driver\nhas been there since f6bb3e9d98c2, and the Rockchip glue driver was\nmerged today. They are fixes to existing code, not new drivers or new\nfeatures.\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nLink: https://patch.msgid.link/20261023075214.1793922-2-coiaprant@gmail.com\nSigned-off-by: Jakub Kicinski \u003ckuba@kernel.org\u003e\n",
  "tree_diff": []
}