config PPC_CELL
	bool
	default n

config PPC_CELL_NATIVE
	bool
	select PPC_CELL
	select PPC_DCR_MMIO
	select PPC_OF_PLATFORM_PCI
	select PPC_INDIRECT_IO
	select PPC_NATIVE
	select MPIC
	default n

config PPC_IBM_CELL_BLADE
	bool "IBM Cell Blade"
	depends on PPC_MULTIPLATFORM && PPC64
	select PPC_CELL_NATIVE
	select PPC_RTAS
	select MMIO_NVRAM
	select PPC_UDBG_16550
	select UDBG_RTAS_CONSOLE

menu "Cell Broadband Engine options"
	depends on PPC_CELL

config SPU_FS
	tristate "SPU file system"
	default m
	depends on PPC_CELL
	select SPU_BASE
	select MEMORY_HOTPLUG
	help
	  The SPU file system is used to access Synergistic Processing
	  Units on machines implementing the Broadband Processor
	  Architecture.

config SPU_FS_64K_LS
	bool "Use 64K pages to map SPE local  store"
	# we depend on PPC_MM_SLICES for now rather than selecting
	# it because we depend on hugetlbfs hooks being present. We
	# will fix that when the generic code has been improved to
	# not require hijacking hugetlbfs hooks.
	depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
	default y
	select PPC_HAS_HASH_64K
	help
	  This option causes SPE local stores to be mapped in process
	  address spaces using 64K pages while the rest of the kernel
	  uses 4K pages. This can improve performances of applications
	  using multiple SPEs by lowering the TLB pressure on them.

config SPU_BASE
	bool
	default n

config CBE_RAS
	bool "RAS features for bare metal Cell BE"
	depends on PPC_CELL_NATIVE
	default y

config CBE_THERM
	tristate "CBE thermal support"
	default m
	depends on CBE_RAS

config CBE_CPUFREQ
	tristate "CBE frequency scaling"
	depends on CBE_RAS && CPU_FREQ
	default m
	help
	  This adds the cpufreq driver for Cell BE processors.
	  For details, take a look at <file:Documentation/cpu-freq/>.
	  If you don't have such processor, say N

config CBE_CPUFREQ_PMI
	tristate "CBE frequency scaling using PMI interface"
	depends on CBE_CPUFREQ && PPC_PMI && EXPERIMENTAL
	default n
	help
	  Select this, if you want to use the PMI interface
	  to switch frequencies. Using PMI, the
	  processor will not only be able to run at lower speed,
	  but also at lower core voltage.

endmenu