)]}'
{
  "commit": "2a47c26e55a2bc085a2349ed1d4e065ee298155f",
  "tree": "5d9b464e577b3218ae93f1e99fc8fe357908751b",
  "parents": [
    "a61288200e8b6f42bff116508dc72ebcc206f10a",
    "ca8313fd83399ea1d18e695c2ae9b259985c9e1f"
  ],
  "author": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Tue Dec 02 11:35:49 2025 -0800"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Tue Dec 02 11:35:49 2025 -0800"
  },
  "message": "Merge tag \u0027x86_microcode_for_v6.19_rc1\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip\n\nPull x86 microcode loading updates from Borislav Petkov:\n\n - Add microcode staging support on Intel: it moves the sole microcode\n   blobs loading to a non-critical path so that microcode loading\n   latencies are kept at minimum. The actual \"directing\" the hardware to\n   load microcode is the only step which is done on the critical path.\n\n   This scheme is also opportunistic as in: on a failure, the machinery\n   falls back to normal loading\n\n - Add the capability to the AMD side of the loader to select one of two\n   per-family/model/stepping patches: one is pre-Entrysign and the other\n   is post-Entrysign; with the goal to take care of machines which\n   haven\u0027t updated their BIOS yet - something they should absolutely do\n   as this is the only proper Entrysign fix\n\n - Other small cleanups and fixlets\n\n* tag \u0027x86_microcode_for_v6.19_rc1\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:\n  x86/microcode: Mark early_parse_cmdline() as __init\n  x86/microcode/AMD: Select which microcode patch to load\n  x86/microcode/intel: Enable staging when available\n  x86/microcode/intel: Support mailbox transfer\n  x86/microcode/intel: Implement staging handler\n  x86/microcode/intel: Define staging state struct\n  x86/microcode/intel: Establish staging control logic\n  x86/microcode: Introduce staging step to reduce late-loading time\n  x86/cpu/topology: Make primary thread mask available with SMP\u003dn\n",
  "tree_diff": []
}