)]}'
{
  "commit": "c1224569cef038b040db0459510cd7948ecd467b",
  "tree": "73e9886a6a81b34fdaad06db622cfaff62948c3a",
  "parents": [
    "d733f519f6443540f8359461a34e3b0042099bbe"
  ],
  "author": {
    "name": "Ivan Vecera",
    "email": "ivecera@redhat.com",
    "time": "Tue May 26 09:45:25 2026 +0200"
  },
  "committer": {
    "name": "Paolo Abeni",
    "email": "pabeni@redhat.com",
    "time": "Thu May 28 14:05:29 2026 +0200"
  },
  "message": "dpll: zl3073x: make frequency monitor a per-device attribute\n\nThe frequency monitoring feature uses shared hardware registers\nthat measure input reference frequencies independently of\nindividual DPLL channels. However, the freq_monitor flag was\nincorrectly placed in the per-DPLL structure, causing each\nchannel to track its own enable/disable state independently.\n\nSince the DPLL core calls measured_freq_get() only for the first\npin registration, the measured_freq_check() in the periodic worker\nwas gated by the per-DPLL freq_monitor flag of whichever channel\nhappens to be checked. If the first DPLL channel had frequency\nmonitoring disabled while another had it enabled, measurements\nwere never reported.\n\nMove freq_monitor from struct zl3073x_dpll to struct zl3073x_dev\nso all DPLL channels share a single flag, matching the hardware\nbehavior. Update freq_monitor_set() to notify other DPLL devices\nabout the change (like phase_offset_avg_factor_set() already does)\nand remove the mode-dependent guard in zl3073x_dpll_changes_check()\nsince all input pin monitoring (pin state, phase offset, FFO, and\nmeasured frequency) works correctly in all DPLL modes.\n\nFixes: bfc923b642874 (\"dpll: zl3073x: implement frequency monitoring\")\nSigned-off-by: Ivan Vecera \u003civecera@redhat.com\u003e\nLink: https://patch.msgid.link/20260526074525.1451008-4-ivecera@redhat.com\nSigned-off-by: Paolo Abeni \u003cpabeni@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5f1e70f3e40a0527ecdc033c70aff0638da69478",
      "old_mode": 33188,
      "old_path": "drivers/dpll/zl3073x/core.c",
      "new_id": "0a133b0f2d9728920d3c21bb3857281a031d2747",
      "new_mode": 33188,
      "new_path": "drivers/dpll/zl3073x/core.c"
    },
    {
      "type": "modify",
      "old_id": "99440620407da909c768fdd98efbaa62a60ad144",
      "old_mode": 33188,
      "old_path": "drivers/dpll/zl3073x/core.h",
      "new_id": "addba378b0df417b0eba9d9ea379423fb185c87b",
      "new_mode": 33188,
      "new_path": "drivers/dpll/zl3073x/core.h"
    },
    {
      "type": "modify",
      "old_id": "0770bd895de9071d6e98a7e3dcc76c0950c24201",
      "old_mode": 33188,
      "old_path": "drivers/dpll/zl3073x/dpll.c",
      "new_id": "0bfcbae2109f8f05f1e0dff817ad20dcf930a346",
      "new_mode": 33188,
      "new_path": "drivers/dpll/zl3073x/dpll.c"
    },
    {
      "type": "modify",
      "old_id": "c8bc8437a709938dc1efdcf431e8cceef3b0b7a1",
      "old_mode": 33188,
      "old_path": "drivers/dpll/zl3073x/dpll.h",
      "new_id": "21adcc18e45e106f7c719efd871c0425427edf7d",
      "new_mode": 33188,
      "new_path": "drivers/dpll/zl3073x/dpll.h"
    }
  ]
}