)]}'
{
  "id": "ac47063bd7be382790c787714ac436f06db126dd",
  "entries": [
    {
      "mode": 33188,
      "type": "blob",
      "id": "833f68fb070089e28bd8a27563fcdcc50b93c227",
      "name": "fpga-bridge.rst"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "8d2b79f696c1fba7fcb3849376b7a99cc0114330",
      "name": "fpga-mgr.rst"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "fb4da4240e961b06ad33cb7b9fe5799a5e5ce247",
      "name": "fpga-programming.rst"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "2d03b5fb7657553f5d2f989800bb01d1988f640c",
      "name": "fpga-region.rst"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "31a4773bd2e6c864740c2b67f727fb9be9e64dc5",
      "name": "index.rst"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "f54c7dabcc7dbe40d4b1a9adf1d3230228515518",
      "name": "intro.rst"
    }
  ]
}
