| /* |
| * MPC8540 ADS Device Tree Source |
| * |
| * Copyright 2006 Freescale Semiconductor Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| |
| / { |
| model = "MPC8540ADS"; |
| compatible = "MPC8540ADS", "MPC85xxADS"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| PowerPC,8540@0 { |
| device_type = "cpu"; |
| reg = <0>; |
| d-cache-line-size = <20>; // 32 bytes |
| i-cache-line-size = <20>; // 32 bytes |
| d-cache-size = <8000>; // L1, 32K |
| i-cache-size = <8000>; // L1, 32K |
| timebase-frequency = <0>; // 33 MHz, from uboot |
| bus-frequency = <0>; // 166 MHz |
| clock-frequency = <0>; // 825 MHz, from uboot |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <00000000 08000000>; // 128M at 0x0 |
| }; |
| |
| soc8540@e0000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| ranges = <0 e0000000 00100000>; |
| reg = <e0000000 00100000>; // CCSRBAR 1M |
| bus-frequency = <0>; |
| |
| memory-controller@2000 { |
| compatible = "fsl,8540-memory-controller"; |
| reg = <2000 1000>; |
| interrupt-parent = <&mpic>; |
| interrupts = <12 2>; |
| }; |
| |
| l2-cache-controller@20000 { |
| compatible = "fsl,8540-l2-cache-controller"; |
| reg = <20000 1000>; |
| cache-line-size = <20>; // 32 bytes |
| cache-size = <40000>; // L2, 256K |
| interrupt-parent = <&mpic>; |
| interrupts = <10 2>; |
| }; |
| |
| i2c@3000 { |
| device_type = "i2c"; |
| compatible = "fsl-i2c"; |
| reg = <3000 100>; |
| interrupts = <2b 2>; |
| interrupt-parent = <&mpic>; |
| dfsrr; |
| }; |
| |
| mdio@24520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "mdio"; |
| compatible = "gianfar"; |
| reg = <24520 20>; |
| phy0: ethernet-phy@0 { |
| interrupt-parent = <&mpic>; |
| interrupts = <5 1>; |
| reg = <0>; |
| device_type = "ethernet-phy"; |
| }; |
| phy1: ethernet-phy@1 { |
| interrupt-parent = <&mpic>; |
| interrupts = <5 1>; |
| reg = <1>; |
| device_type = "ethernet-phy"; |
| }; |
| phy3: ethernet-phy@3 { |
| interrupt-parent = <&mpic>; |
| interrupts = <7 1>; |
| reg = <3>; |
| device_type = "ethernet-phy"; |
| }; |
| }; |
| |
| ethernet@24000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <24000 1000>; |
| /* |
| * address is deprecated and will be removed |
| * in 2.6.25. Only recent versions of |
| * U-Boot support local-mac-address, however. |
| */ |
| address = [ 00 00 00 00 00 00 ]; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <1d 2 1e 2 22 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy0>; |
| }; |
| |
| ethernet@25000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <25000 1000>; |
| /* |
| * address is deprecated and will be removed |
| * in 2.6.25. Only recent versions of |
| * U-Boot support local-mac-address, however. |
| */ |
| address = [ 00 00 00 00 00 00 ]; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <23 2 24 2 28 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy1>; |
| }; |
| |
| ethernet@26000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "network"; |
| model = "FEC"; |
| compatible = "gianfar"; |
| reg = <26000 1000>; |
| /* |
| * address is deprecated and will be removed |
| * in 2.6.25. Only recent versions of |
| * U-Boot support local-mac-address, however. |
| */ |
| address = [ 00 00 00 00 00 00 ]; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <29 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy3>; |
| }; |
| |
| serial@4500 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <4500 100>; // reg base, size |
| clock-frequency = <0>; // should we fill in in uboot? |
| interrupts = <2a 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| serial@4600 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <4600 100>; // reg base, size |
| clock-frequency = <0>; // should we fill in in uboot? |
| interrupts = <2a 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| mpic: pic@40000 { |
| clock-frequency = <0>; |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| reg = <40000 40000>; |
| compatible = "chrp,open-pic"; |
| device_type = "open-pic"; |
| big-endian; |
| }; |
| }; |
| |
| pci@e0008000 { |
| interrupt-map-mask = <f800 0 0 7>; |
| interrupt-map = < |
| |
| /* IDSEL 0x02 */ |
| 1000 0 0 1 &mpic 1 1 |
| 1000 0 0 2 &mpic 2 1 |
| 1000 0 0 3 &mpic 3 1 |
| 1000 0 0 4 &mpic 4 1 |
| |
| /* IDSEL 0x03 */ |
| 1800 0 0 1 &mpic 4 1 |
| 1800 0 0 2 &mpic 1 1 |
| 1800 0 0 3 &mpic 2 1 |
| 1800 0 0 4 &mpic 3 1 |
| |
| /* IDSEL 0x04 */ |
| 2000 0 0 1 &mpic 3 1 |
| 2000 0 0 2 &mpic 4 1 |
| 2000 0 0 3 &mpic 1 1 |
| 2000 0 0 4 &mpic 2 1 |
| |
| /* IDSEL 0x05 */ |
| 2800 0 0 1 &mpic 2 1 |
| 2800 0 0 2 &mpic 3 1 |
| 2800 0 0 3 &mpic 4 1 |
| 2800 0 0 4 &mpic 1 1 |
| |
| /* IDSEL 0x0c */ |
| 6000 0 0 1 &mpic 1 1 |
| 6000 0 0 2 &mpic 2 1 |
| 6000 0 0 3 &mpic 3 1 |
| 6000 0 0 4 &mpic 4 1 |
| |
| /* IDSEL 0x0d */ |
| 6800 0 0 1 &mpic 4 1 |
| 6800 0 0 2 &mpic 1 1 |
| 6800 0 0 3 &mpic 2 1 |
| 6800 0 0 4 &mpic 3 1 |
| |
| /* IDSEL 0x0e */ |
| 7000 0 0 1 &mpic 3 1 |
| 7000 0 0 2 &mpic 4 1 |
| 7000 0 0 3 &mpic 1 1 |
| 7000 0 0 4 &mpic 2 1 |
| |
| /* IDSEL 0x0f */ |
| 7800 0 0 1 &mpic 2 1 |
| 7800 0 0 2 &mpic 3 1 |
| 7800 0 0 3 &mpic 4 1 |
| 7800 0 0 4 &mpic 1 1 |
| |
| /* IDSEL 0x12 */ |
| 9000 0 0 1 &mpic 1 1 |
| 9000 0 0 2 &mpic 2 1 |
| 9000 0 0 3 &mpic 3 1 |
| 9000 0 0 4 &mpic 4 1 |
| |
| /* IDSEL 0x13 */ |
| 9800 0 0 1 &mpic 4 1 |
| 9800 0 0 2 &mpic 1 1 |
| 9800 0 0 3 &mpic 2 1 |
| 9800 0 0 4 &mpic 3 1 |
| |
| /* IDSEL 0x14 */ |
| a000 0 0 1 &mpic 3 1 |
| a000 0 0 2 &mpic 4 1 |
| a000 0 0 3 &mpic 1 1 |
| a000 0 0 4 &mpic 2 1 |
| |
| /* IDSEL 0x15 */ |
| a800 0 0 1 &mpic 2 1 |
| a800 0 0 2 &mpic 3 1 |
| a800 0 0 3 &mpic 4 1 |
| a800 0 0 4 &mpic 1 1>; |
| interrupt-parent = <&mpic>; |
| interrupts = <18 2>; |
| bus-range = <0 0>; |
| ranges = <02000000 0 80000000 80000000 0 20000000 |
| 01000000 0 00000000 e2000000 0 00100000>; |
| clock-frequency = <3f940aa>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <e0008000 1000>; |
| compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; |
| device_type = "pci"; |
| }; |
| }; |
