blob: 8e1812e2f3ee58648ea46d2afac342641ee491af [file] [log] [blame]
* This file contains low level CPU setup functions.
* Valentine Barshak <>
* MontaVista Software, Inc (c) 2007
* Based on cpu_setup_6xx code by
* Benjamin Herrenschmidt <>
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
#include <asm/processor.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
b __init_fpu_44x
mflr r4
bl __init_fpu_44x
bl __plb_disable_wrp
mtlr r4
b __plb_disable_wrp
/* enable APU between CPU and FPU */
mfspr r3,SPRN_CCR0
/* Clear DAPUIB flag in CCR0 */
rlwinm r3,r3,0,12,10
mtspr SPRN_CCR0,r3
* Workaround for the incorrect write to DDR SDRAM errata.
* The write address can be corrupted during writes to
* DDR SDRAM when write pipelining is enabled on PLB0.
* Disable write pipelining here.
#define DCRN_PLB4A0_ACR 0x81
mfdcr r3,DCRN_PLB4A0_ACR
/* clear WRP bit in PLB4A0_ACR */
rlwinm r3,r3,0,8,6
mtdcr DCRN_PLB4A0_ACR,r3