| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * Copyright (c) 2020, The Linux Foundation. All rights reserved. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,dispcc-sm8250.h> |
| #include <dt-bindings/clock/qcom,gcc-sm8250.h> |
| #include <dt-bindings/clock/qcom,gpucc-sm8250.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> |
| #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> |
| #include <dt-bindings/dma/qcom-gpi.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interconnect/qcom,osm-l3.h> |
| #include <dt-bindings/interconnect/qcom,sm8250.h> |
| #include <dt-bindings/mailbox/qcom-ipcc.h> |
| #include <dt-bindings/power/qcom-rpmpd.h> |
| #include <dt-bindings/soc/qcom,apr.h> |
| #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| #include <dt-bindings/sound/qcom,q6afe.h> |
| #include <dt-bindings/thermal/thermal.h> |
| #include <dt-bindings/clock/qcom,camcc-sm8250.h> |
| #include <dt-bindings/clock/qcom,videocc-sm8250.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| i2c5 = &i2c5; |
| i2c6 = &i2c6; |
| i2c7 = &i2c7; |
| i2c8 = &i2c8; |
| i2c9 = &i2c9; |
| i2c10 = &i2c10; |
| i2c11 = &i2c11; |
| i2c12 = &i2c12; |
| i2c13 = &i2c13; |
| i2c14 = &i2c14; |
| i2c15 = &i2c15; |
| i2c16 = &i2c16; |
| i2c17 = &i2c17; |
| i2c18 = &i2c18; |
| i2c19 = &i2c19; |
| spi0 = &spi0; |
| spi1 = &spi1; |
| spi2 = &spi2; |
| spi3 = &spi3; |
| spi4 = &spi4; |
| spi5 = &spi5; |
| spi6 = &spi6; |
| spi7 = &spi7; |
| spi8 = &spi8; |
| spi9 = &spi9; |
| spi10 = &spi10; |
| spi11 = &spi11; |
| spi12 = &spi12; |
| spi13 = &spi13; |
| spi14 = &spi14; |
| spi15 = &spi15; |
| spi16 = &spi16; |
| spi17 = &spi17; |
| spi18 = &spi18; |
| spi19 = &spi19; |
| }; |
| |
| chosen { }; |
| |
| clocks { |
| xo_board: xo-board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <38400000>; |
| clock-output-names = "xo_board"; |
| }; |
| |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo485"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <448>; |
| dynamic-power-coefficient = <205>; |
| next-level-cache = <&L2_0>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, |
| <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| L2_0: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| L3_0: l3-cache { |
| compatible = "cache"; |
| }; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo485"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <448>; |
| dynamic-power-coefficient = <205>; |
| next-level-cache = <&L2_100>; |
| power-domains = <&CPU_PD1>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, |
| <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| L2_100: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo485"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <448>; |
| dynamic-power-coefficient = <205>; |
| next-level-cache = <&L2_200>; |
| power-domains = <&CPU_PD2>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, |
| <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| L2_200: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo485"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <448>; |
| dynamic-power-coefficient = <205>; |
| next-level-cache = <&L2_300>; |
| power-domains = <&CPU_PD3>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, |
| <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| L2_300: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo485"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| dynamic-power-coefficient = <379>; |
| next-level-cache = <&L2_400>; |
| power-domains = <&CPU_PD4>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, |
| <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| L2_400: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo485"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| dynamic-power-coefficient = <379>; |
| next-level-cache = <&L2_500>; |
| power-domains = <&CPU_PD5>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, |
| <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| L2_500: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo485"; |
| reg = <0x0 0x600>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| dynamic-power-coefficient = <379>; |
| next-level-cache = <&L2_600>; |
| power-domains = <&CPU_PD6>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, |
| <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| L2_600: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo485"; |
| reg = <0x0 0x700>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| dynamic-power-coefficient = <444>; |
| next-level-cache = <&L2_700>; |
| power-domains = <&CPU_PD7>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 2>; |
| operating-points-v2 = <&cpu7_opp_table>; |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, |
| <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| L2_700: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| |
| core4 { |
| cpu = <&CPU4>; |
| }; |
| |
| core5 { |
| cpu = <&CPU5>; |
| }; |
| |
| core6 { |
| cpu = <&CPU6>; |
| }; |
| |
| core7 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "silver-rail-power-collapse"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <360>; |
| exit-latency-us = <531>; |
| min-residency-us = <3934>; |
| local-timer-stop; |
| }; |
| |
| BIG_CPU_SLEEP_0: cpu-sleep-1-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "gold-rail-power-collapse"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <702>; |
| exit-latency-us = <1061>; |
| min-residency-us = <4488>; |
| local-timer-stop; |
| }; |
| }; |
| |
| domain-idle-states { |
| CLUSTER_SLEEP_0: cluster-sleep-0 { |
| compatible = "domain-idle-state"; |
| idle-state-name = "cluster-llcc-off"; |
| arm,psci-suspend-param = <0x4100c244>; |
| entry-latency-us = <3264>; |
| exit-latency-us = <6562>; |
| min-residency-us = <9987>; |
| local-timer-stop; |
| }; |
| }; |
| }; |
| |
| cpu0_opp_table: opp-table-cpu0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| cpu0_opp1: opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| opp-peak-kBps = <800000 9600000>; |
| }; |
| |
| cpu0_opp2: opp-403200000 { |
| opp-hz = /bits/ 64 <403200000>; |
| opp-peak-kBps = <800000 9600000>; |
| }; |
| |
| cpu0_opp3: opp-518400000 { |
| opp-hz = /bits/ 64 <518400000>; |
| opp-peak-kBps = <800000 16588800>; |
| }; |
| |
| cpu0_opp4: opp-614400000 { |
| opp-hz = /bits/ 64 <614400000>; |
| opp-peak-kBps = <800000 16588800>; |
| }; |
| |
| cpu0_opp5: opp-691200000 { |
| opp-hz = /bits/ 64 <691200000>; |
| opp-peak-kBps = <800000 19660800>; |
| }; |
| |
| cpu0_opp6: opp-787200000 { |
| opp-hz = /bits/ 64 <787200000>; |
| opp-peak-kBps = <1804000 19660800>; |
| }; |
| |
| cpu0_opp7: opp-883200000 { |
| opp-hz = /bits/ 64 <883200000>; |
| opp-peak-kBps = <1804000 23347200>; |
| }; |
| |
| cpu0_opp8: opp-979200000 { |
| opp-hz = /bits/ 64 <979200000>; |
| opp-peak-kBps = <1804000 26419200>; |
| }; |
| |
| cpu0_opp9: opp-1075200000 { |
| opp-hz = /bits/ 64 <1075200000>; |
| opp-peak-kBps = <1804000 29491200>; |
| }; |
| |
| cpu0_opp10: opp-1171200000 { |
| opp-hz = /bits/ 64 <1171200000>; |
| opp-peak-kBps = <1804000 32563200>; |
| }; |
| |
| cpu0_opp11: opp-1248000000 { |
| opp-hz = /bits/ 64 <1248000000>; |
| opp-peak-kBps = <1804000 36249600>; |
| }; |
| |
| cpu0_opp12: opp-1344000000 { |
| opp-hz = /bits/ 64 <1344000000>; |
| opp-peak-kBps = <2188000 36249600>; |
| }; |
| |
| cpu0_opp13: opp-1420800000 { |
| opp-hz = /bits/ 64 <1420800000>; |
| opp-peak-kBps = <2188000 39321600>; |
| }; |
| |
| cpu0_opp14: opp-1516800000 { |
| opp-hz = /bits/ 64 <1516800000>; |
| opp-peak-kBps = <3072000 42393600>; |
| }; |
| |
| cpu0_opp15: opp-1612800000 { |
| opp-hz = /bits/ 64 <1612800000>; |
| opp-peak-kBps = <3072000 42393600>; |
| }; |
| |
| cpu0_opp16: opp-1708800000 { |
| opp-hz = /bits/ 64 <1708800000>; |
| opp-peak-kBps = <4068000 42393600>; |
| }; |
| |
| cpu0_opp17: opp-1804800000 { |
| opp-hz = /bits/ 64 <1804800000>; |
| opp-peak-kBps = <4068000 42393600>; |
| }; |
| }; |
| |
| cpu4_opp_table: opp-table-cpu4 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| cpu4_opp1: opp-710400000 { |
| opp-hz = /bits/ 64 <710400000>; |
| opp-peak-kBps = <1804000 19660800>; |
| }; |
| |
| cpu4_opp2: opp-825600000 { |
| opp-hz = /bits/ 64 <825600000>; |
| opp-peak-kBps = <2188000 23347200>; |
| }; |
| |
| cpu4_opp3: opp-940800000 { |
| opp-hz = /bits/ 64 <940800000>; |
| opp-peak-kBps = <2188000 26419200>; |
| }; |
| |
| cpu4_opp4: opp-1056000000 { |
| opp-hz = /bits/ 64 <1056000000>; |
| opp-peak-kBps = <3072000 26419200>; |
| }; |
| |
| cpu4_opp5: opp-1171200000 { |
| opp-hz = /bits/ 64 <1171200000>; |
| opp-peak-kBps = <3072000 29491200>; |
| }; |
| |
| cpu4_opp6: opp-1286400000 { |
| opp-hz = /bits/ 64 <1286400000>; |
| opp-peak-kBps = <4068000 29491200>; |
| }; |
| |
| cpu4_opp7: opp-1382400000 { |
| opp-hz = /bits/ 64 <1382400000>; |
| opp-peak-kBps = <4068000 32563200>; |
| }; |
| |
| cpu4_opp8: opp-1478400000 { |
| opp-hz = /bits/ 64 <1478400000>; |
| opp-peak-kBps = <4068000 32563200>; |
| }; |
| |
| cpu4_opp9: opp-1574400000 { |
| opp-hz = /bits/ 64 <1574400000>; |
| opp-peak-kBps = <5412000 39321600>; |
| }; |
| |
| cpu4_opp10: opp-1670400000 { |
| opp-hz = /bits/ 64 <1670400000>; |
| opp-peak-kBps = <5412000 42393600>; |
| }; |
| |
| cpu4_opp11: opp-1766400000 { |
| opp-hz = /bits/ 64 <1766400000>; |
| opp-peak-kBps = <5412000 45465600>; |
| }; |
| |
| cpu4_opp12: opp-1862400000 { |
| opp-hz = /bits/ 64 <1862400000>; |
| opp-peak-kBps = <6220000 45465600>; |
| }; |
| |
| cpu4_opp13: opp-1958400000 { |
| opp-hz = /bits/ 64 <1958400000>; |
| opp-peak-kBps = <6220000 48537600>; |
| }; |
| |
| cpu4_opp14: opp-2054400000 { |
| opp-hz = /bits/ 64 <2054400000>; |
| opp-peak-kBps = <7216000 48537600>; |
| }; |
| |
| cpu4_opp15: opp-2150400000 { |
| opp-hz = /bits/ 64 <2150400000>; |
| opp-peak-kBps = <7216000 51609600>; |
| }; |
| |
| cpu4_opp16: opp-2246400000 { |
| opp-hz = /bits/ 64 <2246400000>; |
| opp-peak-kBps = <7216000 51609600>; |
| }; |
| |
| cpu4_opp17: opp-2342400000 { |
| opp-hz = /bits/ 64 <2342400000>; |
| opp-peak-kBps = <8368000 51609600>; |
| }; |
| |
| cpu4_opp18: opp-2419200000 { |
| opp-hz = /bits/ 64 <2419200000>; |
| opp-peak-kBps = <8368000 51609600>; |
| }; |
| }; |
| |
| cpu7_opp_table: opp-table-cpu7 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| cpu7_opp1: opp-844800000 { |
| opp-hz = /bits/ 64 <844800000>; |
| opp-peak-kBps = <2188000 19660800>; |
| }; |
| |
| cpu7_opp2: opp-960000000 { |
| opp-hz = /bits/ 64 <960000000>; |
| opp-peak-kBps = <2188000 26419200>; |
| }; |
| |
| cpu7_opp3: opp-1075200000 { |
| opp-hz = /bits/ 64 <1075200000>; |
| opp-peak-kBps = <3072000 26419200>; |
| }; |
| |
| cpu7_opp4: opp-1190400000 { |
| opp-hz = /bits/ 64 <1190400000>; |
| opp-peak-kBps = <3072000 29491200>; |
| }; |
| |
| cpu7_opp5: opp-1305600000 { |
| opp-hz = /bits/ 64 <1305600000>; |
| opp-peak-kBps = <4068000 32563200>; |
| }; |
| |
| cpu7_opp6: opp-1401600000 { |
| opp-hz = /bits/ 64 <1401600000>; |
| opp-peak-kBps = <4068000 32563200>; |
| }; |
| |
| cpu7_opp7: opp-1516800000 { |
| opp-hz = /bits/ 64 <1516800000>; |
| opp-peak-kBps = <4068000 36249600>; |
| }; |
| |
| cpu7_opp8: opp-1632000000 { |
| opp-hz = /bits/ 64 <1632000000>; |
| opp-peak-kBps = <5412000 39321600>; |
| }; |
| |
| cpu7_opp9: opp-1747200000 { |
| opp-hz = /bits/ 64 <1708800000>; |
| opp-peak-kBps = <5412000 42393600>; |
| }; |
| |
| cpu7_opp10: opp-1862400000 { |
| opp-hz = /bits/ 64 <1862400000>; |
| opp-peak-kBps = <6220000 45465600>; |
| }; |
| |
| cpu7_opp11: opp-1977600000 { |
| opp-hz = /bits/ 64 <1977600000>; |
| opp-peak-kBps = <6220000 48537600>; |
| }; |
| |
| cpu7_opp12: opp-2073600000 { |
| opp-hz = /bits/ 64 <2073600000>; |
| opp-peak-kBps = <7216000 48537600>; |
| }; |
| |
| cpu7_opp13: opp-2169600000 { |
| opp-hz = /bits/ 64 <2169600000>; |
| opp-peak-kBps = <7216000 51609600>; |
| }; |
| |
| cpu7_opp14: opp-2265600000 { |
| opp-hz = /bits/ 64 <2265600000>; |
| opp-peak-kBps = <7216000 51609600>; |
| }; |
| |
| cpu7_opp15: opp-2361600000 { |
| opp-hz = /bits/ 64 <2361600000>; |
| opp-peak-kBps = <8368000 51609600>; |
| }; |
| |
| cpu7_opp16: opp-2457600000 { |
| opp-hz = /bits/ 64 <2457600000>; |
| opp-peak-kBps = <8368000 51609600>; |
| }; |
| |
| cpu7_opp17: opp-2553600000 { |
| opp-hz = /bits/ 64 <2553600000>; |
| opp-peak-kBps = <8368000 51609600>; |
| }; |
| |
| cpu7_opp18: opp-2649600000 { |
| opp-hz = /bits/ 64 <2649600000>; |
| opp-peak-kBps = <8368000 51609600>; |
| }; |
| |
| cpu7_opp19: opp-2745600000 { |
| opp-hz = /bits/ 64 <2745600000>; |
| opp-peak-kBps = <8368000 51609600>; |
| }; |
| |
| cpu7_opp20: opp-2841600000 { |
| opp-hz = /bits/ 64 <2841600000>; |
| opp-peak-kBps = <8368000 51609600>; |
| }; |
| }; |
| |
| firmware { |
| scm: scm { |
| compatible = "qcom,scm-sm8250", "qcom,scm"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0x0 0x80000000 0x0 0x0>; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| |
| CPU_PD0: cpu0 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD1: cpu1 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD2: cpu2 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD3: cpu3 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD4: cpu4 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD5: cpu5 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD6: cpu6 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD7: cpu7 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CLUSTER_PD: cpu-cluster0 { |
| #power-domain-cells = <0>; |
| domain-idle-states = <&CLUSTER_SLEEP_0>; |
| }; |
| }; |
| |
| qup_opp_table: opp-table-qup { |
| compatible = "operating-points-v2"; |
| |
| opp-50000000 { |
| opp-hz = /bits/ 64 <50000000>; |
| required-opps = <&rpmhpd_opp_min_svs>; |
| }; |
| |
| opp-75000000 { |
| opp-hz = /bits/ 64 <75000000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-120000000 { |
| opp-hz = /bits/ 64 <120000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| hyp_mem: memory@80000000 { |
| reg = <0x0 0x80000000 0x0 0x600000>; |
| no-map; |
| }; |
| |
| xbl_aop_mem: memory@80700000 { |
| reg = <0x0 0x80700000 0x0 0x160000>; |
| no-map; |
| }; |
| |
| cmd_db: memory@80860000 { |
| compatible = "qcom,cmd-db"; |
| reg = <0x0 0x80860000 0x0 0x20000>; |
| no-map; |
| }; |
| |
| smem_mem: memory@80900000 { |
| reg = <0x0 0x80900000 0x0 0x200000>; |
| no-map; |
| }; |
| |
| removed_mem: memory@80b00000 { |
| reg = <0x0 0x80b00000 0x0 0x5300000>; |
| no-map; |
| }; |
| |
| camera_mem: memory@86200000 { |
| reg = <0x0 0x86200000 0x0 0x500000>; |
| no-map; |
| }; |
| |
| wlan_mem: memory@86700000 { |
| reg = <0x0 0x86700000 0x0 0x100000>; |
| no-map; |
| }; |
| |
| ipa_fw_mem: memory@86800000 { |
| reg = <0x0 0x86800000 0x0 0x10000>; |
| no-map; |
| }; |
| |
| ipa_gsi_mem: memory@86810000 { |
| reg = <0x0 0x86810000 0x0 0xa000>; |
| no-map; |
| }; |
| |
| gpu_mem: memory@8681a000 { |
| reg = <0x0 0x8681a000 0x0 0x2000>; |
| no-map; |
| }; |
| |
| npu_mem: memory@86900000 { |
| reg = <0x0 0x86900000 0x0 0x500000>; |
| no-map; |
| }; |
| |
| video_mem: memory@86e00000 { |
| reg = <0x0 0x86e00000 0x0 0x500000>; |
| no-map; |
| }; |
| |
| cvp_mem: memory@87300000 { |
| reg = <0x0 0x87300000 0x0 0x500000>; |
| no-map; |
| }; |
| |
| cdsp_mem: memory@87800000 { |
| reg = <0x0 0x87800000 0x0 0x1400000>; |
| no-map; |
| }; |
| |
| slpi_mem: memory@88c00000 { |
| reg = <0x0 0x88c00000 0x0 0x1500000>; |
| no-map; |
| }; |
| |
| adsp_mem: memory@8a100000 { |
| reg = <0x0 0x8a100000 0x0 0x1d00000>; |
| no-map; |
| }; |
| |
| spss_mem: memory@8be00000 { |
| reg = <0x0 0x8be00000 0x0 0x100000>; |
| no-map; |
| }; |
| |
| cdsp_secure_heap: memory@8bf00000 { |
| reg = <0x0 0x8bf00000 0x0 0x4600000>; |
| no-map; |
| }; |
| }; |
| |
| smem { |
| compatible = "qcom,smem"; |
| memory-region = <&smem_mem>; |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| smp2p-adsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <443>, <429>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_SMP2P |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_SMP2P>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <2>; |
| |
| smp2p_adsp_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| smp2p_adsp_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-cdsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <94>, <432>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_CDSP |
| IPCC_MPROC_SIGNAL_SMP2P |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_CDSP |
| IPCC_MPROC_SIGNAL_SMP2P>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <5>; |
| |
| smp2p_cdsp_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| smp2p_cdsp_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-slpi { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <481>, <430>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_SLPI |
| IPCC_MPROC_SIGNAL_SMP2P |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_SLPI |
| IPCC_MPROC_SIGNAL_SMP2P>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <3>; |
| |
| smp2p_slpi_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| smp2p_slpi_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| soc: soc@0 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0 0 0 0 0x10 0>; |
| dma-ranges = <0 0 0 0 0x10 0>; |
| compatible = "simple-bus"; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,gcc-sm8250"; |
| reg = <0x0 0x00100000 0x0 0x1f0000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| clock-names = "bi_tcxo", |
| "bi_tcxo_ao", |
| "sleep_clk"; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&rpmhcc RPMH_CXO_CLK_A>, |
| <&sleep_clk>; |
| }; |
| |
| ipcc: mailbox@408000 { |
| compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; |
| reg = <0 0x00408000 0 0x1000>; |
| interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| #mbox-cells = <2>; |
| }; |
| |
| rng: rng@793000 { |
| compatible = "qcom,prng-ee"; |
| reg = <0 0x00793000 0 0x1000>; |
| clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "core"; |
| }; |
| |
| gpi_dma2: dma-controller@800000 { |
| compatible = "qcom,sm8250-gpi-dma"; |
| reg = <0 0x00800000 0 0x70000>; |
| interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; |
| dma-channels = <10>; |
| dma-channel-mask = <0x3f>; |
| iommus = <&apps_smmu 0x76 0x0>; |
| #dma-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| qupv3_id_2: geniqup@8c0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0x0 0x008c0000 0x0 0x6000>; |
| clock-names = "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| iommus = <&apps_smmu 0x63 0x0>; |
| ranges; |
| status = "disabled"; |
| |
| i2c14: i2c@880000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00880000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c14_default>; |
| interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 0 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi14: spi@880000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00880000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; |
| interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 0 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c15: i2c@884000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00884000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c15_default>; |
| interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 1 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi15: spi@884000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00884000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; |
| interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 1 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c16: i2c@888000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00888000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c16_default>; |
| interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 2 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi16: spi@888000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00888000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; |
| interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 2 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c17: i2c@88c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0088c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c17_default>; |
| interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 3 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi17: spi@88c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0088c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; |
| interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 3 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart17: serial@88c000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x0088c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart17_default>; |
| interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c18: i2c@890000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00890000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c18_default>; |
| interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 4 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi18: spi@890000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00890000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; |
| interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 4 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart18: serial@890000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00890000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart18_default>; |
| interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c19: i2c@894000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00894000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c19_default>; |
| interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 5 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi19: spi@894000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00894000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; |
| interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 5 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| gpi_dma0: dma-controller@900000 { |
| compatible = "qcom,sm8250-gpi-dma"; |
| reg = <0 0x00900000 0 0x70000>; |
| interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
| dma-channels = <15>; |
| dma-channel-mask = <0x7ff>; |
| iommus = <&apps_smmu 0x5b6 0x0>; |
| #dma-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| qupv3_id_0: geniqup@9c0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0x0 0x009c0000 0x0 0x6000>; |
| clock-names = "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| iommus = <&apps_smmu 0x5a3 0x0>; |
| ranges; |
| status = "disabled"; |
| |
| i2c0: i2c@980000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00980000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c0_default>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 0 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@980000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00980000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, |
| <&gpi_dma0 1 0 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@984000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00984000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c1_default>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 1 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@984000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00984000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, |
| <&gpi_dma0 1 1 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@988000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00988000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c2_default>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 2 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@988000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00988000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, |
| <&gpi_dma0 1 2 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@988000 { |
| compatible = "qcom,geni-debug-uart"; |
| reg = <0 0x00988000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart2_default>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@98c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0098c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c3_default>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 3 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@98c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0098c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, |
| <&gpi_dma0 1 3 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@990000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00990000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c4_default>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 4 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@990000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00990000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, |
| <&gpi_dma0 1 4 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@994000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00994000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c5_default>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 5 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@994000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00994000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, |
| <&gpi_dma0 1 5 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@998000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00998000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c6_default>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 6 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi6: spi@998000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00998000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, |
| <&gpi_dma0 1 6 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart6: serial@998000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00998000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart6_default>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@99c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0099c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c7_default>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 7 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi7: spi@99c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0099c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, |
| <&gpi_dma0 1 7 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| gpi_dma1: dma-controller@a00000 { |
| compatible = "qcom,sm8250-gpi-dma"; |
| reg = <0 0x00a00000 0 0x70000>; |
| interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; |
| dma-channels = <10>; |
| dma-channel-mask = <0x3f>; |
| iommus = <&apps_smmu 0x56 0x0>; |
| #dma-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| qupv3_id_1: geniqup@ac0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0x0 0x00ac0000 0x0 0x6000>; |
| clock-names = "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| iommus = <&apps_smmu 0x43 0x0>; |
| ranges; |
| status = "disabled"; |
| |
| i2c8: i2c@a80000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a80000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c8_default>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 0 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi8: spi@a80000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a80000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 0 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c9: i2c@a84000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a84000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c9_default>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 1 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi9: spi@a84000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a84000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 1 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c10: i2c@a88000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a88000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c10_default>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 2 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi10: spi@a88000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a88000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 2 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c11: i2c@a8c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c11_default>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 3 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi11: spi@a8c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 3 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c12: i2c@a90000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a90000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c12_default>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 4 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi12: spi@a90000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a90000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 4 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart12: serial@a90000 { |
| compatible = "qcom,geni-debug-uart"; |
| reg = <0x0 0x00a90000 0x0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart12_default>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c13: i2c@a94000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a94000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c13_default>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 5 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi13: spi@a94000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a94000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 5 QCOM_GPI_SPI>; |
| dma-names = "tx", "rx"; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| config_noc: interconnect@1500000 { |
| compatible = "qcom,sm8250-config-noc"; |
| reg = <0 0x01500000 0 0xa580>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| system_noc: interconnect@1620000 { |
| compatible = "qcom,sm8250-system-noc"; |
| reg = <0 0x01620000 0 0x1c200>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| mc_virt: interconnect@163d000 { |
| compatible = "qcom,sm8250-mc-virt"; |
| reg = <0 0x0163d000 0 0x1000>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| aggre1_noc: interconnect@16e0000 { |
| compatible = "qcom,sm8250-aggre1-noc"; |
| reg = <0 0x016e0000 0 0x1f180>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| aggre2_noc: interconnect@1700000 { |
| compatible = "qcom,sm8250-aggre2-noc"; |
| reg = <0 0x01700000 0 0x33000>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| compute_noc: interconnect@1733000 { |
| compatible = "qcom,sm8250-compute-noc"; |
| reg = <0 0x01733000 0 0xa180>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| mmss_noc: interconnect@1740000 { |
| compatible = "qcom,sm8250-mmss-noc"; |
| reg = <0 0x01740000 0 0x1f080>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| pcie0: pci@1c00000 { |
| compatible = "qcom,pcie-sm8250"; |
| reg = <0 0x01c00000 0 0x3000>, |
| <0 0x60000000 0 0xf1d>, |
| <0 0x60000f20 0 0xa8>, |
| <0 0x60001000 0 0x1000>, |
| <0 0x60100000 0 0x100000>; |
| reg-names = "parf", "dbi", "elbi", "atu", "config"; |
| device_type = "pci"; |
| linux,pci-domain = <0>; |
| bus-range = <0x00 0xff>; |
| num-lanes = <1>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, |
| <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; |
| |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi0", "msi1", "msi2", "msi3", |
| "msi4", "msi5", "msi6", "msi7"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
| <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
| <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
| <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
| |
| clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, |
| <&gcc GCC_PCIE_0_AUX_CLK>, |
| <&gcc GCC_PCIE_0_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_0_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, |
| <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; |
| clock-names = "pipe", |
| "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "tbu", |
| "ddrss_sf_tbu"; |
| |
| iommus = <&apps_smmu 0x1c00 0x7f>; |
| iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, |
| <0x100 &apps_smmu 0x1c01 0x1>; |
| |
| resets = <&gcc GCC_PCIE_0_BCR>; |
| reset-names = "pci"; |
| |
| power-domains = <&gcc PCIE_0_GDSC>; |
| |
| phys = <&pcie0_lane>; |
| phy-names = "pciephy"; |
| |
| perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; |
| wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pcie0_default_state>; |
| |
| status = "disabled"; |
| }; |
| |
| pcie0_phy: phy@1c06000 { |
| compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; |
| reg = <0 0x01c06000 0 0x1c0>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, |
| <&gcc GCC_PCIE_0_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_WIFI_CLKREF_EN>, |
| <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "refgen"; |
| |
| resets = <&gcc GCC_PCIE_0_PHY_BCR>; |
| reset-names = "phy"; |
| |
| assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| status = "disabled"; |
| |
| pcie0_lane: phy@1c06200 { |
| reg = <0 0x1c06200 0 0x170>, /* tx */ |
| <0 0x1c06400 0 0x200>, /* rx */ |
| <0 0x1c06800 0 0x1f0>, /* pcs */ |
| <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ |
| clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; |
| clock-names = "pipe0"; |
| |
| #phy-cells = <0>; |
| |
| #clock-cells = <0>; |
| clock-output-names = "pcie_0_pipe_clk"; |
| }; |
| }; |
| |
| pcie1: pci@1c08000 { |
| compatible = "qcom,pcie-sm8250"; |
| reg = <0 0x01c08000 0 0x3000>, |
| <0 0x40000000 0 0xf1d>, |
| <0 0x40000f20 0 0xa8>, |
| <0 0x40001000 0 0x1000>, |
| <0 0x40100000 0 0x100000>; |
| reg-names = "parf", "dbi", "elbi", "atu", "config"; |
| device_type = "pci"; |
| linux,pci-domain = <1>; |
| bus-range = <0x00 0xff>; |
| num-lanes = <2>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, |
| <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; |
| |
| interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
| <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
| <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
| <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
| |
| clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, |
| <&gcc GCC_PCIE_1_AUX_CLK>, |
| <&gcc GCC_PCIE_1_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_1_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, |
| <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, |
| <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; |
| clock-names = "pipe", |
| "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "ref", |
| "tbu", |
| "ddrss_sf_tbu"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; |
| assigned-clock-rates = <19200000>; |
| |
| iommus = <&apps_smmu 0x1c80 0x7f>; |
| iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, |
| <0x100 &apps_smmu 0x1c81 0x1>; |
| |
| resets = <&gcc GCC_PCIE_1_BCR>; |
| reset-names = "pci"; |
| |
| power-domains = <&gcc PCIE_1_GDSC>; |
| |
| phys = <&pcie1_lane>; |
| phy-names = "pciephy"; |
| |
| perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; |
| wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pcie1_default_state>; |
| |
| status = "disabled"; |
| }; |
| |
| pcie1_phy: phy@1c0e000 { |
| compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; |
| reg = <0 0x01c0e000 0 0x1c0>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, |
| <&gcc GCC_PCIE_1_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, |
| <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "refgen"; |
| |
| resets = <&gcc GCC_PCIE_1_PHY_BCR>; |
| reset-names = "phy"; |
| |
| assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| status = "disabled"; |
| |
| pcie1_lane: phy@1c0e200 { |
| reg = <0 0x1c0e200 0 0x170>, /* tx0 */ |
| <0 0x1c0e400 0 0x200>, /* rx0 */ |
| <0 0x1c0ea00 0 0x1f0>, /* pcs */ |
| <0 0x1c0e600 0 0x170>, /* tx1 */ |
| <0 0x1c0e800 0 0x200>, /* rx1 */ |
| <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ |
| clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; |
| clock-names = "pipe0"; |
| |
| #phy-cells = <0>; |
| |
| #clock-cells = <0>; |
| clock-output-names = "pcie_1_pipe_clk"; |
| }; |
| }; |
| |
| pcie2: pci@1c10000 { |
| compatible = "qcom,pcie-sm8250"; |
| reg = <0 0x01c10000 0 0x3000>, |
| <0 0x64000000 0 0xf1d>, |
| <0 0x64000f20 0 0xa8>, |
| <0 0x64001000 0 0x1000>, |
| <0 0x64100000 0 0x100000>; |
| reg-names = "parf", "dbi", "elbi", "atu", "config"; |
| device_type = "pci"; |
| linux,pci-domain = <2>; |
| bus-range = <0x00 0xff>; |
| num-lanes = <2>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, |
| <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; |
| |
| interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
| <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
| <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
| <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
| |
| clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, |
| <&gcc GCC_PCIE_2_AUX_CLK>, |
| <&gcc GCC_PCIE_2_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_2_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_PCIE_MDM_CLKREF_EN>, |
| <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, |
| <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; |
| clock-names = "pipe", |
| "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "ref", |
| "tbu", |
| "ddrss_sf_tbu"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; |
| assigned-clock-rates = <19200000>; |
| |
| iommus = <&apps_smmu 0x1d00 0x7f>; |
| iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, |
| <0x100 &apps_smmu 0x1d01 0x1>; |
| |
| resets = <&gcc GCC_PCIE_2_BCR>; |
| reset-names = "pci"; |
| |
| power-domains = <&gcc PCIE_2_GDSC>; |
| |
| phys = <&pcie2_lane>; |
| phy-names = "pciephy"; |
| |
| perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; |
| wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pcie2_default_state>; |
| |
| status = "disabled"; |
| }; |
| |
| pcie2_phy: phy@1c16000 { |
| compatible = "qcom,sm8250-qmp-modem-pcie-phy"; |
| reg = <0 0x1c16000 0 0x1c0>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, |
| <&gcc GCC_PCIE_2_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_MDM_CLKREF_EN>, |
| <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "refgen"; |
| |
| resets = <&gcc GCC_PCIE_2_PHY_BCR>; |
| reset-names = "phy"; |
| |
| assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| status = "disabled"; |
| |
| pcie2_lane: phy@1c16200 { |
| reg = <0 0x1c16200 0 0x170>, /* tx0 */ |
| <0 0x1c16400 0 0x200>, /* rx0 */ |
| <0 0x1c16a00 0 0x1f0>, /* pcs */ |
| <0 0x1c16600 0 0x170>, /* tx1 */ |
| <0 0x1c16800 0 0x200>, /* rx1 */ |
| <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ |
| clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; |
| clock-names = "pipe0"; |
| |
| #phy-cells = <0>; |
| |
| #clock-cells = <0>; |
| clock-output-names = "pcie_2_pipe_clk"; |
| }; |
| }; |
| |
| ufs_mem_hc: ufshc@1d84000 { |
| compatible = "qcom,sm8250-ufshc", "qcom,ufshc", |
| "jedec,ufs-2.0"; |
| reg = <0 0x01d84000 0 0x3000>; |
| interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&ufs_mem_phy_lanes>; |
| phy-names = "ufsphy"; |
| lanes-per-direction = <2>; |
| #reset-cells = <1>; |
| resets = <&gcc GCC_UFS_PHY_BCR>; |
| reset-names = "rst"; |
| |
| power-domains = <&gcc UFS_PHY_GDSC>; |
| |
| iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; |
| |
| clock-names = |
| "core_clk", |
| "bus_aggr_clk", |
| "iface_clk", |
| "core_clk_unipro", |
| "ref_clk", |
| "tx_lane0_sync_clk", |
| "rx_lane0_sync_clk", |
| "rx_lane1_sync_clk"; |
| clocks = |
| <&gcc GCC_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_UFS_PHY_AHB_CLK>, |
| <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; |
| freq-table-hz = |
| <37500000 300000000>, |
| <0 0>, |
| <0 0>, |
| <37500000 300000000>, |
| <0 0>, |
| <0 0>, |
| <0 0>, |
| <0 0>; |
| |
| status = "disabled"; |
| }; |
| |
| ufs_mem_phy: phy@1d87000 { |
| compatible = "qcom,sm8250-qmp-ufs-phy"; |
| reg = <0 0x01d87000 0 0x1c0>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| clock-names = "ref", |
| "ref_aux"; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
| |
| resets = <&ufs_mem_hc 0>; |
| reset-names = "ufsphy"; |
| status = "disabled"; |
| |
| ufs_mem_phy_lanes: phy@1d87400 { |
| reg = <0 0x01d87400 0 0x108>, |
| <0 0x01d87600 0 0x1e0>, |
| <0 0x01d87c00 0 0x1dc>, |
| <0 0x01d87800 0 0x108>, |
| <0 0x01d87a00 0 0x1e0>; |
| #phy-cells = <0>; |
| }; |
| }; |
| |
| ipa_virt: interconnect@1e00000 { |
| compatible = "qcom,sm8250-ipa-virt"; |
| reg = <0 0x01e00000 0 0x1000>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| tcsr_mutex: hwlock@1f40000 { |
| compatible = "qcom,tcsr-mutex"; |
| reg = <0x0 0x01f40000 0x0 0x40000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| wsamacro: codec@3240000 { |
| compatible = "qcom,sm8250-lpass-wsa-macro"; |
| reg = <0 0x03240000 0 0x1000>; |
| clocks = <&audiocc LPASS_CDC_WSA_MCLK>, |
| <&audiocc LPASS_CDC_WSA_NPL>, |
| <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&aoncc LPASS_CDC_VA_MCLK>, |
| <&vamacro>; |
| |
| clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; |
| |
| #clock-cells = <0>; |
| clock-frequency = <9600000>; |
| clock-output-names = "mclk"; |
| #sound-dai-cells = <1>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&wsa_swr_active>; |
| }; |
| |
| swr0: soundwire-controller@3250000 { |
| reg = <0 0x03250000 0 0x2000>; |
| compatible = "qcom,soundwire-v1.5.1"; |
| interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&wsamacro>; |
| clock-names = "iface"; |
| |
| qcom,din-ports = <2>; |
| qcom,dout-ports = <6>; |
| |
| qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; |
| qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; |
| qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; |
| qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; |
| |
| #sound-dai-cells = <1>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| }; |
| |
| audiocc: clock-controller@3300000 { |
| compatible = "qcom,sm8250-lpass-audiocc"; |
| reg = <0 0x03300000 0 0x30000>; |
| #clock-cells = <1>; |
| clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; |
| clock-names = "core", "audio", "bus"; |
| }; |
| |
| vamacro: codec@3370000 { |
| compatible = "qcom,sm8250-lpass-va-macro"; |
| reg = <0 0x03370000 0 0x1000>; |
| clocks = <&aoncc LPASS_CDC_VA_MCLK>, |
| <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; |
| |
| clock-names = "mclk", "macro", "dcodec"; |
| |
| #clock-cells = <0>; |
| clock-frequency = <9600000>; |
| clock-output-names = "fsgen"; |
| #sound-dai-cells = <1>; |
| }; |
| |
| rxmacro: rxmacro@3200000 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&rx_swr_active>; |
| compatible = "qcom,sm8250-lpass-rx-macro"; |
| reg = <0 0x3200000 0 0x1000>; |
| status = "disabled"; |
| |
| clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&vamacro>; |
| |
| clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; |
| |
| #clock-cells = <0>; |
| clock-frequency = <9600000>; |
| clock-output-names = "mclk"; |
| #sound-dai-cells = <1>; |
| }; |
| |
| swr1: soundwire-controller@3210000 { |
| reg = <0 0x3210000 0 0x2000>; |
| compatible = "qcom,soundwire-v1.5.1"; |
| status = "disabled"; |
| interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&rxmacro>; |
| clock-names = "iface"; |
| label = "RX"; |
| qcom,din-ports = <0>; |
| qcom,dout-ports = <5>; |
| |
| qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; |
| qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; |
| qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; |
| qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; |
| qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; |
| qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; |
| qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; |
| qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; |
| qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; |
| |
| #sound-dai-cells = <1>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| }; |
| |
| txmacro: txmacro@3220000 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&tx_swr_active>; |
| compatible = "qcom,sm8250-lpass-tx-macro"; |
| reg = <0 0x3220000 0 0x1000>; |
| status = "disabled"; |
| |
| clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&vamacro>; |
| |
| clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; |
| |
| #clock-cells = <0>; |
| clock-frequency = <9600000>; |
| clock-output-names = "mclk"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| #sound-dai-cells = <1>; |
| }; |
| |
| /* tx macro */ |
| swr2: soundwire-controller@3230000 { |
| reg = <0 0x3230000 0 0x2000>; |
| compatible = "qcom,soundwire-v1.5.1"; |
| interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "core"; |
| status = "disabled"; |
| |
| clocks = <&txmacro>; |
| clock-names = "iface"; |
| label = "TX"; |
| |
| qcom,din-ports = <5>; |
| qcom,dout-ports = <0>; |
| qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; |
| qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; |
| qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; |
| qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; |
| qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; |
| qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; |
| qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; |
| qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; |
| qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; |
| qcom,port-offset = <1>; |
| #sound-dai-cells = <1>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| }; |
| |
| aoncc: clock-controller@3380000 { |
| compatible = "qcom,sm8250-lpass-aoncc"; |
| reg = <0 0x03380000 0 0x40000>; |
| #clock-cells = <1>; |
| clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; |
| clock-names = "core", "audio", "bus"; |
| }; |
| |
| lpass_tlmm: pinctrl@33c0000{ |
| compatible = "qcom,sm8250-lpass-lpi-pinctrl"; |
| reg = <0 0x033c0000 0x0 0x20000>, |
| <0 0x03550000 0x0 0x10000>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&lpass_tlmm 0 0 14>; |
| |
| clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; |
| clock-names = "core", "audio"; |
| |
| wsa_swr_active: wsa-swr-active-pins { |
| clk { |
| pins = "gpio10"; |
| function = "wsa_swr_clk"; |
| drive-strength = <2>; |
| slew-rate = <1>; |
| bias-disable; |
| }; |
| |
| data { |
| pins = "gpio11"; |
| function = "wsa_swr_data"; |
| drive-strength = <2>; |
| slew-rate = <1>; |
| bias-bus-hold; |
| |
| }; |
| }; |
| |
| wsa_swr_sleep: wsa-swr-sleep-pins { |
| clk { |
| pins = "gpio10"; |
| function = "wsa_swr_clk"; |
| drive-strength = <2>; |
| input-enable; |
| bias-pull-down; |
| }; |
| |
| data { |
| pins = "gpio11"; |
| function = "wsa_swr_data"; |
| drive-strength = <2>; |
| input-enable; |
| bias-pull-down; |
| |
| }; |
| }; |
| |
| dmic01_active: dmic01-active-pins { |
| clk { |
| pins = "gpio6"; |
| function = "dmic1_clk"; |
| drive-strength = <8>; |
| output-high; |
| }; |
| data { |
| pins = "gpio7"; |
| function = "dmic1_data"; |
| drive-strength = <8>; |
| input-enable; |
| }; |
| }; |
| |
| dmic01_sleep: dmic01-sleep-pins { |
| clk { |
| pins = "gpio6"; |
| function = "dmic1_clk"; |
| drive-strength = <2>; |
| bias-disable; |
| output-low; |
| }; |
| |
| data { |
| pins = "gpio7"; |
| function = "dmic1_data"; |
| drive-strength = <2>; |
| pull-down; |
| input-enable; |
| }; |
| }; |
| |
| rx_swr_active: rx_swr-active-pins { |
| clk { |
| pins = "gpio3"; |
| function = "swr_rx_clk"; |
| drive-strength = <2>; |
| slew-rate = <1>; |
| bias-disable; |
| }; |
| |
| data { |
| pins = "gpio4", "gpio5"; |
| function = "swr_rx_data"; |
| drive-strength = <2>; |
| slew-rate = <1>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| tx_swr_active: tx_swr-active-pins { |
| clk { |
| pins = "gpio0"; |
| function = "swr_tx_clk"; |
| drive-strength = <2>; |
| slew-rate = <1>; |
| bias-disable; |
| }; |
| |
| data { |
| pins = "gpio1", "gpio2"; |
| function = "swr_tx_data"; |
| drive-strength = <2>; |
| slew-rate = <1>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| tx_swr_sleep: tx_swr-sleep-pins { |
| clk { |
| pins = "gpio0"; |
| function = "swr_tx_clk"; |
| drive-strength = <2>; |
| input-enable; |
| bias-pull-down; |
| }; |
| |
| data1 { |
| pins = "gpio1"; |
| function = "swr_tx_data"; |
| drive-strength = <2>; |
| input-enable; |
| bias-bus-hold; |
| }; |
| |
| data2 { |
| pins = "gpio2"; |
| function = "swr_tx_data"; |
| drive-strength = <2>; |
| input-enable; |
| bias-pull-down; |
| }; |
| }; |
| }; |
| |
| gpu: gpu@3d00000 { |
| compatible = "qcom,adreno-650.2", |
| "qcom,adreno"; |
| |
| reg = <0 0x03d00000 0 0x40000>; |
| reg-names = "kgsl_3d0_reg_memory"; |
| |
| interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; |
| |
| iommus = <&adreno_smmu 0 0x401>; |
| |
| operating-points-v2 = <&gpu_opp_table>; |
| |
| qcom,gmu = <&gmu>; |
| |
| status = "disabled"; |
| |
| zap-shader { |
| memory-region = <&gpu_mem>; |
| }; |
| |
| /* note: downstream checks gpu binning for 670 Mhz */ |
| gpu_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-670000000 { |
| opp-hz = /bits/ 64 <670000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| }; |
| |
| opp-587000000 { |
| opp-hz = /bits/ 64 <587000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
| }; |
| |
| opp-525000000 { |
| opp-hz = /bits/ 64 <525000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; |
| }; |
| |
| opp-490000000 { |
| opp-hz = /bits/ 64 <490000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| }; |
| |
| opp-441600000 { |
| opp-hz = /bits/ 64 <441600000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; |
| }; |
| |
| opp-400000000 { |
| opp-hz = /bits/ 64 <400000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
| }; |
| |
| opp-305000000 { |
| opp-hz = /bits/ 64 <305000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
| }; |
| }; |
| }; |
| |
| gmu: gmu@3d6a000 { |
| compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; |
| |
| reg = <0 0x03d6a000 0 0x30000>, |
| <0 0x3de0000 0 0x10000>, |
| <0 0xb290000 0 0x10000>, |
| <0 0xb490000 0 0x10000>; |
| reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; |
| |
| interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hfi", "gmu"; |
| |
| clocks = <&gpucc GPU_CC_AHB_CLK>, |
| <&gpucc GPU_CC_CX_GMU_CLK>, |
| <&gpucc GPU_CC_CXO_CLK>, |
| <&gcc GCC_DDRSS_GPU_AXI_CLK>, |
| <&gcc GCC_GPU_MEMNOC_GFX_CLK>; |
| clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; |
| |
| power-domains = <&gpucc GPU_CX_GDSC>, |
| <&gpucc GPU_GX_GDSC>; |
| power-domain-names = "cx", "gx"; |
| |
| iommus = <&adreno_smmu 5 0x400>; |
| |
| operating-points-v2 = <&gmu_opp_table>; |
| |
| status = "disabled"; |
| |
| gmu_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-200000000 { |
| opp-hz = /bits/ 64 <200000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
| }; |
| }; |
| }; |
| |
| gpucc: clock-controller@3d90000 { |
| compatible = "qcom,sm8250-gpucc"; |
| reg = <0 0x03d90000 0 0x9000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_GPU_GPLL0_CLK_SRC>, |
| <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; |
| clock-names = "bi_tcxo", |
| "gcc_gpu_gpll0_clk_src", |
| "gcc_gpu_gpll0_div_clk_src"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| adreno_smmu: iommu@3da0000 { |
| compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; |
| reg = <0 0x03da0000 0 0x10000>; |
| #iommu-cells = <2>; |
| #global-interrupts = <2>; |
| interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gpucc GPU_CC_AHB_CLK>, |
| <&gcc GCC_GPU_MEMNOC_GFX_CLK>, |
| <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; |
| clock-names = "ahb", "bus", "iface"; |
| |
| power-domains = <&gpucc GPU_CX_GDSC>; |
| }; |
| |
| slpi: remoteproc@5c00000 { |
| compatible = "qcom,sm8250-slpi-pas"; |
| reg = <0 0x05c00000 0 0x4000>; |
| |
| interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, |
| <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", |
| "handover", "stop-ack"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| |
| power-domains = <&rpmhpd SM8250_LCX>, |
| <&rpmhpd SM8250_LMX>; |
| power-domain-names = "lcx", "lmx"; |
| |
| memory-region = <&slpi_mem>; |
| |
| qcom,qmp = <&aoss_qmp>; |
| |
| qcom,smem-states = <&smp2p_slpi_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| status = "disabled"; |
| |
| glink-edge { |
| interrupts-extended = <&ipcc IPCC_CLIENT_SLPI |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_SLPI |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| |
| label = "slpi"; |
| qcom,remote-pid = <3>; |
| |
| fastrpc { |
| compatible = "qcom,fastrpc"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| label = "sdsp"; |
| qcom,non-secure-domain; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compute-cb@1 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <1>; |
| iommus = <&apps_smmu 0x0541 0x0>; |
| }; |
| |
| compute-cb@2 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <2>; |
| iommus = <&apps_smmu 0x0542 0x0>; |
| }; |
| |
| compute-cb@3 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <3>; |
| iommus = <&apps_smmu 0x0543 0x0>; |
| /* note: shared-cb = <4> in downstream */ |
| }; |
| }; |
| }; |
| }; |
| |
| cdsp: remoteproc@8300000 { |
| compatible = "qcom,sm8250-cdsp-pas"; |
| reg = <0 0x08300000 0 0x10000>; |
| |
| interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, |
| <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", |
| "handover", "stop-ack"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| |
| power-domains = <&rpmhpd SM8250_CX>; |
| |
| memory-region = <&cdsp_mem>; |
| |
| qcom,qmp = <&aoss_qmp>; |
| |
| qcom,smem-states = <&smp2p_cdsp_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| status = "disabled"; |
| |
| glink-edge { |
| interrupts-extended = <&ipcc IPCC_CLIENT_CDSP |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_CDSP |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| |
| label = "cdsp"; |
| qcom,remote-pid = <5>; |
| |
| fastrpc { |
| compatible = "qcom,fastrpc"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| label = "cdsp"; |
| qcom,non-secure-domain; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compute-cb@1 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <1>; |
| iommus = <&apps_smmu 0x1001 0x0460>; |
| }; |
| |
| compute-cb@2 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <2>; |
| iommus = <&apps_smmu 0x1002 0x0460>; |
| }; |
| |
| compute-cb@3 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <3>; |
| iommus = <&apps_smmu 0x1003 0x0460>; |
| }; |
| |
| compute-cb@4 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <4>; |
| iommus = <&apps_smmu 0x1004 0x0460>; |
| }; |
| |
| compute-cb@5 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <5>; |
| iommus = <&apps_smmu 0x1005 0x0460>; |
| }; |
| |
| compute-cb@6 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <6>; |
| iommus = <&apps_smmu 0x1006 0x0460>; |
| }; |
| |
| compute-cb@7 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <7>; |
| iommus = <&apps_smmu 0x1007 0x0460>; |
| }; |
| |
| compute-cb@8 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <8>; |
| iommus = <&apps_smmu 0x1008 0x0460>; |
| }; |
| |
| /* note: secure cb9 in downstream */ |
| }; |
| }; |
| }; |
| |
| sound: sound { |
| }; |
| |
| usb_1_hsphy: phy@88e3000 { |
| compatible = "qcom,sm8250-usb-hs-phy", |
| "qcom,usb-snps-hs-7nm-phy"; |
| reg = <0 0x088e3000 0 0x400>; |
| status = "disabled"; |
| #phy-cells = <0>; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "ref"; |
| |
| resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
| }; |
| |
| usb_2_hsphy: phy@88e4000 { |
| compatible = "qcom,sm8250-usb-hs-phy", |
| "qcom,usb-snps-hs-7nm-phy"; |
| reg = <0 0x088e4000 0 0x400>; |
| status = "disabled"; |
| #phy-cells = <0>; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "ref"; |
| |
| resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; |
| }; |
| |
| usb_1_qmpphy: phy@88e9000 { |
| compatible = "qcom,sm8250-qmp-usb3-dp-phy"; |
| reg = <0 0x088e9000 0 0x200>, |
| <0 0x088e8000 0 0x40>, |
| <0 0x088ea000 0 0x200>; |
| status = "disabled"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; |
| clock-names = "aux", "ref_clk_src", "com_aux"; |
| |
| resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, |
| <&gcc GCC_USB3_PHY_PRIM_BCR>; |
| reset-names = "phy", "common"; |
| |
| usb_1_ssphy: usb3-phy@88e9200 { |
| reg = <0 0x088e9200 0 0x200>, |
| <0 0x088e9400 0 0x200>, |
| <0 0x088e9c00 0 0x400>, |
| <0 0x088e9600 0 0x200>, |
| <0 0x088e9800 0 0x200>, |
| <0 0x088e9a00 0 0x100>; |
| #clock-cells = <0>; |
| #phy-cells = <0>; |
| clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
| clock-names = "pipe0"; |
| clock-output-names = "usb3_phy_pipe_clk_src"; |
| }; |
| |
| dp_phy: dp-phy@88ea200 { |
| reg = <0 0x088ea200 0 0x200>, |
| <0 0x088ea400 0 0x200>, |
| <0 0x088eac00 0 0x400>, |
| <0 0x088ea600 0 0x200>, |
| <0 0x088ea800 0 0x200>, |
| <0 0x088eaa00 0 0x100>; |
| #phy-cells = <0>; |
| #clock-cells = <1>; |
| clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
| clock-names = "pipe0"; |
| clock-output-names = "usb3_phy_pipe_clk_src"; |
| }; |
| }; |
| |
| usb_2_qmpphy: phy@88eb000 { |
| compatible = "qcom,sm8250-qmp-usb3-uni-phy"; |
| reg = <0 0x088eb000 0 0x200>; |
| status = "disabled"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_USB3_SEC_CLKREF_EN>, |
| <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; |
| clock-names = "aux", "ref_clk_src", "ref", "com_aux"; |
| |
| resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, |
| <&gcc GCC_USB3_PHY_SEC_BCR>; |
| reset-names = "phy", "common"; |
| |
| usb_2_ssphy: phy@88eb200 { |
| reg = <0 0x088eb200 0 0x200>, |
| <0 0x088eb400 0 0x200>, |
| <0 0x088eb800 0 0x800>; |
| #clock-cells = <0>; |
| #phy-cells = <0>; |
| clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; |
| clock-names = "pipe0"; |
| clock-output-names = "usb3_uni_phy_pipe_clk_src"; |
| }; |
| }; |
| |
| sdhc_2: mmc@8804000 { |
| compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; |
| reg = <0 0x08804000 0 0x1000>; |
| |
| interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| clocks = <&gcc GCC_SDCC2_AHB_CLK>, |
| <&gcc GCC_SDCC2_APPS_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "iface", "core", "xo"; |
| iommus = <&apps_smmu 0x4a0 0x0>; |
| qcom,dll-config = <0x0007642c>; |
| qcom,ddr-config = <0x80040868>; |
| power-domains = <&rpmhpd SM8250_CX>; |
| operating-points-v2 = <&sdhc2_opp_table>; |
| |
| status = "disabled"; |
| |
| sdhc2_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-19200000 { |
| opp-hz = /bits/ 64 <19200000>; |
| required-opps = <&rpmhpd_opp_min_svs>; |
| }; |
| |
| opp-50000000 { |
| opp-hz = /bits/ 64 <50000000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| |
| opp-202000000 { |
| opp-hz = /bits/ 64 <202000000>; |
| required-opps = <&rpmhpd_opp_svs_l1>; |
| }; |
| }; |
| }; |
| |
| dc_noc: interconnect@90c0000 { |
| compatible = "qcom,sm8250-dc-noc"; |
| reg = <0 0x090c0000 0 0x4200>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| gem_noc: interconnect@9100000 { |
| compatible = "qcom,sm8250-gem-noc"; |
| reg = <0 0x09100000 0 0xb4000>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| npu_noc: interconnect@9990000 { |
| compatible = "qcom,sm8250-npu-noc"; |
| reg = <0 0x09990000 0 0x1600>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| usb_1: usb@a6f8800 { |
| compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; |
| reg = <0 0x0a6f8800 0 0x400>; |
| status = "disabled"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| dma-ranges; |
| |
| clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
| <&gcc GCC_USB30_PRIM_MASTER_CLK>, |
| <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, |
| <&gcc GCC_USB30_PRIM_SLEEP_CLK>, |
| <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB3_SEC_CLKREF_EN>; |
| clock-names = "cfg_noc", |
| "core", |
| "iface", |
| "sleep", |
| "mock_utmi", |
| "xo"; |
| |
| assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB30_PRIM_MASTER_CLK>; |
| assigned-clock-rates = <19200000>, <200000000>; |
| |
| interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 15 IRQ_TYPE_EDGE_BOTH>, |
| <&pdc 14 IRQ_TYPE_EDGE_BOTH>; |
| interrupt-names = "hs_phy_irq", |
| "ss_phy_irq", |
| "dm_hs_phy_irq", |
| "dp_hs_phy_irq"; |
| |
| power-domains = <&gcc USB30_PRIM_GDSC>; |
| |
| resets = <&gcc GCC_USB30_PRIM_BCR>; |
| |
| usb_1_dwc3: usb@a600000 { |
| compatible = "snps,dwc3"; |
| reg = <0 0x0a600000 0 0xcd00>; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| iommus = <&apps_smmu 0x0 0x0>; |
| snps,dis_u2_susphy_quirk; |
| snps,dis_enblslpm_quirk; |
| phys = <&usb_1_hsphy>, <&usb_1_ssphy>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| }; |
| }; |
| |
| system-cache-controller@9200000 { |
| compatible = "qcom,sm8250-llcc"; |
| reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; |
| reg-names = "llcc_base", "llcc_broadcast_base"; |
| }; |
| |
| usb_2: usb@a8f8800 { |
| compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; |
| reg = <0 0x0a8f8800 0 0x400>; |
| status = "disabled"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| dma-ranges; |
| |
| clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, |
| <&gcc GCC_USB30_SEC_MASTER_CLK>, |
| <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, |
| <&gcc GCC_USB30_SEC_SLEEP_CLK>, |
| <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB3_SEC_CLKREF_EN>; |
| clock-names = "cfg_noc", |
| "core", |
| "iface", |
| "sleep", |
| "mock_utmi", |
| "xo"; |
| |
| assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB30_SEC_MASTER_CLK>; |
| assigned-clock-rates = <19200000>, <200000000>; |
| |
| interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 13 IRQ_TYPE_EDGE_BOTH>, |
| <&pdc 12 IRQ_TYPE_EDGE_BOTH>; |
| interrupt-names = "hs_phy_irq", |
| "ss_phy_irq", |
| "dm_hs_phy_irq", |
| "dp_hs_phy_irq"; |
| |
| power-domains = <&gcc USB30_SEC_GDSC>; |
| |
| resets = <&gcc GCC_USB30_SEC_BCR>; |
| |
| usb_2_dwc3: usb@a800000 { |
| compatible = "snps,dwc3"; |
| reg = <0 0x0a800000 0 0xcd00>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| iommus = <&apps_smmu 0x20 0>; |
| snps,dis_u2_susphy_quirk; |
| snps,dis_enblslpm_quirk; |
| phys = <&usb_2_hsphy>, <&usb_2_ssphy>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| }; |
| }; |
| |
| venus: video-codec@aa00000 { |
| compatible = "qcom,sm8250-venus"; |
| reg = <0 0x0aa00000 0 0x100000>; |
| interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&videocc MVS0C_GDSC>, |
| <&videocc MVS0_GDSC>, |
| <&rpmhpd SM8250_MX>; |
| power-domain-names = "venus", "vcodec0", "mx"; |
| operating-points-v2 = <&venus_opp_table>; |
| |
| clocks = <&gcc GCC_VIDEO_AXI0_CLK>, |
| <&videocc VIDEO_CC_MVS0C_CLK>, |
| <&videocc VIDEO_CC_MVS0_CLK>; |
| clock-names = "iface", "core", "vcodec0_core"; |
| |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, |
| <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; |
| interconnect-names = "cpu-cfg", "video-mem"; |
| |
| iommus = <&apps_smmu 0x2100 0x0400>; |
| memory-region = <&video_mem>; |
| |
| resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, |
| <&videocc VIDEO_CC_MVS0C_CLK_ARES>; |
| reset-names = "bus", "core"; |
| |
| status = "disabled"; |
| |
| video-decoder { |
| compatible = "venus-decoder"; |
| }; |
| |
| video-encoder { |
| compatible = "venus-encoder"; |
| }; |
| |
| venus_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-720000000 { |
| opp-hz = /bits/ 64 <720000000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-1014000000 { |
| opp-hz = /bits/ 64 <1014000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| |
| opp-1098000000 { |
| opp-hz = /bits/ 64 <1098000000>; |
| required-opps = <&rpmhpd_opp_svs_l1>; |
| }; |
| |
| opp-1332000000 { |
| opp-hz = /bits/ 64 <1332000000>; |
| required-opps = <&rpmhpd_opp_nom>; |
| }; |
| }; |
| }; |
| |
| videocc: clock-controller@abf0000 { |
| compatible = "qcom,sm8250-videocc"; |
| reg = <0 0x0abf0000 0 0x10000>; |
| clocks = <&gcc GCC_VIDEO_AHB_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>, |
| <&rpmhcc RPMH_CXO_CLK_A>; |
| power-domains = <&rpmhpd SM8250_MMCX>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| cci0: cci@ac4f000 { |
| compatible = "qcom,sm8250-cci"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg = <0 0x0ac4f000 0 0x1000>; |
| interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; |
| power-domains = <&camcc TITAN_TOP_GDSC>; |
| |
| clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&camcc CAM_CC_CPAS_AHB_CLK>, |
| <&camcc CAM_CC_CCI_0_CLK>, |
| <&camcc CAM_CC_CCI_0_CLK_SRC>; |
| clock-names = "camnoc_axi", |
| "slow_ahb_src", |
| "cpas_ahb", |
| "cci", |
| "cci_src"; |
| |
| pinctrl-0 = <&cci0_default>; |
| pinctrl-1 = <&cci0_sleep>; |
| pinctrl-names = "default", "sleep"; |
| |
| status = "disabled"; |
| |
| cci0_i2c0: i2c-bus@0 { |
| reg = <0>; |
| clock-frequency = <1000000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| cci0_i2c1: i2c-bus@1 { |
| reg = <1>; |
| clock-frequency = <1000000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| cci1: cci@ac50000 { |
| compatible = "qcom,sm8250-cci"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg = <0 0x0ac50000 0 0x1000>; |
| interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; |
| power-domains = <&camcc TITAN_TOP_GDSC>; |
| |
| clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&camcc CAM_CC_CPAS_AHB_CLK>, |
| <&camcc CAM_CC_CCI_1_CLK>, |
| <&camcc CAM_CC_CCI_1_CLK_SRC>; |
| clock-names = "camnoc_axi", |
| "slow_ahb_src", |
| "cpas_ahb", |
| "cci", |
| "cci_src"; |
| |
| pinctrl-0 = <&cci1_default>; |
| pinctrl-1 = <&cci1_sleep>; |
| pinctrl-names = "default", "sleep"; |
| |
| status = "disabled"; |
| |
| cci1_i2c0: i2c-bus@0 { |
| reg = <0>; |
| clock-frequency = <1000000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| cci1_i2c1: i2c-bus@1 { |
| reg = <1>; |
| clock-frequency = <1000000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| camss: camss@ac6a000 { |
| compatible = "qcom,sm8250-camss"; |
| status = "disabled"; |
| |
| reg = <0 0xac6a000 0 0x2000>, |
| <0 0xac6c000 0 0x2000>, |
| <0 0xac6e000 0 0x1000>, |
| <0 0xac70000 0 0x1000>, |
| <0 0xac72000 0 0x1000>, |
| <0 0xac74000 0 0x1000>, |
| <0 0xacb4000 0 0xd000>, |
| <0 0xacc3000 0 0xd000>, |
| <0 0xacd9000 0 0x2200>, |
| <0 0xacdb200 0 0x2200>; |
| reg-names = "csiphy0", |
| "csiphy1", |
| "csiphy2", |
| "csiphy3", |
| "csiphy4", |
| "csiphy5", |
| "vfe0", |
| "vfe1", |
| "vfe_lite0", |
| "vfe_lite1"; |
| |
| interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "csiphy0", |
| "csiphy1", |
| "csiphy2", |
| "csiphy3", |
| "csiphy4", |
| "csiphy5", |
| "csid0", |
| "csid1", |
| "csid2", |
| "csid3", |
| "vfe0", |
| "vfe1", |
| "vfe_lite0", |
| "vfe_lite1"; |
| |
| power-domains = <&camcc IFE_0_GDSC>, |
| <&camcc IFE_1_GDSC>, |
| <&camcc TITAN_TOP_GDSC>; |
| |
| clocks = <&gcc GCC_CAMERA_AHB_CLK>, |
| <&gcc GCC_CAMERA_HF_AXI_CLK>, |
| <&gcc GCC_CAMERA_SF_AXI_CLK>, |
| <&camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, |
| <&camcc CAM_CC_CORE_AHB_CLK>, |
| <&camcc CAM_CC_CPAS_AHB_CLK>, |
| <&camcc CAM_CC_CSIPHY0_CLK>, |
| <&camcc CAM_CC_CSI0PHYTIMER_CLK>, |
| <&camcc CAM_CC_CSIPHY1_CLK>, |
| <&camcc CAM_CC_CSI1PHYTIMER_CLK>, |
| <&camcc CAM_CC_CSIPHY2_CLK>, |
| <&camcc CAM_CC_CSI2PHYTIMER_CLK>, |
| <&camcc CAM_CC_CSIPHY3_CLK>, |
| <&camcc CAM_CC_CSI3PHYTIMER_CLK>, |
| <&camcc CAM_CC_CSIPHY4_CLK>, |
| <&camcc CAM_CC_CSI4PHYTIMER_CLK>, |
| <&camcc CAM_CC_CSIPHY5_CLK>, |
| <&camcc CAM_CC_CSI5PHYTIMER_CLK>, |
| <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&camcc CAM_CC_IFE_0_AHB_CLK>, |
| <&camcc CAM_CC_IFE_0_AXI_CLK>, |
| <&camcc CAM_CC_IFE_0_CLK>, |
| <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, |
| <&camcc CAM_CC_IFE_0_CSID_CLK>, |
| <&camcc CAM_CC_IFE_0_AREG_CLK>, |
| <&camcc CAM_CC_IFE_1_AHB_CLK>, |
| <&camcc CAM_CC_IFE_1_AXI_CLK>, |
| <&camcc CAM_CC_IFE_1_CLK>, |
| <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, |
| <&camcc CAM_CC_IFE_1_CSID_CLK>, |
| <&camcc CAM_CC_IFE_1_AREG_CLK>, |
| <&camcc CAM_CC_IFE_LITE_AHB_CLK>, |
| <&camcc CAM_CC_IFE_LITE_AXI_CLK>, |
| <&camcc CAM_CC_IFE_LITE_CLK>, |
| <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, |
| <&camcc CAM_CC_IFE_LITE_CSID_CLK>; |
| |
| clock-names = "cam_ahb_clk", |
| "cam_hf_axi", |
| "cam_sf_axi", |
| "camnoc_axi", |
| "camnoc_axi_src", |
| "core_ahb", |
| "cpas_ahb", |
| "csiphy0", |
| "csiphy0_timer", |
| "csiphy1", |
| "csiphy1_timer", |
| "csiphy2", |
| "csiphy2_timer", |
| "csiphy3", |
| "csiphy3_timer", |
| "csiphy4", |
| "csiphy4_timer", |
| "csiphy5", |
| "csiphy5_timer", |
| "slow_ahb_src", |
| "vfe0_ahb", |
| "vfe0_axi", |
| "vfe0", |
| "vfe0_cphy_rx", |
| "vfe0_csid", |
| "vfe0_areg", |
| "vfe1_ahb", |
| "vfe1_axi", |
| "vfe1", |
| "vfe1_cphy_rx", |
| "vfe1_csid", |
| "vfe1_areg", |
| "vfe_lite_ahb", |
| "vfe_lite_axi", |
| "vfe_lite", |
| "vfe_lite_cphy_rx", |
| "vfe_lite_csid"; |
| |
| iommus = <&apps_smmu 0x800 0x400>, |
| <&apps_smmu 0x801 0x400>, |
| <&apps_smmu 0x840 0x400>, |
| <&apps_smmu 0x841 0x400>, |
| <&apps_smmu 0xc00 0x400>, |
| <&apps_smmu 0xc01 0x400>, |
| <&apps_smmu 0xc40 0x400>, |
| <&apps_smmu 0xc41 0x400>; |
| |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, |
| <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, |
| <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, |
| <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; |
| interconnect-names = "cam_ahb", |
| "cam_hf_0_mnoc", |
| "cam_sf_0_mnoc", |
| "cam_sf_icp_mnoc"; |
| }; |
| |
| camcc: clock-controller@ad00000 { |
| compatible = "qcom,sm8250-camcc"; |
| reg = <0 0x0ad00000 0 0x10000>; |
| clocks = <&gcc GCC_CAMERA_AHB_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>, |
| <&rpmhcc RPMH_CXO_CLK_A>, |
| <&sleep_clk>; |
| clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; |
| power-domains = <&rpmhpd SM8250_MMCX>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| status = "disabled"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| mdss: mdss@ae00000 { |
| compatible = "qcom,sm8250-mdss"; |
| reg = <0 0x0ae00000 0 0x1000>; |
| reg-names = "mdss"; |
| |
| interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, |
| <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; |
| interconnect-names = "mdp0-mem", "mdp1-mem"; |
| |
| power-domains = <&dispcc MDSS_GDSC>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&gcc GCC_DISP_HF_AXI_CLK>, |
| <&gcc GCC_DISP_SF_AXI_CLK>, |
| <&dispcc DISP_CC_MDSS_MDP_CLK>; |
| clock-names = "iface", "bus", "nrt_bus", "core"; |
| |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| iommus = <&apps_smmu 0x820 0x402>; |
| |
| status = "disabled"; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| mdss_mdp: display-controller@ae01000 { |
| compatible = "qcom,sm8250-dpu"; |
| reg = <0 0x0ae01000 0 0x8f000>, |
| <0 0x0aeb0000 0 0x2008>; |
| reg-names = "mdp", "vbif"; |
| |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&gcc GCC_DISP_HF_AXI_CLK>, |
| <&dispcc DISP_CC_MDSS_MDP_CLK>, |
| <&dispcc DISP_CC_MDSS_VSYNC_CLK>; |
| clock-names = "iface", "bus", "core", "vsync"; |
| |
| assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; |
| assigned-clock-rates = <19200000>; |
| |
| operating-points-v2 = <&mdp_opp_table>; |
| power-domains = <&rpmhpd SM8250_MMCX>; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| dpu_intf1_out: endpoint { |
| remote-endpoint = <&dsi0_in>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| dpu_intf2_out: endpoint { |
| remote-endpoint = <&dsi1_in>; |
| }; |
| }; |
| }; |
| |
| mdp_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-200000000 { |
| opp-hz = /bits/ 64 <200000000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| |
| opp-345000000 { |
| opp-hz = /bits/ 64 <345000000>; |
| required-opps = <&rpmhpd_opp_svs_l1>; |
| }; |
| |
| opp-460000000 { |
| opp-hz = /bits/ 64 <460000000>; |
| required-opps = <&rpmhpd_opp_nom>; |
| }; |
| }; |
| }; |
| |
| dsi0: dsi@ae94000 { |
| compatible = "qcom,mdss-dsi-ctrl"; |
| reg = <0 0x0ae94000 0 0x400>; |
| reg-names = "dsi_ctrl"; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <4>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, |
| <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, |
| <&dispcc DISP_CC_MDSS_PCLK0_CLK>, |
| <&dispcc DISP_CC_MDSS_ESC0_CLK>, |
| <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&gcc GCC_DISP_HF_AXI_CLK>; |
| clock-names = "byte", |
| "byte_intf", |
| "pixel", |
| "core", |
| "iface", |
| "bus"; |
| |
| assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; |
| assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; |
| |
| operating-points-v2 = <&dsi_opp_table>; |
| power-domains = <&rpmhpd SM8250_MMCX>; |
| |
| phys = <&dsi0_phy>; |
| phy-names = "dsi"; |
| |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| dsi0_in: endpoint { |
| remote-endpoint = <&dpu_intf1_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| dsi0_out: endpoint { |
| }; |
| }; |
| }; |
| |
| dsi_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-187500000 { |
| opp-hz = /bits/ 64 <187500000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| |
| opp-358000000 { |
| opp-hz = /bits/ 64 <358000000>; |
| required-opps = <&rpmhpd_opp_svs_l1>; |
| }; |
| }; |
| }; |
| |
| dsi0_phy: dsi-phy@ae94400 { |
| compatible = "qcom,dsi-phy-7nm"; |
| reg = <0 0x0ae94400 0 0x200>, |
| <0 0x0ae94600 0 0x280>, |
| <0 0x0ae94900 0 0x260>; |
| reg-names = "dsi_phy", |
| "dsi_phy_lane", |
| "dsi_pll"; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "iface", "ref"; |
| |
| status = "disabled"; |
| }; |
| |
| dsi1: dsi@ae96000 { |
| compatible = "qcom,mdss-dsi-ctrl"; |
| reg = <0 0x0ae96000 0 0x400>; |
| reg-names = "dsi_ctrl"; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <5>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, |
| <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, |
| <&dispcc DISP_CC_MDSS_PCLK1_CLK>, |
| <&dispcc DISP_CC_MDSS_ESC1_CLK>, |
| <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&gcc GCC_DISP_HF_AXI_CLK>; |
| clock-names = "byte", |
| "byte_intf", |
| "pixel", |
| "core", |
| "iface", |
| "bus"; |
| |
| assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; |
| assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; |
| |
| operating-points-v2 = <&dsi_opp_table>; |
| power-domains = <&rpmhpd SM8250_MMCX>; |
| |
| phys = <&dsi1_phy>; |
| phy-names = "dsi"; |
| |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| dsi1_in: endpoint { |
| remote-endpoint = <&dpu_intf2_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| dsi1_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| dsi1_phy: dsi-phy@ae96400 { |
| compatible = "qcom,dsi-phy-7nm"; |
| reg = <0 0x0ae96400 0 0x200>, |
| <0 0x0ae96600 0 0x280>, |
| <0 0x0ae96900 0 0x260>; |
| reg-names = "dsi_phy", |
| "dsi_phy_lane", |
| "dsi_pll"; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "iface", "ref"; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| dispcc: clock-controller@af00000 { |
| compatible = "qcom,sm8250-dispcc"; |
| reg = <0 0x0af00000 0 0x10000>; |
| power-domains = <&rpmhpd SM8250_MMCX>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&dsi0_phy 0>, |
| <&dsi0_phy 1>, |
| <&dsi1_phy 0>, |
| <&dsi1_phy 1>, |
| <&dp_phy 0>, |
| <&dp_phy 1>; |
| clock-names = "bi_tcxo", |
| "dsi0_phy_pll_out_byteclk", |
| "dsi0_phy_pll_out_dsiclk", |
| "dsi1_phy_pll_out_byteclk", |
| "dsi1_phy_pll_out_dsiclk", |
| "dp_phy_pll_link_clk", |
| "dp_phy_pll_vco_div_clk"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| pdc: interrupt-controller@b220000 { |
| compatible = "qcom,sm8250-pdc", "qcom,pdc"; |
| reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; |
| qcom,pdc-ranges = <0 480 94>, <94 609 31>, |
| <125 63 1>, <126 716 12>; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&intc>; |
| interrupt-controller; |
| }; |
| |
| tsens0: thermal-sensor@c263000 { |
| compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; |
| reg = <0 0x0c263000 0 0x1ff>, /* TM */ |
| <0 0x0c222000 0 0x1ff>; /* SROT */ |
| #qcom,sensors = <16>; |
| interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "uplow", "critical"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| tsens1: thermal-sensor@c265000 { |
| compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; |
| reg = <0 0x0c265000 0 0x1ff>, /* TM */ |
| <0 0x0c223000 0 0x1ff>; /* SROT */ |
| #qcom,sensors = <9>; |
| interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "uplow", "critical"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| aoss_qmp: power-controller@c300000 { |
| compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; |
| reg = <0 0x0c300000 0 0x400>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_AOP |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_AOP |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| |
| #clock-cells = <0>; |
| }; |
| |
| sram@c3f0000 { |
| compatible = "qcom,rpmh-stats"; |
| reg = <0 0x0c3f0000 0 0x400>; |
| }; |
| |
| spmi_bus: spmi@c440000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0x0 0x0c440000 0x0 0x0001100>, |
| <0x0 0x0c600000 0x0 0x2000000>, |
| <0x0 0x0e600000 0x0 0x0100000>, |
| <0x0 0x0e700000 0x0 0x00a0000>, |
| <0x0 0x0c40a000 0x0 0x0026000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| }; |
| |
| tlmm: pinctrl@f100000 { |
| compatible = "qcom,sm8250-pinctrl"; |
| reg = <0 0x0f100000 0 0x300000>, |
| <0 0x0f500000 0 0x300000>, |
| <0 0x0f900000 0 0x300000>; |
| reg-names = "west", "south", "north"; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 181>; |
| wakeup-parent = <&pdc>; |
| |
| cci0_default: cci0-default { |
| cci0_i2c0_default: cci0-i2c0-default { |
| /* SDA, SCL */ |
| pins = "gpio101", "gpio102"; |
| function = "cci_i2c"; |
| |
| bias-pull-up; |
| drive-strength = <2>; /* 2 mA */ |
| }; |
| |
| cci0_i2c1_default: cci0-i2c1-default { |
| /* SDA, SCL */ |
| pins = "gpio103", "gpio104"; |
| function = "cci_i2c"; |
| |
| bias-pull-up; |
| drive-strength = <2>; /* 2 mA */ |
| }; |
| }; |
| |
| cci0_sleep: cci0-sleep { |
| cci0_i2c0_sleep: cci0-i2c0-sleep { |
| /* SDA, SCL */ |
| pins = "gpio101", "gpio102"; |
| function = "cci_i2c"; |
| |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; |
| }; |
| |
| cci0_i2c1_sleep: cci0-i2c1-sleep { |
| /* SDA, SCL */ |
| pins = "gpio103", "gpio104"; |
| function = "cci_i2c"; |
| |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; |
| }; |
| }; |
| |
| cci1_default: cci1-default { |
| cci1_i2c0_default: cci1-i2c0-default { |
| /* SDA, SCL */ |
| pins = "gpio105","gpio106"; |
| function = "cci_i2c"; |
| |
| bias-pull-up; |
| drive-strength = <2>; /* 2 mA */ |
| }; |
| |
| cci1_i2c1_default: cci1-i2c1-default { |
| /* SDA, SCL */ |
| pins = "gpio107","gpio108"; |
| function = "cci_i2c"; |
| |
| bias-pull-up; |
| drive-strength = <2>; /* 2 mA */ |
| }; |
| }; |
| |
| cci1_sleep: cci1-sleep { |
| cci1_i2c0_sleep: cci1-i2c0-sleep { |
| /* SDA, SCL */ |
| pins = "gpio105","gpio106"; |
| function = "cci_i2c"; |
| |
| bias-pull-down; |
| drive-strength = <2>; /* 2 mA */ |
| }; |
| |
| cci1_i2c1_sleep: cci1-i2c1-sleep { |
| /* SDA, SCL */ |
| pins = "gpio107","gpio108"; |
| function = "cci_i2c"; |
| |
| bias-pull-down; |
| drive-strength = <2>; /* 2 mA */ |
| }; |
| }; |
| |
| pri_mi2s_active: pri-mi2s-active { |
| sclk { |
| pins = "gpio138"; |
| function = "mi2s0_sck"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| |
| ws { |
| pins = "gpio141"; |
| function = "mi2s0_ws"; |
| drive-strength = <8>; |
| output-high; |
| }; |
| |
| data0 { |
| pins = "gpio139"; |
| function = "mi2s0_data0"; |
| drive-strength = <8>; |
| bias-disable; |
| output-high; |
| }; |
| |
| data1 { |
| pins = "gpio140"; |
| function = "mi2s0_data1"; |
| drive-strength = <8>; |
| output-high; |
| }; |
| }; |
| |
| qup_i2c0_default: qup-i2c0-default { |
| mux { |
| pins = "gpio28", "gpio29"; |
| function = "qup0"; |
| }; |
| |
| config { |
| pins = "gpio28", "gpio29"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c1_default: qup-i2c1-default { |
| pinmux { |
| pins = "gpio4", "gpio5"; |
| function = "qup1"; |
| }; |
| |
| config { |
| pins = "gpio4", "gpio5"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c2_default: qup-i2c2-default { |
| mux { |
| pins = "gpio115", "gpio116"; |
| function = "qup2"; |
| }; |
| |
| config { |
| pins = "gpio115", "gpio116"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c3_default: qup-i2c3-default { |
| mux { |
| pins = "gpio119", "gpio120"; |
| function = "qup3"; |
| }; |
| |
| config { |
| pins = "gpio119", "gpio120"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c4_default: qup-i2c4-default { |
| mux { |
| pins = "gpio8", "gpio9"; |
| function = "qup4"; |
| }; |
| |
| config { |
| pins = "gpio8", "gpio9"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c5_default: qup-i2c5-default { |
| mux { |
| pins = "gpio12", "gpio13"; |
| function = "qup5"; |
| }; |
| |
| config { |
| pins = "gpio12", "gpio13"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c6_default: qup-i2c6-default { |
| mux { |
| pins = "gpio16", "gpio17"; |
| function = "qup6"; |
| }; |
| |
| config { |
| pins = "gpio16", "gpio17"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c7_default: qup-i2c7-default { |
| mux { |
| pins = "gpio20", "gpio21"; |
| function = "qup7"; |
| }; |
| |
| config { |
| pins = "gpio20", "gpio21"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c8_default: qup-i2c8-default { |
| mux { |
| pins = "gpio24", "gpio25"; |
| function = "qup8"; |
| }; |
| |
| config { |
| pins = "gpio24", "gpio25"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c9_default: qup-i2c9-default { |
| mux { |
| pins = "gpio125", "gpio126"; |
| function = "qup9"; |
| }; |
| |
| config { |
| pins = "gpio125", "gpio126"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c10_default: qup-i2c10-default { |
| mux { |
| pins = "gpio129", "gpio130"; |
| function = "qup10"; |
| }; |
| |
| config { |
| pins = "gpio129", "gpio130"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c11_default: qup-i2c11-default { |
| mux { |
| pins = "gpio60", "gpio61"; |
| function = "qup11"; |
| }; |
| |
| config { |
| pins = "gpio60", "gpio61"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c12_default: qup-i2c12-default { |
| mux { |
| pins = "gpio32", "gpio33"; |
| function = "qup12"; |
| }; |
| |
| config { |
| pins = "gpio32", "gpio33"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c13_default: qup-i2c13-default { |
| mux { |
| pins = "gpio36", "gpio37"; |
| function = "qup13"; |
| }; |
| |
| config { |
| pins = "gpio36", "gpio37"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c14_default: qup-i2c14-default { |
| mux { |
| pins = "gpio40", "gpio41"; |
| function = "qup14"; |
| }; |
| |
| config { |
| pins = "gpio40", "gpio41"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c15_default: qup-i2c15-default { |
| mux { |
| pins = "gpio44", "gpio45"; |
| function = "qup15"; |
| }; |
| |
| config { |
| pins = "gpio44", "gpio45"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c16_default: qup-i2c16-default { |
| mux { |
| pins = "gpio48", "gpio49"; |
| function = "qup16"; |
| }; |
| |
| config { |
| pins = "gpio48", "gpio49"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c17_default: qup-i2c17-default { |
| mux { |
| pins = "gpio52", "gpio53"; |
| function = "qup17"; |
| }; |
| |
| config { |
| pins = "gpio52", "gpio53"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c18_default: qup-i2c18-default { |
| mux { |
| pins = "gpio56", "gpio57"; |
| function = "qup18"; |
| }; |
| |
| config { |
| pins = "gpio56", "gpio57"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_i2c19_default: qup-i2c19-default { |
| mux { |
| pins = "gpio0", "gpio1"; |
| function = "qup19"; |
| }; |
| |
| config { |
| pins = "gpio0", "gpio1"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qup_spi0_cs: qup-spi0-cs { |
| pins = "gpio31"; |
| function = "qup0"; |
| }; |
| |
| qup_spi0_cs_gpio: qup-spi0-cs-gpio { |
| pins = "gpio31"; |
| function = "gpio"; |
| }; |
| |
| qup_spi0_data_clk: qup-spi0-data-clk { |
| pins = "gpio28", "gpio29", |
| "gpio30"; |
| function = "qup0"; |
| }; |
| |
| qup_spi1_cs: qup-spi1-cs { |
| pins = "gpio7"; |
| function = "qup1"; |
| }; |
| |
| qup_spi1_cs_gpio: qup-spi1-cs-gpio { |
| pins = "gpio7"; |
| function = "gpio"; |
| }; |
| |
| qup_spi1_data_clk: qup-spi1-data-clk { |
| pins = "gpio4", "gpio5", |
| "gpio6"; |
| function = "qup1"; |
| }; |
| |
| qup_spi2_cs: qup-spi2-cs { |
| pins = "gpio118"; |
| function = "qup2"; |
| }; |
| |
| qup_spi2_cs_gpio: qup-spi2-cs-gpio { |
| pins = "gpio118"; |
| function = "gpio"; |
| }; |
| |
| qup_spi2_data_clk: qup-spi2-data-clk { |
| pins = "gpio115", "gpio116", |
| "gpio117"; |
| function = "qup2"; |
| }; |
| |
| qup_spi3_cs: qup-spi3-cs { |
| pins = "gpio122"; |
| function = "qup3"; |
| }; |
| |
| qup_spi3_cs_gpio: qup-spi3-cs-gpio { |
| pins = "gpio122"; |
| function = "gpio"; |
| }; |
| |
| qup_spi3_data_clk: qup-spi3-data-clk { |
| pins = "gpio119", "gpio120", |
| "gpio121"; |
| function = "qup3"; |
| }; |
| |
| qup_spi4_cs: qup-spi4-cs { |
| pins = "gpio11"; |
| function = "qup4"; |
| }; |
| |
| qup_spi4_cs_gpio: qup-spi4-cs-gpio { |
| pins = "gpio11"; |
| function = "gpio"; |
| }; |
| |
| qup_spi4_data_clk: qup-spi4-data-clk { |
| pins = "gpio8", "gpio9", |
| "gpio10"; |
| function = "qup4"; |
| }; |
| |
| qup_spi5_cs: qup-spi5-cs { |
| pins = "gpio15"; |
| function = "qup5"; |
| }; |
| |
| qup_spi5_cs_gpio: qup-spi5-cs-gpio { |
| pins = "gpio15"; |
| function = "gpio"; |
| }; |
| |
| qup_spi5_data_clk: qup-spi5-data-clk { |
| pins = "gpio12", "gpio13", |
| "gpio14"; |
| function = "qup5"; |
| }; |
| |
| qup_spi6_cs: qup-spi6-cs { |
| pins = "gpio19"; |
| function = "qup6"; |
| }; |
| |
| qup_spi6_cs_gpio: qup-spi6-cs-gpio { |
| pins = "gpio19"; |
| function = "gpio"; |
| }; |
| |
| qup_spi6_data_clk: qup-spi6-data-clk { |
| pins = "gpio16", "gpio17", |
| "gpio18"; |
| function = "qup6"; |
| }; |
| |
| qup_spi7_cs: qup-spi7-cs { |
| pins = "gpio23"; |
| function = "qup7"; |
| }; |
| |
| qup_spi7_cs_gpio: qup-spi7-cs-gpio { |
| pins = "gpio23"; |
| function = "gpio"; |
| }; |
| |
| qup_spi7_data_clk: qup-spi7-data-clk { |
| pins = "gpio20", "gpio21", |
| "gpio22"; |
| function = "qup7"; |
| }; |
| |
| qup_spi8_cs: qup-spi8-cs { |
| pins = "gpio27"; |
| function = "qup8"; |
| }; |
| |
| qup_spi8_cs_gpio: qup-spi8-cs-gpio { |
| pins = "gpio27"; |
| function = "gpio"; |
| }; |
| |
| qup_spi8_data_clk: qup-spi8-data-clk { |
| pins = "gpio24", "gpio25", |
| "gpio26"; |
| function = "qup8"; |
| }; |
| |
| qup_spi9_cs: qup-spi9-cs { |
| pins = "gpio128"; |
| function = "qup9"; |
| }; |
| |
| qup_spi9_cs_gpio: qup-spi9-cs-gpio { |
| pins = "gpio128"; |
| function = "gpio"; |
| }; |
| |
| qup_spi9_data_clk: qup-spi9-data-clk { |
| pins = "gpio125", "gpio126", |
| "gpio127"; |
| function = "qup9"; |
| }; |
| |
| qup_spi10_cs: qup-spi10-cs { |
| pins = "gpio132"; |
| function = "qup10"; |
| }; |
| |
| qup_spi10_cs_gpio: qup-spi10-cs-gpio { |
| pins = "gpio132"; |
| function = "gpio"; |
| }; |
| |
| qup_spi10_data_clk: qup-spi10-data-clk { |
| pins = "gpio129", "gpio130", |
| "gpio131"; |
| function = "qup10"; |
| }; |
| |
| qup_spi11_cs: qup-spi11-cs { |
| pins = "gpio63"; |
| function = "qup11"; |
| }; |
| |
| qup_spi11_cs_gpio: qup-spi11-cs-gpio { |
| pins = "gpio63"; |
| function = "gpio"; |
| }; |
| |
| qup_spi11_data_clk: qup-spi11-data-clk { |
| pins = "gpio60", "gpio61", |
| "gpio62"; |
| function = "qup11"; |
| }; |
| |
| qup_spi12_cs: qup-spi12-cs { |
| pins = "gpio35"; |
| function = "qup12"; |
| }; |
| |
| qup_spi12_cs_gpio: qup-spi12-cs-gpio { |
| pins = "gpio35"; |
| function = "gpio"; |
| }; |
| |
| qup_spi12_data_clk: qup-spi12-data-clk { |
| pins = "gpio32", "gpio33", |
| "gpio34"; |
| function = "qup12"; |
| }; |
| |
| qup_spi13_cs: qup-spi13-cs { |
| pins = "gpio39"; |
| function = "qup13"; |
| }; |
| |
| qup_spi13_cs_gpio: qup-spi13-cs-gpio { |
| pins = "gpio39"; |
| function = "gpio"; |
| }; |
| |
| qup_spi13_data_clk: qup-spi13-data-clk { |
| pins = "gpio36", "gpio37", |
| "gpio38"; |
| function = "qup13"; |
| }; |
| |
| qup_spi14_cs: qup-spi14-cs { |
| pins = "gpio43"; |
| function = "qup14"; |
| }; |
| |
| qup_spi14_cs_gpio: qup-spi14-cs-gpio { |
| pins = "gpio43"; |
| function = "gpio"; |
| }; |
| |
| qup_spi14_data_clk: qup-spi14-data-clk { |
| pins = "gpio40", "gpio41", |
| "gpio42"; |
| function = "qup14"; |
| }; |
| |
| qup_spi15_cs: qup-spi15-cs { |
| pins = "gpio47"; |
| function = "qup15"; |
| }; |
| |
| qup_spi15_cs_gpio: qup-spi15-cs-gpio { |
| pins = "gpio47"; |
| function = "gpio"; |
| }; |
| |
| qup_spi15_data_clk: qup-spi15-data-clk { |
| pins = "gpio44", "gpio45", |
| "gpio46"; |
| function = "qup15"; |
| }; |
| |
| qup_spi16_cs: qup-spi16-cs { |
| pins = "gpio51"; |
| function = "qup16"; |
| }; |
| |
| qup_spi16_cs_gpio: qup-spi16-cs-gpio { |
| pins = "gpio51"; |
| function = "gpio"; |
| }; |
| |
| qup_spi16_data_clk: qup-spi16-data-clk { |
| pins = "gpio48", "gpio49", |
| "gpio50"; |
| function = "qup16"; |
| }; |
| |
| qup_spi17_cs: qup-spi17-cs { |
| pins = "gpio55"; |
| function = "qup17"; |
| }; |
| |
| qup_spi17_cs_gpio: qup-spi17-cs-gpio { |
| pins = "gpio55"; |
| function = "gpio"; |
| }; |
| |
| qup_spi17_data_clk: qup-spi17-data-clk { |
| pins = "gpio52", "gpio53", |
| "gpio54"; |
| function = "qup17"; |
| }; |
| |
| qup_spi18_cs: qup-spi18-cs { |
| pins = "gpio59"; |
| function = "qup18"; |
| }; |
| |
| qup_spi18_cs_gpio: qup-spi18-cs-gpio { |
| pins = "gpio59"; |
| function = "gpio"; |
| }; |
| |
| qup_spi18_data_clk: qup-spi18-data-clk { |
| pins = "gpio56", "gpio57", |
| "gpio58"; |
| function = "qup18"; |
| }; |
| |
| qup_spi19_cs: qup-spi19-cs { |
| pins = "gpio3"; |
| function = "qup19"; |
| }; |
| |
| qup_spi19_cs_gpio: qup-spi19-cs-gpio { |
| pins = "gpio3"; |
| function = "gpio"; |
| }; |
| |
| qup_spi19_data_clk: qup-spi19-data-clk { |
| pins = "gpio0", "gpio1", |
| "gpio2"; |
| function = "qup19"; |
| }; |
| |
| qup_uart2_default: qup-uart2-default { |
| mux { |
| pins = "gpio117", "gpio118"; |
| function = "qup2"; |
| }; |
| }; |
| |
| qup_uart6_default: qup-uart6-default { |
| mux { |
| pins = "gpio16", "gpio17", |
| "gpio18", "gpio19"; |
| function = "qup6"; |
| }; |
| }; |
| |
| qup_uart12_default: qup-uart12-default { |
| mux { |
| pins = "gpio34", "gpio35"; |
| function = "qup12"; |
| }; |
| }; |
| |
| qup_uart17_default: qup-uart17-default { |
| mux { |
| pins = "gpio52", "gpio53", |
| "gpio54", "gpio55"; |
| function = "qup17"; |
| }; |
| }; |
| |
| qup_uart18_default: qup-uart18-default { |
| mux { |
| pins = "gpio58", "gpio59"; |
| function = "qup18"; |
| }; |
| }; |
| |
| tert_mi2s_active: tert-mi2s-active { |
| sck { |
| pins = "gpio133"; |
| function = "mi2s2_sck"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| |
| data0 { |
| pins = "gpio134"; |
| function = "mi2s2_data0"; |
| drive-strength = <8>; |
| bias-disable; |
| output-high; |
| }; |
| |
| ws { |
| pins = "gpio135"; |
| function = "mi2s2_ws"; |
| drive-strength = <8>; |
| output-high; |
| }; |
| }; |
| |
| sdc2_sleep_state: sdc2-sleep { |
| clk { |
| pins = "sdc2_clk"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| cmd { |
| pins = "sdc2_cmd"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| data { |
| pins = "sdc2_data"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| |
| pcie0_default_state: pcie0-default { |
| perst { |
| pins = "gpio79"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| |
| clkreq { |
| pins = "gpio80"; |
| function = "pci_e0"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| wake { |
| pins = "gpio81"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| |
| pcie1_default_state: pcie1-default { |
| perst { |
| pins = "gpio82"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| |
| clkreq { |
| pins = "gpio83"; |
| function = "pci_e1"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| wake { |
| pins = "gpio84"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| |
| pcie2_default_state: pcie2-default { |
| perst { |
| pins = "gpio85"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| |
| clkreq { |
| pins = "gpio86"; |
| function = "pci_e2"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| wake { |
| pins = "gpio87"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| }; |
| |
| apps_smmu: iommu@15000000 { |
| compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; |
| reg = <0 0x15000000 0 0x100000>; |
| #iommu-cells = <2>; |
| #global-interrupts = <2>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| adsp: remoteproc@17300000 { |
| compatible = "qcom,sm8250-adsp-pas"; |
| reg = <0 0x17300000 0 0x100>; |
| |
| interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, |
| <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", |
| "handover", "stop-ack"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| |
| power-domains = <&rpmhpd SM8250_LCX>, |
| <&rpmhpd SM8250_LMX>; |
| power-domain-names = "lcx", "lmx"; |
| |
| memory-region = <&adsp_mem>; |
| |
| qcom,qmp = <&aoss_qmp>; |
| |
| qcom,smem-states = <&smp2p_adsp_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| status = "disabled"; |
| |
| glink-edge { |
| interrupts-extended = <&ipcc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| |
| label = "lpass"; |
| qcom,remote-pid = <2>; |
| |
| apr { |
| compatible = "qcom,apr-v2"; |
| qcom,glink-channels = "apr_audio_svc"; |
| qcom,domain = <APR_DOMAIN_ADSP>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| apr-service@3 { |
| reg = <APR_SVC_ADSP_CORE>; |
| compatible = "qcom,q6core"; |
| qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
| }; |
| |
| q6afe: apr-service@4 { |
| compatible = "qcom,q6afe"; |
| reg = <APR_SVC_AFE>; |
| qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
| q6afedai: dais { |
| compatible = "qcom,q6afe-dais"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #sound-dai-cells = <1>; |
| }; |
| |
| q6afecc: cc { |
| compatible = "qcom,q6afe-clocks"; |
| #clock-cells = <2>; |
| }; |
| }; |
| |
| q6asm: apr-service@7 { |
| compatible = "qcom,q6asm"; |
| reg = <APR_SVC_ASM>; |
| qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
| q6asmdai: dais { |
| compatible = "qcom,q6asm-dais"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #sound-dai-cells = <1>; |
| iommus = <&apps_smmu 0x1801 0x0>; |
| }; |
| }; |
| |
| q6adm: apr-service@8 { |
| compatible = "qcom,q6adm"; |
| reg = <APR_SVC_ADM>; |
| qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
| q6routing: routing { |
| compatible = "qcom,q6adm-routing"; |
| #sound-dai-cells = <0>; |
| }; |
| }; |
| }; |
| |
| fastrpc { |
| compatible = "qcom,fastrpc"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| label = "adsp"; |
| qcom,non-secure-domain; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compute-cb@3 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <3>; |
| iommus = <&apps_smmu 0x1803 0x0>; |
| }; |
| |
| compute-cb@4 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <4>; |
| iommus = <&apps_smmu 0x1804 0x0>; |
| }; |
| |
| compute-cb@5 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <5>; |
| iommus = <&apps_smmu 0x1805 0x0>; |
| }; |
| }; |
| }; |
| }; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ |
| <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| watchdog@17c10000 { |
| compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; |
| reg = <0 0x17c10000 0 0x1000>; |
| clocks = <&sleep_clk>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| timer@17c20000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0x20000000>; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x0 0x17c20000 0x0 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@17c21000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c21000 0x1000>, |
| <0x17c22000 0x1000>; |
| }; |
| |
| frame@17c23000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c23000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c25000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c25000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c27000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c27000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c29000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c29000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c2b000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c2b000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c2d000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c2d000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| apps_rsc: rsc@18200000 { |
| label = "apps_rsc"; |
| compatible = "qcom,rpmh-rsc"; |
| reg = <0x0 0x18200000 0x0 0x10000>, |
| <0x0 0x18210000 0x0 0x10000>, |
| <0x0 0x18220000 0x0 0x10000>; |
| reg-names = "drv-0", "drv-1", "drv-2"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,tcs-offset = <0xd00>; |
| qcom,drv-id = <2>; |
| qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, |
| <WAKE_TCS 3>, <CONTROL_TCS 1>; |
| |
| rpmhcc: clock-controller { |
| compatible = "qcom,sm8250-rpmh-clk"; |
| #clock-cells = <1>; |
| clock-names = "xo"; |
| clocks = <&xo_board>; |
| }; |
| |
| rpmhpd: power-controller { |
| compatible = "qcom,sm8250-rpmhpd"; |
| #power-domain-cells = <1>; |
| operating-points-v2 = <&rpmhpd_opp_table>; |
| |
| rpmhpd_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| rpmhpd_opp_ret: opp1 { |
| opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| }; |
| |
| rpmhpd_opp_min_svs: opp2 { |
| opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
| }; |
| |
| rpmhpd_opp_low_svs: opp3 { |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
| }; |
| |
| rpmhpd_opp_svs: opp4 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
| }; |
| |
| rpmhpd_opp_svs_l1: opp5 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| }; |
| |
| rpmhpd_opp_nom: opp6 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
| }; |
| |
| rpmhpd_opp_nom_l1: opp7 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| }; |
| |
| rpmhpd_opp_nom_l2: opp8 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; |
| }; |
| |
| rpmhpd_opp_turbo: opp9 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
| }; |
| |
| rpmhpd_opp_turbo_l1: opp10 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
| }; |
| }; |
| }; |
| |
| apps_bcm_voter: bcm-voter { |
| compatible = "qcom,bcm-voter"; |
| }; |
| }; |
| |
| epss_l3: interconnect@18590000 { |
| compatible = "qcom,sm8250-epss-l3"; |
| reg = <0 0x18590000 0 0x1000>; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; |
| clock-names = "xo", "alternate"; |
| |
| #interconnect-cells = <1>; |
| }; |
| |
| cpufreq_hw: cpufreq@18591000 { |
| compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; |
| reg = <0 0x18591000 0 0x1000>, |
| <0 0x18592000 0 0x1000>, |
| <0 0x18593000 0 0x1000>; |
| reg-names = "freq-domain0", "freq-domain1", |
| "freq-domain2"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; |
| clock-names = "xo", "alternate"; |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; |
| #freq-domain-cells = <1>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| thermal-zones { |
| cpu0-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 1>; |
| |
| trips { |
| cpu0_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu0_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu0_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu0_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu0_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu1-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 2>; |
| |
| trips { |
| cpu1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu1_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu1_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu1_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu1_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu2-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 3>; |
| |
| trips { |
| cpu2_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu2_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu2_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu2_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu2_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu3-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 4>; |
| |
| trips { |
| cpu3_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu3_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu3_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu3_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu3_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu4-top-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 7>; |
| |
| trips { |
| cpu4_top_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu4_top_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu4_top_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu4_top_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu4_top_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu5-top-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 8>; |
| |
| trips { |
| cpu5_top_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu5_top_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu5_top_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu5_top_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu5_top_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu6-top-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 9>; |
| |
| trips { |
| cpu6_top_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu6_top_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu6_top_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu6_top_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu6_top_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu7-top-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 10>; |
| |
| trips { |
| cpu7_top_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu7_top_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu7_top_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu7_top_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu7_top_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu4-bottom-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 11>; |
| |
| trips { |
| cpu4_bottom_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu4_bottom_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu4_bottom_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu4_bottom_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu4_bottom_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu5-bottom-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 12>; |
| |
| trips { |
| cpu5_bottom_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu5_bottom_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu5_bottom_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu5_bottom_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu5_bottom_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu6-bottom-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 13>; |
| |
| trips { |
| cpu6_bottom_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu6_bottom_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu6_bottom_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu6_bottom_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu6_bottom_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu7-bottom-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 14>; |
| |
| trips { |
| cpu7_bottom_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu7_bottom_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu7_bottom_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu7_bottom_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu7_bottom_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| aoss0-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 0>; |
| |
| trips { |
| aoss0_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| cluster0-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 5>; |
| |
| trips { |
| cluster0_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| cluster0_crit: cluster0_crit { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| cluster1-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 6>; |
| |
| trips { |
| cluster1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| cluster1_crit: cluster1_crit { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| gpu-top-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 15>; |
| |
| trips { |
| gpu1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| aoss1-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens1 0>; |
| |
| trips { |
| aoss1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| wlan-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens1 1>; |
| |
| trips { |
| wlan_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| video-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens1 2>; |
| |
| trips { |
| video_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| mem-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens1 3>; |
| |
| trips { |
| mem_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| q6-hvx-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens1 4>; |
| |
| trips { |
| q6_hvx_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| camera-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens1 5>; |
| |
| trips { |
| camera_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| compute-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens1 6>; |
| |
| trips { |
| compute_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| npu-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens1 7>; |
| |
| trips { |
| npu_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| gpu-bottom-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens1 8>; |
| |
| trips { |
| gpu2_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| }; |
| }; |
