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linux / linux / kernel / git / torvalds / linux / refs/tags/v2.6.12-rc5 / . / drivers / scsi / advansys.c
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#define ASC_VERSION "3.3K" /* AdvanSys Driver Version */
/*
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-2000 Advanced System Products, Inc.
* Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*
* As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
* changed its name to ConnectCom Solutions, Inc.
*
*/
/*
Documentation for the AdvanSys Driver
A. Linux Kernels Supported by this Driver
B. Adapters Supported by this Driver
C. Linux source files modified by AdvanSys Driver
D. Source Comments
E. Driver Compile Time Options and Debugging
F. Driver LILO Option
G. Tests to run before releasing new driver
H. Release History
I. Known Problems/Fix List
J. Credits (Chronological Order)
A. Linux Kernels Supported by this Driver
This driver has been tested in the following Linux kernels: v2.2.18
v2.4.0. The driver is supported on v2.2 and v2.4 kernels and on x86,
alpha, and PowerPC platforms.
B. Adapters Supported by this Driver
AdvanSys (Advanced System Products, Inc.) manufactures the following
RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
(8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
transfer) SCSI Host Adapters for the PCI bus.
The CDB counts below indicate the number of SCSI CDB (Command
Descriptor Block) requests that can be stored in the RISC chip
cache and board LRAM. A CDB is a single SCSI command. The driver
detect routine will display the number of CDBs available for each
adapter detected. The number of CDBs used by the driver can be
lowered in the BIOS by changing the 'Host Queue Size' adapter setting.
Laptop Products:
ABP-480 - Bus-Master CardBus (16 CDB) (2.4 kernel and greater)
Connectivity Products:
ABP510/5150 - Bus-Master ISA (240 CDB)
ABP5140 - Bus-Master ISA PnP (16 CDB)
ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
ABP902/3902 - Bus-Master PCI (16 CDB)
ABP3905 - Bus-Master PCI (16 CDB)
ABP915 - Bus-Master PCI (16 CDB)
ABP920 - Bus-Master PCI (16 CDB)
ABP3922 - Bus-Master PCI (16 CDB)
ABP3925 - Bus-Master PCI (16 CDB)
ABP930 - Bus-Master PCI (16 CDB)
ABP930U - Bus-Master PCI Ultra (16 CDB)
ABP930UA - Bus-Master PCI Ultra (16 CDB)
ABP960 - Bus-Master PCI MAC/PC (16 CDB)
ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB)
Single Channel Products:
ABP542 - Bus-Master ISA with floppy (240 CDB)
ABP742 - Bus-Master EISA (240 CDB)
ABP842 - Bus-Master VL (240 CDB)
ABP940 - Bus-Master PCI (240 CDB)
ABP940U - Bus-Master PCI Ultra (240 CDB)
ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
ABP970 - Bus-Master PCI MAC/PC (240 CDB)
ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
ABP3960UA - Bus-Master PCI MAC/PC Ultra (240 CDB)
ABP940UW/3940UW - Bus-Master PCI Ultra-Wide (253 CDB)
ABP970UW - Bus-Master PCI MAC/PC Ultra-Wide (253 CDB)
ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
Multi-Channel Products:
ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel)
ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel)
ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB Per Channel)
ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide and Ultra-Wide (253 CDB)
ABP3950U3W - Bus-Master PCI Dual LVD2/Ultra3-Wide (253 CDB)
C. Linux source files modified by AdvanSys Driver
This section for historical purposes documents the changes
originally made to the Linux kernel source to add the advansys
driver. As Linux has changed some of these files have also
been modified.
1. linux/arch/i386/config.in:
bool 'AdvanSys SCSI support' CONFIG_SCSI_ADVANSYS y
2. linux/drivers/scsi/hosts.c:
#ifdef CONFIG_SCSI_ADVANSYS
#include "advansys.h"
#endif
and after "static Scsi_Host_Template builtin_scsi_hosts[] =":
#ifdef CONFIG_SCSI_ADVANSYS
ADVANSYS,
#endif
3. linux/drivers/scsi/Makefile:
ifdef CONFIG_SCSI_ADVANSYS
SCSI_SRCS := $(SCSI_SRCS) advansys.c
SCSI_OBJS := $(SCSI_OBJS) advansys.o
else
SCSI_MODULE_OBJS := $(SCSI_MODULE_OBJS) advansys.o
endif
4. linux/init/main.c:
extern void advansys_setup(char *str, int *ints);
and add the following lines to the bootsetups[] array.
#ifdef CONFIG_SCSI_ADVANSYS
{ "advansys=", advansys_setup },
#endif
D. Source Comments
1. Use tab stops set to 4 for the source files. For vi use 'se tabstops=4'.
2. This driver should be maintained in multiple files. But to make
it easier to include with Linux and to follow Linux conventions,
the whole driver is maintained in the source files advansys.h and
advansys.c. In this file logical sections of the driver begin with
a comment that contains '---'. The following are the logical sections
of the driver below.
--- Linux Version
--- Linux Include File
--- Driver Options
--- Debugging Header
--- Asc Library Constants and Macros
--- Adv Library Constants and Macros
--- Driver Constants and Macros
--- Driver Structures
--- Driver Data
--- Driver Function Prototypes
--- Linux 'Scsi_Host_Template' and advansys_setup() Functions
--- Loadable Driver Support
--- Miscellaneous Driver Functions
--- Functions Required by the Asc Library
--- Functions Required by the Adv Library
--- Tracing and Debugging Functions
--- Asc Library Functions
--- Adv Library Functions
3. The string 'XXX' is used to flag code that needs to be re-written
or that contains a problem that needs to be addressed.
4. I have stripped comments from and reformatted the source for the
Asc Library and Adv Library to reduce the size of this file. This
source can be found under the following headings. The Asc Library
is used to support Narrow Boards. The Adv Library is used to
support Wide Boards.
--- Asc Library Constants and Macros
--- Adv Library Constants and Macros
--- Asc Library Functions
--- Adv Library Functions
E. Driver Compile Time Options and Debugging
In this source file the following constants can be defined. They are
defined in the source below. Both of these options are enabled by
default.
1. ADVANSYS_ASSERT - Enable driver assertions (Def: Enabled)
Enabling this option adds assertion logic statements to the
driver. If an assertion fails a message will be displayed to
the console, but the system will continue to operate. Any
assertions encountered should be reported to the person
responsible for the driver. Assertion statements may proactively
detect problems with the driver and facilitate fixing these
problems. Enabling assertions will add a small overhead to the
execution of the driver.
2. ADVANSYS_DEBUG - Enable driver debugging (Def: Disabled)
Enabling this option adds tracing functions to the driver and
the ability to set a driver tracing level at boot time. This
option will also export symbols not required outside the driver to
the kernel name space. This option is very useful for debugging
the driver, but it will add to the size of the driver execution
image and add overhead to the execution of the driver.
The amount of debugging output can be controlled with the global
variable 'asc_dbglvl'. The higher the number the more output. By
default the debug level is 0.
If the driver is loaded at boot time and the LILO Driver Option
is included in the system, the debug level can be changed by
specifying a 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port. The
first three hex digits of the pseudo I/O Port must be set to
'deb' and the fourth hex digit specifies the debug level: 0 - F.
The following command line will look for an adapter at 0x330
and set the debug level to 2.
linux advansys=0x330,0,0,0,0xdeb2
If the driver is built as a loadable module this variable can be
defined when the driver is loaded. The following insmod command
will set the debug level to one.
insmod advansys.o asc_dbglvl=1
Debugging Message Levels:
0: Errors Only
1: High-Level Tracing
2-N: Verbose Tracing
To enable debug output to console, please make sure that:
a. System and kernel logging is enabled (syslogd, klogd running).
b. Kernel messages are routed to console output. Check
/etc/syslog.conf for an entry similar to this:
kern.* /dev/console
c. klogd is started with the appropriate -c parameter
(e.g. klogd -c 8)
This will cause printk() messages to be be displayed on the
current console. Refer to the klogd(8) and syslogd(8) man pages
for details.
Alternatively you can enable printk() to console with this
program. However, this is not the 'official' way to do this.
Debug output is logged in /var/log/messages.
main()
{
syscall(103, 7, 0, 0);
}
Increasing LOG_BUF_LEN in kernel/printk.c to something like
40960 allows more debug messages to be buffered in the kernel
and written to the console or log file.
3. ADVANSYS_STATS - Enable statistics (Def: Enabled >= v1.3.0)
Enabling this option adds statistics collection and display
through /proc to the driver. The information is useful for
monitoring driver and device performance. It will add to the
size of the driver execution image and add minor overhead to
the execution of the driver.
Statistics are maintained on a per adapter basis. Driver entry
point call counts and transfer size counts are maintained.
Statistics are only available for kernels greater than or equal
to v1.3.0 with the CONFIG_PROC_FS (/proc) file system configured.
AdvanSys SCSI adapter files have the following path name format:
/proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
This information can be displayed with cat. For example:
cat /proc/scsi/advansys/0
When ADVANSYS_STATS is not defined the AdvanSys /proc files only
contain adapter and device configuration information.
F. Driver LILO Option
If init/main.c is modified as described in the 'Directions for Adding
the AdvanSys Driver to Linux' section (B.4.) above, the driver will
recognize the 'advansys' LILO command line and /etc/lilo.conf option.
This option can be used to either disable I/O port scanning or to limit
scanning to 1 - 4 I/O ports. Regardless of the option setting EISA and
PCI boards will still be searched for and detected. This option only
affects searching for ISA and VL boards.
Examples:
1. Eliminate I/O port scanning:
boot: linux advansys=
or
boot: linux advansys=0x0
2. Limit I/O port scanning to one I/O port:
boot: linux advansys=0x110
3. Limit I/O port scanning to four I/O ports:
boot: linux advansys=0x110,0x210,0x230,0x330
For a loadable module the same effect can be achieved by setting
the 'asc_iopflag' variable and 'asc_ioport' array when loading
the driver, e.g.
insmod advansys.o asc_iopflag=1 asc_ioport=0x110,0x330
If ADVANSYS_DEBUG is defined a 5th (ASC_NUM_IOPORT_PROBE + 1)
I/O Port may be added to specify the driver debug level. Refer to
the 'Driver Compile Time Options and Debugging' section above for
more information.
G. Tests to run before releasing new driver
1. In the supported kernels verify there are no warning or compile
errors when the kernel is built as both a driver and as a module
and with the following options:
ADVANSYS_DEBUG - enabled and disabled
CONFIG_SMP - enabled and disabled
CONFIG_PROC_FS - enabled and disabled
2. Run tests on an x86, alpha, and PowerPC with at least one narrow
card and one wide card attached to a hard disk and CD-ROM drive:
fdisk, mkfs, fsck, bonnie, copy/compare test from the
CD-ROM to the hard drive.
H. Release History
BETA-1.0 (12/23/95):
First Release
BETA-1.1 (12/28/95):
1. Prevent advansys_detect() from being called twice.
2. Add LILO 0xdeb[0-f] option to set 'asc_dbglvl'.
1.2 (1/12/96):
1. Prevent re-entrancy in the interrupt handler which
resulted in the driver hanging Linux.
2. Fix problem that prevented ABP-940 cards from being
recognized on some PCI motherboards.
3. Add support for the ABP-5140 PnP ISA card.
4. Fix check condition return status.
5. Add conditionally compiled code for Linux v1.3.X.
1.3 (2/23/96):
1. Fix problem in advansys_biosparam() that resulted in the
wrong drive geometry being returned for drives > 1GB with
extended translation enabled.
2. Add additional tracing during device initialization.
3. Change code that only applies to ISA PnP adapter.
4. Eliminate 'make dep' warning.
5. Try to fix problem with handling resets by increasing their
timeout value.
1.4 (5/8/96):
1. Change definitions to eliminate conflicts with other subsystems.
2. Add versioning code for the shared interrupt changes.
3. Eliminate problem in asc_rmqueue() with iterating after removing
a request.
4. Remove reset request loop problem from the "Known Problems or
Issues" section. This problem was isolated and fixed in the
mid-level SCSI driver.
1.5 (8/8/96):
1. Add support for ABP-940U (PCI Ultra) adapter.
2. Add support for IRQ sharing by setting the SA_SHIRQ flag for
request_irq and supplying a dev_id pointer to both request_irq()
and free_irq().
3. In AscSearchIOPortAddr11() restore a call to check_region() which
should be used before I/O port probing.
4. Fix bug in asc_prt_hex() which resulted in the displaying
the wrong data.
5. Incorporate miscellaneous Asc Library bug fixes and new microcode.
6. Change driver versioning to be specific to each Linux sub-level.
7. Change statistics gathering to be per adapter instead of global
to the driver.
8. Add more information and statistics to the adapter /proc file:
/proc/scsi/advansys[0...].
9. Remove 'cmd_per_lun' from the "Known Problems or Issues" list.
This problem has been addressed with the SCSI mid-level changes
made in v1.3.89. The advansys_select_queue_depths() function
was added for the v1.3.89 changes.
1.6 (9/10/96):
1. Incorporate miscellaneous Asc Library bug fixes and new microcode.
1.7 (9/25/96):
1. Enable clustering and optimize the setting of the maximum number
of scatter gather elements for any particular board. Clustering
increases CPU utilization, but results in a relatively larger
increase in I/O throughput.
2. Improve the performance of the request queuing functions by
adding a last pointer to the queue structure.
3. Correct problems with reset and abort request handling that
could have hung or crashed Linux.
4. Add more information to the adapter /proc file:
/proc/scsi/advansys[0...].
5. Remove the request timeout issue form the driver issues list.
6. Miscellaneous documentation additions and changes.
1.8 (10/4/96):
1. Make changes to handle the new v2.1.0 kernel memory mapping
in which a kernel virtual address may not be equivalent to its
bus or DMA memory address.
2. Change abort and reset request handling to make it yet even
more robust.
3. Try to mitigate request starvation by sending ordered requests
to heavily loaded, tag queuing enabled devices.
4. Maintain statistics on request response time.
5. Add request response time statistics and other information to
the adapter /proc file: /proc/scsi/advansys[0...].
1.9 (10/21/96):
1. Add conditionally compiled code (ASC_QUEUE_FLOW_CONTROL) to
make use of mid-level SCSI driver device queue depth flow
control mechanism. This will eliminate aborts caused by a
device being unable to keep up with requests and eliminate
repeat busy or QUEUE FULL status returned by a device.
2. Incorporate miscellaneous Asc Library bug fixes.
3. To allow the driver to work in kernels with broken module
support set 'cmd_per_lun' if the driver is compiled as a
module. This change affects kernels v1.3.89 to present.
4. Remove PCI BIOS address from the driver banner. The PCI BIOS
is relocated by the motherboard BIOS and its new address can
not be determined by the driver.
5. Add mid-level SCSI queue depth information to the adapter
/proc file: /proc/scsi/advansys[0...].
2.0 (11/14/96):
1. Change allocation of global structures used for device
initialization to guarantee they are in DMA-able memory.
Previously when the driver was loaded as a module these
structures might not have been in DMA-able memory, causing
device initialization to fail.
2.1 (12/30/96):
1. In advansys_reset(), if the request is a synchronous reset
request, even if the request serial number has changed, then
complete the request.
2. Add Asc Library bug fixes including new microcode.
3. Clear inquiry buffer before using it.
4. Correct ifdef typo.
2.2 (1/15/97):
1. Add Asc Library bug fixes including new microcode.
2. Add synchronous data transfer rate information to the
adapter /proc file: /proc/scsi/advansys[0...].
3. Change ADVANSYS_DEBUG to be disabled by default. This
will reduce the size of the driver image, eliminate execution
overhead, and remove unneeded symbols from the kernel symbol
space that were previously added by the driver.
4. Add new compile-time option ADVANSYS_ASSERT for assertion
code that used to be defined within ADVANSYS_DEBUG. This
option is enabled by default.
2.8 (5/26/97):
1. Change version number to 2.8 to synchronize the Linux driver
version numbering with other AdvanSys drivers.
2. Reformat source files without tabs to present the same view
of the file to everyone regardless of the editor tab setting
being used.
3. Add Asc Library bug fixes.
3.1A (1/8/98):
1. Change version number to 3.1 to indicate that support for
Ultra-Wide adapters (ABP-940UW) is included in this release.
2. Add Asc Library (Narrow Board) bug fixes.
3. Report an underrun condition with the host status byte set
to DID_UNDERRUN. Currently DID_UNDERRUN is defined to 0 which
causes the underrun condition to be ignored. When Linux defines
its own DID_UNDERRUN the constant defined in this file can be
removed.
4. Add patch to AscWaitTixISRDone().
5. Add support for up to 16 different AdvanSys host adapter SCSI
channels in one system. This allows four cards with four channels
to be used in one system.
3.1B (1/9/98):
1. Handle that PCI register base addresses are not always page
aligned even though ioremap() requires that the address argument
be page aligned.
3.1C (1/10/98):
1. Update latest BIOS version checked for from the /proc file.
2. Don't set microcode SDTR variable at initialization. Instead
wait until device capabilities have been detected from an Inquiry
command.
3.1D (1/21/98):
1. Improve performance when the driver is compiled as module by
allowing up to 64 scatter-gather elements instead of 8.
3.1E (5/1/98):
1. Set time delay in AscWaitTixISRDone() to 1000 ms.
2. Include SMP locking changes.
3. For v2.1.93 and newer kernels use CONFIG_PCI and new PCI BIOS
access functions.
4. Update board serial number printing.
5. Try allocating an IRQ both with and without the SA_INTERRUPT
flag set to allow IRQ sharing with drivers that do not set
the SA_INTERRUPT flag. Also display a more descriptive error
message if request_irq() fails.
6. Update to latest Asc and Adv Libraries.
3.2A (7/22/99):
1. Update Adv Library to 4.16 which includes support for
the ASC38C0800 (Ultra2/LVD) IC.
3.2B (8/23/99):
1. Correct PCI compile time option for v2.1.93 and greater
kernels, advansys_info() string, and debug compile time
option.
2. Correct DvcSleepMilliSecond() for v2.1.0 and greater
kernels. This caused an LVD detection/BIST problem problem
among other things.
3. Sort PCI cards by PCI Bus, Slot, Function ascending order
to be consistent with the BIOS.
4. Update to Asc Library S121 and Adv Library 5.2.
3.2C (8/24/99):
1. Correct PCI card detection bug introduced in 3.2B that
prevented PCI cards from being detected in kernels older
than v2.1.93.
3.2D (8/26/99):
1. Correct /proc device synchronous speed information display.
Also when re-negotiation is pending for a target device
note this condition with an * and footnote.
2. Correct initialization problem with Ultra-Wide cards that
have a pre-3.2 BIOS. A microcode variable changed locations
in 3.2 and greater BIOSes which caused WDTR to be attempted
erroneously with drives that don't support WDTR.
3.2E (8/30/99):
1. Fix compile error caused by v2.3.13 PCI structure change.
2. Remove field from ASCEEP_CONFIG that resulted in an EEPROM
checksum error for ISA cards.
3. Remove ASC_QUEUE_FLOW_CONTROL conditional code. The mid-level
SCSI changes that it depended on were never included in Linux.
3.2F (9/3/99):
1. Handle new initial function code added in v2.3.16 for all
driver versions.
3.2G (9/8/99):
1. Fix PCI board detection in v2.3.13 and greater kernels.
2. Fix comiple errors in v2.3.X with debugging enabled.
3.2H (9/13/99):
1. Add 64-bit address, long support for Alpha and UltraSPARC.
The driver has been verified to work on an Alpha system.
2. Add partial byte order handling support for Power PC and
other big-endian platforms. This support has not yet been
completed or verified.
3. For wide boards replace block zeroing of request and
scatter-gather structures with individual field initialization
to improve performance.
4. Correct and clarify ROM BIOS version detection.
3.2I (10/8/99):
1. Update to Adv Library 5.4.
2. Add v2.3.19 underrun reporting to asc_isr_callback() and
adv_isr_callback(). Remove DID_UNDERRUN constant and other
no longer needed code that previously documented the lack
of underrun handling.
3.2J (10/14/99):
1. Eliminate compile errors for v2.0 and earlier kernels.
3.2K (11/15/99):
1. Correct debug compile error in asc_prt_adv_scsi_req_q().
2. Update Adv Library to 5.5.
3. Add ifdef handling for /proc changes added in v2.3.28.
4. Increase Wide board scatter-gather list maximum length to
255 when the driver is compiled into the kernel.
3.2L (11/18/99):
1. Fix bug in adv_get_sglist() that caused an assertion failure
at line 7475. The reqp->sgblkp pointer must be initialized
to NULL in adv_get_sglist().
3.2M (11/29/99):
1. Really fix bug in adv_get_sglist().
2. Incorporate v2.3.29 changes into driver.
3.2N (4/1/00):
1. Add CONFIG_ISA ifdef code.
2. Include advansys_interrupts_enabled name change patch.
3. For >= v2.3.28 use new SCSI error handling with new function
advansys_eh_bus_reset(). Don't include an abort function
because of base library limitations.
4. For >= v2.3.28 use per board lock instead of io_request_lock.
5. For >= v2.3.28 eliminate advansys_command() and
advansys_command_done().
6. Add some changes for PowerPC (Big Endian) support, but it isn't
working yet.
7. Fix "nonexistent resource free" problem that occurred on a module
unload for boards with an I/O space >= 255. The 'n_io_port' field
is only one byte and can not be used to hold an ioport length more
than 255.
3.3A (4/4/00):
1. Update to Adv Library 5.8.
2. For wide cards add support for CDBs up to 16 bytes.
3. Eliminate warnings when CONFIG_PROC_FS is not defined.
3.3B (5/1/00):
1. Support for PowerPC (Big Endian) wide cards. Narrow cards
still need work.
2. Change bitfields to shift and mask access for endian
portability.
3.3C (10/13/00):
1. Update for latest 2.4 kernel.
2. Test ABP-480 CardBus support in 2.4 kernel - works!
3. Update to Asc Library S123.
4. Update to Adv Library 5.12.
3.3D (11/22/00):
1. Update for latest 2.4 kernel.
2. Create patches for 2.2 and 2.4 kernels.
3.3E (1/9/01):
1. Now that 2.4 is released remove ifdef code for kernel versions
less than 2.2. The driver is now only supported in kernels 2.2,
2.4, and greater.
2. Add code to release and acquire the io_request_lock in
the driver entrypoint functions: advansys_detect and
advansys_queuecommand. In kernel 2.4 the SCSI mid-level driver
still holds the io_request_lock on entry to SCSI low-level drivers.
This was supposed to be removed before 2.4 was released but never
happened. When the mid-level SCSI driver is changed all references
to the io_request_lock should be removed from the driver.
3. Simplify error handling by removing advansys_abort(),
AscAbortSRB(), AscResetDevice(). SCSI bus reset requests are
now handled by resetting the SCSI bus and fully re-initializing
the chip. This simple method of error recovery has proven to work
most reliably after attempts at different methods. Also now only
support the "new" error handling method and remove the obsolete
error handling interface.
4. Fix debug build errors.
3.3F (1/24/01):
1. Merge with ConnectCom version from Andy Kellner which
updates Adv Library to 5.14.
2. Make PowerPC (Big Endian) work for narrow cards and
fix problems writing EEPROM for wide cards.
3. Remove interrupts_enabled assertion function.
3.3G (2/16/01):
1. Return an error from narrow boards if passed a 16 byte
CDB. The wide board can already handle 16 byte CDBs.
3.3GJ (4/15/02):
1. hacks for lk 2.5 series (D. Gilbert)
3.3GJD (10/14/02):
1. change select_queue_depths to slave_configure
2. make cmd_per_lun be sane again
3.3K [2004/06/24]:
1. continuing cleanup for lk 2.6 series
2. Fix problem in lk 2.6.7-bk2 that broke PCI wide cards
3. Fix problem that oopsed ISA cards
I. Known Problems/Fix List (XXX)
1. Need to add memory mapping workaround. Test the memory mapping.
If it doesn't work revert to I/O port access. Can a test be done
safely?
2. Handle an interrupt not working. Keep an interrupt counter in
the interrupt handler. In the timeout function if the interrupt
has not occurred then print a message and run in polled mode.
3. Allow bus type scanning order to be changed.
4. Need to add support for target mode commands, cf. CAM XPT.
J. Credits (Chronological Order)
Bob Frey <bfrey@turbolinux.com.cn> wrote the AdvanSys SCSI driver
and maintained it up to 3.3F. He continues to answer questions
and help maintain the driver.
Nathan Hartwell <mage@cdc3.cdc.net> provided the directions and
basis for the Linux v1.3.X changes which were included in the
1.2 release.
Thomas E Zerucha <zerucha@shell.portal.com> pointed out a bug
in advansys_biosparam() which was fixed in the 1.3 release.
Erik Ratcliffe <erik@caldera.com> has done testing of the
AdvanSys driver in the Caldera releases.
Rik van Riel <H.H.vanRiel@fys.ruu.nl> provided a patch to
AscWaitTixISRDone() which he found necessary to make the
driver work with a SCSI-1 disk.
Mark Moran <mmoran@mmoran.com> has helped test Ultra-Wide
support in the 3.1A driver.
Doug Gilbert <dgilbert@interlog.com> has made changes and
suggestions to improve the driver and done a lot of testing.
Ken Mort <ken@mort.net> reported a DEBUG compile bug fixed
in 3.2K.
Tom Rini <trini@kernel.crashing.org> provided the CONFIG_ISA
patch and helped with PowerPC wide and narrow board support.
Philip Blundell <philb@gnu.org> provided an
advansys_interrupts_enabled patch.
Dave Jones <dave@denial.force9.co.uk> reported the compiler
warnings generated when CONFIG_PROC_FS was not defined in
the 3.2M driver.
Jerry Quinn <jlquinn@us.ibm.com> fixed PowerPC support (endian
problems) for wide cards.
Bryan Henderson <bryanh@giraffe-data.com> helped debug narrow
card error handling.
Manuel Veloso <veloso@pobox.com> worked hard on PowerPC narrow
board support and fixed a bug in AscGetEEPConfig().
Arnaldo Carvalho de Melo <acme@conectiva.com.br> made
save_flags/restore_flags changes.
Andy Kellner <AKellner@connectcom.net> continues the Advansys SCSI
driver development for ConnectCom (Version > 3.3F).
K. ConnectCom (AdvanSys) Contact Information
Mail: ConnectCom Solutions, Inc.
1150 Ringwood Court
San Jose, CA 95131
Operator/Sales: 1-408-383-9400
FAX: 1-408-383-9612
Tech Support: 1-408-467-2930
Tech Support E-Mail: linux@connectcom.net
FTP Site: ftp.connectcom.net (login: anonymous)
Web Site: http://www.connectcom.net
*/
/*
* --- Linux Include Files
*/
#include <linux/config.h>
#include <linux/module.h>
#if defined(CONFIG_X86) && !defined(CONFIG_ISA)
#define CONFIG_ISA
#endif /* CONFIG_X86 && !CONFIG_ISA */
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/proc_fs.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/stat.h>
#include <linux/spinlock.h>
#include <linux/dma-mapping.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/dma.h>
/* FIXME: (by jejb@steeleye.com) This warning is present for two
* reasons:
*
* 1) This driver badly needs converting to the correct driver model
* probing API
*
* 2) Although all of the necessary command mapping places have the
* appropriate dma_map.. APIs, the driver still processes its internal
* queue using bus_to_virt() and virt_to_bus() which are illegal under
* the API. The entire queue processing structure will need to be
* altered to fix this.
*/
#warning this driver is still not properly converted to the DMA API
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_tcq.h>
#include <scsi/scsi.h>
#include <scsi/scsi_host.h>
#include "advansys.h"
#ifdef CONFIG_PCI
#include <linux/pci.h>
#endif /* CONFIG_PCI */
/*
* --- Driver Options
*/
/* Enable driver assertions. */
#define ADVANSYS_ASSERT
/* Enable driver /proc statistics. */
#define ADVANSYS_STATS
/* Enable driver tracing. */
/* #define ADVANSYS_DEBUG */
/*
* --- Debugging Header
*/
#ifdef ADVANSYS_DEBUG
#define STATIC
#else /* ADVANSYS_DEBUG */
#define STATIC static
#endif /* ADVANSYS_DEBUG */
/*
* --- Asc Library Constants and Macros
*/
#define ASC_LIB_VERSION_MAJOR 1
#define ASC_LIB_VERSION_MINOR 24
#define ASC_LIB_SERIAL_NUMBER 123
/*
* Portable Data Types
*
* Any instance where a 32-bit long or pointer type is assumed
* for precision or HW defined structures, the following define
* types must be used. In Linux the char, short, and int types
* are all consistent at 8, 16, and 32 bits respectively. Pointers
* and long types are 64 bits on Alpha and UltraSPARC.
*/
#define ASC_PADDR __u32 /* Physical/Bus address data type. */
#define ASC_VADDR __u32 /* Virtual address data type. */
#define ASC_DCNT __u32 /* Unsigned Data count type. */
#define ASC_SDCNT __s32 /* Signed Data count type. */
/*
* These macros are used to convert a virtual address to a
* 32-bit value. This currently can be used on Linux Alpha
* which uses 64-bit virtual address but a 32-bit bus address.
* This is likely to break in the future, but doing this now
* will give us time to change the HW and FW to handle 64-bit
* addresses.
*/
#define ASC_VADDR_TO_U32 virt_to_bus
#define ASC_U32_TO_VADDR bus_to_virt
typedef unsigned char uchar;
#ifndef TRUE
#define TRUE (1)
#endif
#ifndef FALSE
#define FALSE (0)
#endif
#define EOF (-1)
#define ERR (-1)
#define UW_ERR (uint)(0xFFFF)
#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
#define AscPCIConfigVendorIDRegister 0x0000
#define AscPCIConfigDeviceIDRegister 0x0002
#define AscPCIConfigCommandRegister 0x0004
#define AscPCIConfigStatusRegister 0x0006
#define AscPCIConfigRevisionIDRegister 0x0008
#define AscPCIConfigCacheSize 0x000C
#define AscPCIConfigLatencyTimer 0x000D
#define AscPCIIOBaseRegister 0x0010
#define AscPCICmdRegBits_IOMemBusMaster 0x0007
#define ASC_PCI_ID2BUS(id) ((id) & 0xFF)
#define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F)
#define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7)
#define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF))
#define ASC_PCI_VENDORID 0x10CD
#define ASC_PCI_DEVICEID_1200A 0x1100
#define ASC_PCI_DEVICEID_1200B 0x1200
#define ASC_PCI_DEVICEID_ULTRA 0x1300
#define ASC_PCI_REVISION_3150 0x02
#define ASC_PCI_REVISION_3050 0x03
#define ASC_DVCLIB_CALL_DONE (1)
#define ASC_DVCLIB_CALL_FAILED (0)
#define ASC_DVCLIB_CALL_ERROR (-1)
/*
* Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
* The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
* macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
* SRB structure.
*/
#define CC_VERY_LONG_SG_LIST 0
#define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
#define PortAddr unsigned short /* port address size */
#define inp(port) inb(port)
#define outp(port, byte) outb((byte), (port))
#define inpw(port) inw(port)
#define outpw(port, word) outw((word), (port))
#define ASC_MAX_SG_QUEUE 7
#define ASC_MAX_SG_LIST 255
#define ASC_CS_TYPE unsigned short
#define ASC_IS_ISA (0x0001)
#define ASC_IS_ISAPNP (0x0081)
#define ASC_IS_EISA (0x0002)
#define ASC_IS_PCI (0x0004)
#define ASC_IS_PCI_ULTRA (0x0104)
#define ASC_IS_PCMCIA (0x0008)
#define ASC_IS_MCA (0x0020)
#define ASC_IS_VL (0x0040)
#define ASC_ISA_PNP_PORT_ADDR (0x279)
#define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800)
#define ASC_IS_WIDESCSI_16 (0x0100)
#define ASC_IS_WIDESCSI_32 (0x0200)
#define ASC_IS_BIG_ENDIAN (0x8000)
#define ASC_CHIP_MIN_VER_VL (0x01)
#define ASC_CHIP_MAX_VER_VL (0x07)
#define ASC_CHIP_MIN_VER_PCI (0x09)
#define ASC_CHIP_MAX_VER_PCI (0x0F)
#define ASC_CHIP_VER_PCI_BIT (0x08)
#define ASC_CHIP_MIN_VER_ISA (0x11)
#define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
#define ASC_CHIP_MAX_VER_ISA (0x27)
#define ASC_CHIP_VER_ISA_BIT (0x30)
#define ASC_CHIP_VER_ISAPNP_BIT (0x20)
#define ASC_CHIP_VER_ASYN_BUG (0x21)
#define ASC_CHIP_VER_PCI 0x08
#define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
#define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
#define ASC_CHIP_MIN_VER_EISA (0x41)
#define ASC_CHIP_MAX_VER_EISA (0x47)
#define ASC_CHIP_VER_EISA_BIT (0x40)
#define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
#define ASC_MAX_LIB_SUPPORTED_ISA_CHIP_VER 0x21
#define ASC_MAX_LIB_SUPPORTED_PCI_CHIP_VER 0x0A
#define ASC_MAX_VL_DMA_ADDR (0x07FFFFFFL)
#define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
#define ASC_MAX_PCI_DMA_ADDR (0xFFFFFFFFL)
#define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
#define ASC_MAX_ISA_DMA_ADDR (0x00FFFFFFL)
#define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
#define ASC_MAX_EISA_DMA_ADDR (0x07FFFFFFL)
#define ASC_MAX_EISA_DMA_COUNT (0x07FFFFFFL)
#define ASC_SCSI_ID_BITS 3
#define ASC_SCSI_TIX_TYPE uchar
#define ASC_ALL_DEVICE_BIT_SET 0xFF
#define ASC_SCSI_BIT_ID_TYPE uchar
#define ASC_MAX_TID 7
#define ASC_MAX_LUN 7
#define ASC_SCSI_WIDTH_BIT_SET 0xFF
#define ASC_MAX_SENSE_LEN 32
#define ASC_MIN_SENSE_LEN 14
#define ASC_MAX_CDB_LEN 12
#define ASC_SCSI_RESET_HOLD_TIME_US 60
#define ADV_INQ_CLOCKING_ST_ONLY 0x0
#define ADV_INQ_CLOCKING_DT_ONLY 0x1
#define ADV_INQ_CLOCKING_ST_AND_DT 0x3
/*
* Inquiry SPC-2 SPI Byte 1 EVPD (Enable Vital Product Data)
* and CmdDt (Command Support Data) field bit definitions.
*/
#define ADV_INQ_RTN_VPD_AND_CMDDT 0x3
#define ADV_INQ_RTN_CMDDT_FOR_OP_CODE 0x2
#define ADV_INQ_RTN_VPD_FOR_PG_CODE 0x1
#define ADV_INQ_RTN_STD_INQUIRY_DATA 0x0
#define ASC_SCSIDIR_NOCHK 0x00
#define ASC_SCSIDIR_T2H 0x08
#define ASC_SCSIDIR_H2T 0x10
#define ASC_SCSIDIR_NODATA 0x18
#define SCSI_ASC_NOMEDIA 0x3A
#define ASC_SRB_HOST(x) ((uchar)((uchar)(x) >> 4))
#define ASC_SRB_TID(x) ((uchar)((uchar)(x) & (uchar)0x0F))
#define ASC_SRB_LUN(x) ((uchar)((uint)(x) >> 13))
#define PUT_CDB1(x) ((uchar)((uint)(x) >> 8))
#define MS_CMD_DONE 0x00
#define MS_EXTEND 0x01
#define MS_SDTR_LEN 0x03
#define MS_SDTR_CODE 0x01
#define MS_WDTR_LEN 0x02
#define MS_WDTR_CODE 0x03
#define MS_MDP_LEN 0x05
#define MS_MDP_CODE 0x00
/*
* Inquiry data structure and bitfield macros
*
* Only quantities of more than 1 bit are shifted, since the others are
* just tested for true or false. C bitfields aren't portable between big
* and little-endian platforms so they are not used.
*/
#define ASC_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
#define ASC_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
#define ASC_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
#define ASC_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
#define ASC_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
#define ASC_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
#define ASC_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
#define ASC_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
#define ASC_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
#define ASC_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
#define ASC_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
#define ASC_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
#define ASC_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
#define ASC_INQ_SYNC(inq) ((inq)->flags & 0x10)
#define ASC_INQ_WIDE16(inq) ((inq)->flags & 0x20)
#define ASC_INQ_WIDE32(inq) ((inq)->flags & 0x40)
#define ASC_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
#define ASC_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
#define ASC_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
#define ASC_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
typedef struct {
uchar periph;
uchar devtype;
uchar ver;
uchar byte3;
uchar add_len;
uchar res1;
uchar res2;
uchar flags;
uchar vendor_id[8];
uchar product_id[16];
uchar product_rev_level[4];
} ASC_SCSI_INQUIRY;
#define ASC_SG_LIST_PER_Q 7
#define QS_FREE 0x00
#define QS_READY 0x01
#define QS_DISC1 0x02
#define QS_DISC2 0x04
#define QS_BUSY 0x08
#define QS_ABORTED 0x40
#define QS_DONE 0x80
#define QC_NO_CALLBACK 0x01
#define QC_SG_SWAP_QUEUE 0x02
#define QC_SG_HEAD 0x04
#define QC_DATA_IN 0x08
#define QC_DATA_OUT 0x10
#define QC_URGENT 0x20
#define QC_MSG_OUT 0x40
#define QC_REQ_SENSE 0x80
#define QCSG_SG_XFER_LIST 0x02
#define QCSG_SG_XFER_MORE 0x04
#define QCSG_SG_XFER_END 0x08
#define QD_IN_PROGRESS 0x00
#define QD_NO_ERROR 0x01
#define QD_ABORTED_BY_HOST 0x02
#define QD_WITH_ERROR 0x04
#define QD_INVALID_REQUEST 0x80
#define QD_INVALID_HOST_NUM 0x81
#define QD_INVALID_DEVICE 0x82
#define QD_ERR_INTERNAL 0xFF
#define QHSTA_NO_ERROR 0x00
#define QHSTA_M_SEL_TIMEOUT 0x11
#define QHSTA_M_DATA_OVER_RUN 0x12
#define QHSTA_M_DATA_UNDER_RUN 0x12
#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
#define QHSTA_D_HOST_ABORT_FAILED 0x23
#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
#define QHSTA_D_ASPI_NO_BUF_POOL 0x26
#define QHSTA_M_WTM_TIMEOUT 0x41
#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
#define QHSTA_M_TARGET_STATUS_BUSY 0x45
#define QHSTA_M_BAD_TAG_CODE 0x46
#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
#define QHSTA_D_LRAM_CMP_ERROR 0x81
#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
#define ASC_FLAG_SCSIQ_REQ 0x01
#define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
#define ASC_FLAG_BIOS_ASYNC_IO 0x04
#define ASC_FLAG_SRB_LINEAR_ADDR 0x08
#define ASC_FLAG_WIN16 0x10
#define ASC_FLAG_WIN32 0x20
#define ASC_FLAG_ISA_OVER_16MB 0x40
#define ASC_FLAG_DOS_VM_CALLBACK 0x80
#define ASC_TAG_FLAG_EXTRA_BYTES 0x10
#define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
#define ASC_SCSIQ_CPY_BEG 4
#define ASC_SCSIQ_SGHD_CPY_BEG 2
#define ASC_SCSIQ_B_FWD 0
#define ASC_SCSIQ_B_BWD 1
#define ASC_SCSIQ_B_STATUS 2
#define ASC_SCSIQ_B_QNO 3
#define ASC_SCSIQ_B_CNTL 4
#define ASC_SCSIQ_B_SG_QUEUE_CNT 5
#define ASC_SCSIQ_D_DATA_ADDR 8
#define ASC_SCSIQ_D_DATA_CNT 12
#define ASC_SCSIQ_B_SENSE_LEN 20
#define ASC_SCSIQ_DONE_INFO_BEG 22
#define ASC_SCSIQ_D_SRBPTR 22
#define ASC_SCSIQ_B_TARGET_IX 26
#define ASC_SCSIQ_B_CDB_LEN 28
#define ASC_SCSIQ_B_TAG_CODE 29
#define ASC_SCSIQ_W_VM_ID 30
#define ASC_SCSIQ_DONE_STATUS 32
#define ASC_SCSIQ_HOST_STATUS 33
#define ASC_SCSIQ_SCSI_STATUS 34
#define ASC_SCSIQ_CDB_BEG 36
#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
#define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
#define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
#define ASC_SCSIQ_B_SG_WK_QP 49
#define ASC_SCSIQ_B_SG_WK_IX 50
#define ASC_SCSIQ_W_ALT_DC1 52
#define ASC_SCSIQ_B_LIST_CNT 6
#define ASC_SCSIQ_B_CUR_LIST_CNT 7
#define ASC_SGQ_B_SG_CNTL 4
#define ASC_SGQ_B_SG_HEAD_QP 5
#define ASC_SGQ_B_SG_LIST_CNT 6
#define ASC_SGQ_B_SG_CUR_LIST_CNT 7
#define ASC_SGQ_LIST_BEG 8
#define ASC_DEF_SCSI1_QNG 4
#define ASC_MAX_SCSI1_QNG 4
#define ASC_DEF_SCSI2_QNG 16
#define ASC_MAX_SCSI2_QNG 32
#define ASC_TAG_CODE_MASK 0x23
#define ASC_STOP_REQ_RISC_STOP 0x01
#define ASC_STOP_ACK_RISC_STOP 0x03
#define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
#define ASC_STOP_CLEAN_UP_DISC_Q 0x20
#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
#define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
#define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
#define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
#define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
#define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
#define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
#define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
typedef struct asc_scsiq_1 {
uchar status;
uchar q_no;
uchar cntl;
uchar sg_queue_cnt;
uchar target_id;
uchar target_lun;
ASC_PADDR data_addr;
ASC_DCNT data_cnt;
ASC_PADDR sense_addr;
uchar sense_len;
uchar extra_bytes;
} ASC_SCSIQ_1;
typedef struct asc_scsiq_2 {
ASC_VADDR srb_ptr;
uchar target_ix;
uchar flag;
uchar cdb_len;
uchar tag_code;
ushort vm_id;
} ASC_SCSIQ_2;
typedef struct asc_scsiq_3 {
uchar done_stat;
uchar host_stat;
uchar scsi_stat;
uchar scsi_msg;
} ASC_SCSIQ_3;
typedef struct asc_scsiq_4 {
uchar cdb[ASC_MAX_CDB_LEN];
uchar y_first_sg_list_qp;
uchar y_working_sg_qp;
uchar y_working_sg_ix;
uchar y_res;
ushort x_req_count;
ushort x_reconnect_rtn;
ASC_PADDR x_saved_data_addr;
ASC_DCNT x_saved_data_cnt;
} ASC_SCSIQ_4;
typedef struct asc_q_done_info {
ASC_SCSIQ_2 d2;
ASC_SCSIQ_3 d3;
uchar q_status;
uchar q_no;
uchar cntl;
uchar sense_len;
uchar extra_bytes;
uchar res;
ASC_DCNT remain_bytes;
} ASC_QDONE_INFO;
typedef struct asc_sg_list {
ASC_PADDR addr;
ASC_DCNT bytes;
} ASC_SG_LIST;
typedef struct asc_sg_head {
ushort entry_cnt;
ushort queue_cnt;
ushort entry_to_copy;
ushort res;
ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
} ASC_SG_HEAD;
#define ASC_MIN_SG_LIST 2
typedef struct asc_min_sg_head {
ushort entry_cnt;
ushort queue_cnt;
ushort entry_to_copy;
ushort res;
ASC_SG_LIST sg_list[ASC_MIN_SG_LIST];
} ASC_MIN_SG_HEAD;
#define QCX_SORT (0x0001)
#define QCX_COALEASE (0x0002)
typedef struct asc_scsi_q {
ASC_SCSIQ_1 q1;
ASC_SCSIQ_2 q2;
uchar *cdbptr;
ASC_SG_HEAD *sg_head;
ushort remain_sg_entry_cnt;
ushort next_sg_index;
} ASC_SCSI_Q;
typedef struct asc_scsi_req_q {
ASC_SCSIQ_1 r1;
ASC_SCSIQ_2 r2;
uchar *cdbptr;
ASC_SG_HEAD *sg_head;
uchar *sense_ptr;
ASC_SCSIQ_3 r3;
uchar cdb[ASC_MAX_CDB_LEN];
uchar sense[ASC_MIN_SENSE_LEN];
} ASC_SCSI_REQ_Q;
typedef struct asc_scsi_bios_req_q {
ASC_SCSIQ_1 r1;
ASC_SCSIQ_2 r2;
uchar *cdbptr;
ASC_SG_HEAD *sg_head;
uchar *sense_ptr;
ASC_SCSIQ_3 r3;
uchar cdb[ASC_MAX_CDB_LEN];
uchar sense[ASC_MIN_SENSE_LEN];
} ASC_SCSI_BIOS_REQ_Q;
typedef struct asc_risc_q {
uchar fwd;
uchar bwd;
ASC_SCSIQ_1 i1;
ASC_SCSIQ_2 i2;
ASC_SCSIQ_3 i3;
ASC_SCSIQ_4 i4;
} ASC_RISC_Q;
typedef struct asc_sg_list_q {
uchar seq_no;
uchar q_no;
uchar cntl;
uchar sg_head_qp;
uchar sg_list_cnt;
uchar sg_cur_list_cnt;
} ASC_SG_LIST_Q;
typedef struct asc_risc_sg_list_q {
uchar fwd;
uchar bwd;
ASC_SG_LIST_Q sg;
ASC_SG_LIST sg_list[7];
} ASC_RISC_SG_LIST_Q;
#define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL
#define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024
#define ASCQ_ERR_NO_ERROR 0
#define ASCQ_ERR_IO_NOT_FOUND 1
#define ASCQ_ERR_LOCAL_MEM 2
#define ASCQ_ERR_CHKSUM 3
#define ASCQ_ERR_START_CHIP 4
#define ASCQ_ERR_INT_TARGET_ID 5
#define ASCQ_ERR_INT_LOCAL_MEM 6
#define ASCQ_ERR_HALT_RISC 7
#define ASCQ_ERR_GET_ASPI_ENTRY 8
#define ASCQ_ERR_CLOSE_ASPI 9
#define ASCQ_ERR_HOST_INQUIRY 0x0A
#define ASCQ_ERR_SAVED_SRB_BAD 0x0B
#define ASCQ_ERR_QCNTL_SG_LIST 0x0C
#define ASCQ_ERR_Q_STATUS 0x0D
#define ASCQ_ERR_WR_SCSIQ 0x0E
#define ASCQ_ERR_PC_ADDR 0x0F
#define ASCQ_ERR_SYN_OFFSET 0x10
#define ASCQ_ERR_SYN_XFER_TIME 0x11
#define ASCQ_ERR_LOCK_DMA 0x12
#define ASCQ_ERR_UNLOCK_DMA 0x13
#define ASCQ_ERR_VDS_CHK_INSTALL 0x14
#define ASCQ_ERR_MICRO_CODE_HALT 0x15
#define ASCQ_ERR_SET_LRAM_ADDR 0x16
#define ASCQ_ERR_CUR_QNG 0x17
#define ASCQ_ERR_SG_Q_LINKS 0x18
#define ASCQ_ERR_SCSIQ_PTR 0x19
#define ASCQ_ERR_ISR_RE_ENTRY 0x1A
#define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
#define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
#define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D
#define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E
#define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F
#define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20
#define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21
#define ASCQ_ERR_SEND_SCSI_Q 0x22
#define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23
#define ASCQ_ERR_RESET_SDTR 0x24
/*
* Warning code values are set in ASC_DVC_VAR 'warn_code'.
*/
#define ASC_WARN_NO_ERROR 0x0000
#define ASC_WARN_IO_PORT_ROTATE 0x0001
#define ASC_WARN_EEPROM_CHKSUM 0x0002
#define ASC_WARN_IRQ_MODIFIED 0x0004
#define ASC_WARN_AUTO_CONFIG 0x0008
#define ASC_WARN_CMD_QNG_CONFLICT 0x0010
#define ASC_WARN_EEPROM_RECOVER 0x0020
#define ASC_WARN_CFG_MSW_RECOVER 0x0040
#define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080
/*
* Error code values are set in ASC_DVC_VAR 'err_code'.
*/
#define ASC_IERR_WRITE_EEPROM 0x0001
#define ASC_IERR_MCODE_CHKSUM 0x0002
#define ASC_IERR_SET_PC_ADDR 0x0004
#define ASC_IERR_START_STOP_CHIP 0x0008
#define ASC_IERR_IRQ_NO 0x0010
#define ASC_IERR_SET_IRQ_NO 0x0020
#define ASC_IERR_CHIP_VERSION 0x0040
#define ASC_IERR_SET_SCSI_ID 0x0080
#define ASC_IERR_GET_PHY_ADDR 0x0100
#define ASC_IERR_BAD_SIGNATURE 0x0200
#define ASC_IERR_NO_BUS_TYPE 0x0400
#define ASC_IERR_SCAM 0x0800
#define ASC_IERR_SET_SDTR 0x1000
#define ASC_IERR_RW_LRAM 0x8000
#define ASC_DEF_IRQ_NO 10
#define ASC_MAX_IRQ_NO 15
#define ASC_MIN_IRQ_NO 10
#define ASC_MIN_REMAIN_Q (0x02)
#define ASC_DEF_MAX_TOTAL_QNG (0xF0)
#define ASC_MIN_TAG_Q_PER_DVC (0x04)
#define ASC_DEF_TAG_Q_PER_DVC (0x04)
#define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q
#define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
#define ASC_MAX_TOTAL_QNG 240
#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
#define ASC_MAX_INRAM_TAG_QNG 16
#define ASC_IOADR_TABLE_MAX_IX 11
#define ASC_IOADR_GAP 0x10
#define ASC_SEARCH_IOP_GAP 0x10
#define ASC_MIN_IOP_ADDR (PortAddr)0x0100
#define ASC_MAX_IOP_ADDR (PortAddr)0x3F0
#define ASC_IOADR_1 (PortAddr)0x0110
#define ASC_IOADR_2 (PortAddr)0x0130
#define ASC_IOADR_3 (PortAddr)0x0150
#define ASC_IOADR_4 (PortAddr)0x0190
#define ASC_IOADR_5 (PortAddr)0x0210
#define ASC_IOADR_6 (PortAddr)0x0230
#define ASC_IOADR_7 (PortAddr)0x0250
#define ASC_IOADR_8 (PortAddr)0x0330
#define ASC_IOADR_DEF ASC_IOADR_8
#define ASC_LIB_SCSIQ_WK_SP 256
#define ASC_MAX_SYN_XFER_NO 16
#define ASC_SYN_MAX_OFFSET 0x0F
#define ASC_DEF_SDTR_OFFSET 0x0F
#define ASC_DEF_SDTR_INDEX 0x00
#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
#define SYN_XFER_NS_0 25
#define SYN_XFER_NS_1 30
#define SYN_XFER_NS_2 35
#define SYN_XFER_NS_3 40
#define SYN_XFER_NS_4 50
#define SYN_XFER_NS_5 60
#define SYN_XFER_NS_6 70
#define SYN_XFER_NS_7 85
#define SYN_ULTRA_XFER_NS_0 12
#define SYN_ULTRA_XFER_NS_1 19
#define SYN_ULTRA_XFER_NS_2 25
#define SYN_ULTRA_XFER_NS_3 32
#define SYN_ULTRA_XFER_NS_4 38
#define SYN_ULTRA_XFER_NS_5 44
#define SYN_ULTRA_XFER_NS_6 50
#define SYN_ULTRA_XFER_NS_7 57
#define SYN_ULTRA_XFER_NS_8 63
#define SYN_ULTRA_XFER_NS_9 69
#define SYN_ULTRA_XFER_NS_10 75
#define SYN_ULTRA_XFER_NS_11 82
#define SYN_ULTRA_XFER_NS_12 88
#define SYN_ULTRA_XFER_NS_13 94
#define SYN_ULTRA_XFER_NS_14 100
#define SYN_ULTRA_XFER_NS_15 107
typedef struct ext_msg {
uchar msg_type;
uchar msg_len;
uchar msg_req;
union {
struct {
uchar sdtr_xfer_period;
uchar sdtr_req_ack_offset;
} sdtr;
struct {
uchar wdtr_width;
} wdtr;
struct {
uchar mdp_b3;
uchar mdp_b2;
uchar mdp_b1;
uchar mdp_b0;
} mdp;
} u_ext_msg;
uchar res;
} EXT_MSG;
#define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
#define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
#define wdtr_width u_ext_msg.wdtr.wdtr_width
#define mdp_b3 u_ext_msg.mdp_b3
#define mdp_b2 u_ext_msg.mdp_b2
#define mdp_b1 u_ext_msg.mdp_b1
#define mdp_b0 u_ext_msg.mdp_b0
typedef struct asc_dvc_cfg {
ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
ASC_SCSI_BIT_ID_TYPE disc_enable;
ASC_SCSI_BIT_ID_TYPE sdtr_enable;
uchar chip_scsi_id;
uchar isa_dma_speed;
uchar isa_dma_channel;
uchar chip_version;
ushort lib_serial_no;
ushort lib_version;
ushort mcode_date;
ushort mcode_version;
uchar max_tag_qng[ASC_MAX_TID + 1];
uchar *overrun_buf;
uchar sdtr_period_offset[ASC_MAX_TID + 1];
ushort pci_slot_info;
uchar adapter_info[6];
struct device *dev;
} ASC_DVC_CFG;
#define ASC_DEF_DVC_CNTL 0xFFFF
#define ASC_DEF_CHIP_SCSI_ID 7
#define ASC_DEF_ISA_DMA_SPEED 4
#define ASC_INIT_STATE_NULL 0x0000
#define ASC_INIT_STATE_BEG_GET_CFG 0x0001
#define ASC_INIT_STATE_END_GET_CFG 0x0002
#define ASC_INIT_STATE_BEG_SET_CFG 0x0004
#define ASC_INIT_STATE_END_SET_CFG 0x0008
#define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
#define ASC_INIT_STATE_END_LOAD_MC 0x0020
#define ASC_INIT_STATE_BEG_INQUIRY 0x0040
#define ASC_INIT_STATE_END_INQUIRY 0x0080
#define ASC_INIT_RESET_SCSI_DONE 0x0100
#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
#define ASC_PCI_DEVICE_ID_REV_A 0x1100
#define ASC_PCI_DEVICE_ID_REV_B 0x1200
#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
#define ASC_MIN_TAGGED_CMD 7
#define ASC_MAX_SCSI_RESET_WAIT 30
struct asc_dvc_var; /* Forward Declaration. */
typedef void (* ASC_ISR_CALLBACK)(struct asc_dvc_var *, ASC_QDONE_INFO *);
typedef int (* ASC_EXE_CALLBACK)(struct asc_dvc_var *, ASC_SCSI_Q *);
typedef struct asc_dvc_var {
PortAddr iop_base;
ushort err_code;
ushort dvc_cntl;
ushort bug_fix_cntl;
ushort bus_type;
ASC_ISR_CALLBACK isr_callback;
ASC_EXE_CALLBACK exe_callback;
ASC_SCSI_BIT_ID_TYPE init_sdtr;
ASC_SCSI_BIT_ID_TYPE sdtr_done;
ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
ASC_SCSI_BIT_ID_TYPE unit_not_ready;
ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
ASC_SCSI_BIT_ID_TYPE start_motor;
uchar scsi_reset_wait;
uchar chip_no;
char is_in_int;
uchar max_total_qng;
uchar cur_total_qng;
uchar in_critical_cnt;
uchar irq_no;
uchar last_q_shortage;
ushort init_state;
uchar cur_dvc_qng[ASC_MAX_TID + 1];
uchar max_dvc_qng[ASC_MAX_TID + 1];
ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
ASC_DVC_CFG *cfg;
ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
char redo_scam;
ushort res2;
uchar dos_int13_table[ASC_MAX_TID + 1];
ASC_DCNT max_dma_count;
ASC_SCSI_BIT_ID_TYPE no_scam;
ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
uchar max_sdtr_index;
uchar host_init_sdtr_index;
struct asc_board *drv_ptr;
ASC_DCNT uc_break;
} ASC_DVC_VAR;
typedef struct asc_dvc_inq_info {
uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
} ASC_DVC_INQ_INFO;
typedef struct asc_cap_info {
ASC_DCNT lba;
ASC_DCNT blk_size;
} ASC_CAP_INFO;
typedef struct asc_cap_info_array {
ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
} ASC_CAP_INFO_ARRAY;
#define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
#define ASC_MCNTL_NULL_TARGET (ushort)0x0002
#define ASC_CNTL_INITIATOR (ushort)0x0001
#define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
#define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
#define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
#define ASC_CNTL_NO_SCAM (ushort)0x0010
#define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
#define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
#define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
#define ASC_CNTL_RESET_SCSI (ushort)0x0200
#define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
#define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
#define ASC_CNTL_SCSI_PARITY (ushort)0x1000
#define ASC_CNTL_BURST_MODE (ushort)0x2000
#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
#define ASC_EEP_DVC_CFG_BEG_VL 2
#define ASC_EEP_MAX_DVC_ADDR_VL 15
#define ASC_EEP_DVC_CFG_BEG 32
#define ASC_EEP_MAX_DVC_ADDR 45
#define ASC_EEP_DEFINED_WORDS 10
#define ASC_EEP_MAX_ADDR 63
#define ASC_EEP_RES_WORDS 0
#define ASC_EEP_MAX_RETRY 20
#define ASC_MAX_INIT_BUSY_RETRY 8
#define ASC_EEP_ISA_PNP_WSIZE 16
/*
* These macros keep the chip SCSI id and ISA DMA speed
* bitfields in board order. C bitfields aren't portable
* between big and little-endian platforms so they are
* not used.
*/
#define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
#define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
typedef struct asceep_config {
ushort cfg_lsw;
ushort cfg_msw;
uchar init_sdtr;
uchar disc_enable;
uchar use_cmd_qng;
uchar start_motor;
uchar max_total_qng;
uchar max_tag_qng;
uchar bios_scan;
uchar power_up_wait;
uchar no_scam;
uchar id_speed; /* low order 4 bits is chip scsi id */
/* high order 4 bits is isa dma speed */
uchar dos_int13_table[ASC_MAX_TID + 1];
uchar adapter_info[6];
ushort cntl;
ushort chksum;
} ASCEEP_CONFIG;
#define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800
#define ASC_PCI_CFG_LSW_BURST_MODE 0x0080
#define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020
#define ASC_EEP_CMD_READ 0x80
#define ASC_EEP_CMD_WRITE 0x40
#define ASC_EEP_CMD_WRITE_ABLE 0x30
#define ASC_EEP_CMD_WRITE_DISABLE 0x00
#define ASC_OVERRUN_BSIZE 0x00000048UL
#define ASC_CTRL_BREAK_ONCE 0x0001
#define ASC_CTRL_BREAK_STAY_IDLE 0x0002
#define ASCV_MSGOUT_BEG 0x0000
#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
#define ASCV_BREAK_SAVED_CODE (ushort)0x0006
#define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
#define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
#define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
#define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
#define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
#define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
#define ASCV_BREAK_ADDR (ushort)0x0028
#define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
#define ASCV_BREAK_CONTROL (ushort)0x002C
#define ASCV_BREAK_HIT_COUNT (ushort)0x002E
#define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
#define ASCV_MCODE_CHKSUM_W (ushort)0x0032
#define ASCV_MCODE_SIZE_W (ushort)0x0034
#define ASCV_STOP_CODE_B (ushort)0x0036
#define ASCV_DVC_ERR_CODE_B (ushort)0x0037
#define ASCV_OVERRUN_PADDR_D (ushort)0x0038
#define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
#define ASCV_HALTCODE_W (ushort)0x0040
#define ASCV_CHKSUM_W (ushort)0x0042
#define ASCV_MC_DATE_W (ushort)0x0044
#define ASCV_MC_VER_W (ushort)0x0046
#define ASCV_NEXTRDY_B (ushort)0x0048
#define ASCV_DONENEXT_B (ushort)0x0049
#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
#define ASCV_SCSIBUSY_B (ushort)0x004B
#define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
#define ASCV_CURCDB_B (ushort)0x004D
#define ASCV_RCLUN_B (ushort)0x004E
#define ASCV_BUSY_QHEAD_B (ushort)0x004F
#define ASCV_DISC1_QHEAD_B (ushort)0x0050
#define ASCV_DISC_ENABLE_B (ushort)0x0052
#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
#define ASCV_HOSTSCSI_ID_B (ushort)0x0055
#define ASCV_MCODE_CNTL_B (ushort)0x0056
#define ASCV_NULL_TARGET_B (ushort)0x0057
#define ASCV_FREE_Q_HEAD_W (ushort)0x0058
#define ASCV_DONE_Q_TAIL_W (ushort)0x005A
#define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
#define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
#define ASCV_HOST_FLAG_B (ushort)0x005D
#define ASCV_TOTAL_READY_Q_B (ushort)0x0064
#define ASCV_VER_SERIAL_B (ushort)0x0065
#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
#define ASCV_WTM_FLAG_B (ushort)0x0068
#define ASCV_RISC_FLAG_B (ushort)0x006A
#define ASCV_REQ_SG_LIST_QP (ushort)0x006B
#define ASC_HOST_FLAG_IN_ISR 0x01
#define ASC_HOST_FLAG_ACK_INT 0x02
#define ASC_RISC_FLAG_GEN_INT 0x01
#define ASC_RISC_FLAG_REQ_SG_LIST 0x02
#define IOP_CTRL (0x0F)
#define IOP_STATUS (0x0E)
#define IOP_INT_ACK IOP_STATUS
#define IOP_REG_IFC (0x0D)
#define IOP_SYN_OFFSET (0x0B)
#define IOP_EXTRA_CONTROL (0x0D)
#define IOP_REG_PC (0x0C)
#define IOP_RAM_ADDR (0x0A)
#define IOP_RAM_DATA (0x08)
#define IOP_EEP_DATA (0x06)
#define IOP_EEP_CMD (0x07)
#define IOP_VERSION (0x03)
#define IOP_CONFIG_HIGH (0x04)
#define IOP_CONFIG_LOW (0x02)
#define IOP_SIG_BYTE (0x01)
#define IOP_SIG_WORD (0x00)
#define IOP_REG_DC1 (0x0E)
#define IOP_REG_DC0 (0x0C)
#define IOP_REG_SB (0x0B)
#define IOP_REG_DA1 (0x0A)
#define IOP_REG_DA0 (0x08)
#define IOP_REG_SC (0x09)
#define IOP_DMA_SPEED (0x07)
#define IOP_REG_FLAG (0x07)
#define IOP_FIFO_H (0x06)
#define IOP_FIFO_L (0x04)
#define IOP_REG_ID (0x05)
#define IOP_REG_QP (0x03)
#define IOP_REG_IH (0x02)
#define IOP_REG_IX (0x01)
#define IOP_REG_AX (0x00)
#define IFC_REG_LOCK (0x00)
#define IFC_REG_UNLOCK (0x09)
#define IFC_WR_EN_FILTER (0x10)
#define IFC_RD_NO_EEPROM (0x10)
#define IFC_SLEW_RATE (0x20)
#define IFC_ACT_NEG (0x40)
#define IFC_INP_FILTER (0x80)
#define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
#define SC_SEL (uchar)(0x80)
#define SC_BSY (uchar)(0x40)
#define SC_ACK (uchar)(0x20)
#define SC_REQ (uchar)(0x10)
#define SC_ATN (uchar)(0x08)
#define SC_IO (uchar)(0x04)
#define SC_CD (uchar)(0x02)
#define SC_MSG (uchar)(0x01)
#define SEC_SCSI_CTL (uchar)(0x80)
#define SEC_ACTIVE_NEGATE (uchar)(0x40)
#define SEC_SLEW_RATE (uchar)(0x20)
#define SEC_ENABLE_FILTER (uchar)(0x10)
#define ASC_HALT_EXTMSG_IN (ushort)0x8000
#define ASC_HALT_CHK_CONDITION (ushort)0x8100
#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
#define ASC_MAX_QNO 0xF8
#define ASC_DATA_SEC_BEG (ushort)0x0080
#define ASC_DATA_SEC_END (ushort)0x0080
#define ASC_CODE_SEC_BEG (ushort)0x0080
#define ASC_CODE_SEC_END (ushort)0x0080
#define ASC_QADR_BEG (0x4000)
#define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
#define ASC_QADR_END (ushort)0x7FFF
#define ASC_QLAST_ADR (ushort)0x7FC0
#define ASC_QBLK_SIZE 0x40
#define ASC_BIOS_DATA_QBEG 0xF8
#define ASC_MIN_ACTIVE_QNO 0x01
#define ASC_QLINK_END 0xFF
#define ASC_EEPROM_WORDS 0x10
#define ASC_MAX_MGS_LEN 0x10
#define ASC_BIOS_ADDR_DEF 0xDC00
#define ASC_BIOS_SIZE 0x3800
#define ASC_BIOS_RAM_OFF 0x3800
#define ASC_BIOS_RAM_SIZE 0x800
#define ASC_BIOS_MIN_ADDR 0xC000
#define ASC_BIOS_MAX_ADDR 0xEC00
#define ASC_BIOS_BANK_SIZE 0x0400
#define ASC_MCODE_START_ADDR 0x0080
#define ASC_CFG0_HOST_INT_ON 0x0020
#define ASC_CFG0_BIOS_ON 0x0040
#define ASC_CFG0_VERA_BURST_ON 0x0080
#define ASC_CFG0_SCSI_PARITY_ON 0x0800
#define ASC_CFG1_SCSI_TARGET_ON 0x0080
#define ASC_CFG1_LRAM_8BITS_ON 0x0800
#define ASC_CFG_MSW_CLR_MASK 0x3080
#define CSW_TEST1 (ASC_CS_TYPE)0x8000
#define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
#define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
#define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
#define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
#define CSW_TEST2 (ASC_CS_TYPE)0x0400
#define CSW_TEST3 (ASC_CS_TYPE)0x0200
#define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
#define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
#define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
#define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
#define CSW_HALTED (ASC_CS_TYPE)0x0010
#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
#define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
#define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
#define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
#define CIW_INT_ACK (ASC_CS_TYPE)0x0100
#define CIW_TEST1 (ASC_CS_TYPE)0x0200
#define CIW_TEST2 (ASC_CS_TYPE)0x0400
#define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
#define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
#define CC_CHIP_RESET (uchar)0x80
#define CC_SCSI_RESET (uchar)0x40
#define CC_HALT (uchar)0x20
#define CC_SINGLE_STEP (uchar)0x10
#define CC_DMA_ABLE (uchar)0x08
#define CC_TEST (uchar)0x04
#define CC_BANK_ONE (uchar)0x02
#define CC_DIAG (uchar)0x01
#define ASC_1000_ID0W 0x04C1
#define ASC_1000_ID0W_FIX 0x00C1
#define ASC_1000_ID1B 0x25
#define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50)
#define ASC_EISA_SMALL_IOP_GAP (0x0020)
#define ASC_EISA_MIN_IOP_ADDR (0x0C30)
#define ASC_EISA_MAX_IOP_ADDR (0xFC50)
#define ASC_EISA_REV_IOP_MASK (0x0C83)
#define ASC_EISA_PID_IOP_MASK (0x0C80)
#define ASC_EISA_CFG_IOP_MASK (0x0C86)
#define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
#define ASC_EISA_ID_740 0x01745004UL
#define ASC_EISA_ID_750 0x01755004UL
#define INS_HALTINT (ushort)0x6281
#define INS_HALT (ushort)0x6280
#define INS_SINT (ushort)0x6200
#define INS_RFLAG_WTM (ushort)0x7380
#define ASC_MC_SAVE_CODE_WSIZE 0x500
#define ASC_MC_SAVE_DATA_WSIZE 0x40
typedef struct asc_mc_saved {
ushort data[ASC_MC_SAVE_DATA_WSIZE];
ushort code[ASC_MC_SAVE_CODE_WSIZE];
} ASC_MC_SAVED;
#define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
#define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
#define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
#define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
#define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
#define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
#define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
#define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
#define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
#define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
#define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data));
#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id));
#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data);
#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id));
#define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
#define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
#define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
#define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
#define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
#define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
#define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
#define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
#define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
#define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
#define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
#define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
#define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
#define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
#define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
#define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
#define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
#define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
#define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
#define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
#define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
#define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
#define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
#define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
#define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
#define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
#define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
#define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
#define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
#define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
#define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
#define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
#define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
#define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
#define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
#define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
#define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
#define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
#define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
#define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
#define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
#define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
#define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
#define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
#define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
#define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
#define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
#define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
#define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
#define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
#define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
STATIC int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg);
STATIC int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg);
STATIC void AscWaitEEPRead(void);
STATIC void AscWaitEEPWrite(void);
STATIC ushort AscReadEEPWord(PortAddr, uchar);
STATIC ushort AscWriteEEPWord(PortAddr, uchar, ushort);
STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
STATIC int AscSetEEPConfigOnce(PortAddr, ASCEEP_CONFIG *, ushort);
STATIC int AscSetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
STATIC int AscStartChip(PortAddr);
STATIC int AscStopChip(PortAddr);
STATIC void AscSetChipIH(PortAddr, ushort);
STATIC int AscIsChipHalted(PortAddr);
STATIC void AscAckInterrupt(PortAddr);
STATIC void AscDisableInterrupt(PortAddr);
STATIC void AscEnableInterrupt(PortAddr);
STATIC void AscSetBank(PortAddr, uchar);
STATIC int AscResetChipAndScsiBus(ASC_DVC_VAR *);
#ifdef CONFIG_ISA
STATIC ushort AscGetIsaDmaChannel(PortAddr);
STATIC ushort AscSetIsaDmaChannel(PortAddr, ushort);
STATIC uchar AscSetIsaDmaSpeed(PortAddr, uchar);
STATIC uchar AscGetIsaDmaSpeed(PortAddr);
#endif /* CONFIG_ISA */
STATIC uchar AscReadLramByte(PortAddr, ushort);
STATIC ushort AscReadLramWord(PortAddr, ushort);
#if CC_VERY_LONG_SG_LIST
STATIC ASC_DCNT AscReadLramDWord(PortAddr, ushort);
#endif /* CC_VERY_LONG_SG_LIST */
STATIC void AscWriteLramWord(PortAddr, ushort, ushort);
STATIC void AscWriteLramByte(PortAddr, ushort, uchar);
STATIC ASC_DCNT AscMemSumLramWord(PortAddr, ushort, int);
STATIC void AscMemWordSetLram(PortAddr, ushort, ushort, int);
STATIC void AscMemWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
STATIC void AscMemDWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
STATIC void AscMemWordCopyPtrFromLram(PortAddr, ushort, uchar *, int);
STATIC ushort AscInitAscDvcVar(ASC_DVC_VAR *);
STATIC ushort AscInitFromEEP(ASC_DVC_VAR *);
STATIC ushort AscInitFromAscDvcVar(ASC_DVC_VAR *);
STATIC ushort AscInitMicroCodeVar(ASC_DVC_VAR *);
STATIC int AscTestExternalLram(ASC_DVC_VAR *);
STATIC uchar AscMsgOutSDTR(ASC_DVC_VAR *, uchar, uchar);
STATIC uchar AscCalSDTRData(ASC_DVC_VAR *, uchar, uchar);
STATIC void AscSetChipSDTR(PortAddr, uchar, uchar);
STATIC uchar AscGetSynPeriodIndex(ASC_DVC_VAR *, uchar);
STATIC uchar AscAllocFreeQueue(PortAddr, uchar);
STATIC uchar AscAllocMultipleFreeQueue(PortAddr, uchar, uchar);
STATIC int AscHostReqRiscHalt(PortAddr);
STATIC int AscStopQueueExe(PortAddr);
STATIC int AscSendScsiQueue(ASC_DVC_VAR *,
ASC_SCSI_Q * scsiq,
uchar n_q_required);
STATIC int AscPutReadyQueue(ASC_DVC_VAR *,
ASC_SCSI_Q *, uchar);
STATIC int AscPutReadySgListQueue(ASC_DVC_VAR *,
ASC_SCSI_Q *, uchar);
STATIC int AscSetChipSynRegAtID(PortAddr, uchar, uchar);
STATIC int AscSetRunChipSynRegAtID(PortAddr, uchar, uchar);
STATIC ushort AscInitLram(ASC_DVC_VAR *);
STATIC ushort AscInitQLinkVar(ASC_DVC_VAR *);
STATIC int AscSetLibErrorCode(ASC_DVC_VAR *, ushort);
STATIC int AscIsrChipHalted(ASC_DVC_VAR *);
STATIC uchar _AscCopyLramScsiDoneQ(PortAddr, ushort,
ASC_QDONE_INFO *, ASC_DCNT);
STATIC int AscIsrQDone(ASC_DVC_VAR *);
STATIC int AscCompareString(uchar *, uchar *, int);
#ifdef CONFIG_ISA
STATIC ushort AscGetEisaChipCfg(PortAddr);
STATIC ASC_DCNT AscGetEisaProductID(PortAddr);
STATIC PortAddr AscSearchIOPortAddrEISA(PortAddr);
STATIC PortAddr AscSearchIOPortAddr11(PortAddr);
STATIC PortAddr AscSearchIOPortAddr(PortAddr, ushort);
STATIC void AscSetISAPNPWaitForKey(void);
#endif /* CONFIG_ISA */
STATIC uchar AscGetChipScsiCtrl(PortAddr);
STATIC uchar AscSetChipScsiID(PortAddr, uchar);
STATIC uchar AscGetChipVersion(PortAddr, ushort);
STATIC ushort AscGetChipBusType(PortAddr);
STATIC ASC_DCNT AscLoadMicroCode(PortAddr, ushort, uchar *, ushort);
STATIC int AscFindSignature(PortAddr);
STATIC void AscToggleIRQAct(PortAddr);
STATIC uchar AscGetChipIRQ(PortAddr, ushort);
STATIC uchar AscSetChipIRQ(PortAddr, uchar, ushort);
STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
STATIC inline ulong DvcEnterCritical(void);
STATIC inline void DvcLeaveCritical(ulong);
#ifdef CONFIG_PCI
STATIC uchar DvcReadPCIConfigByte(ASC_DVC_VAR *, ushort);
STATIC void DvcWritePCIConfigByte(ASC_DVC_VAR *,
ushort, uchar);
#endif /* CONFIG_PCI */
STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
STATIC void DvcSleepMilliSecond(ASC_DCNT);
STATIC void DvcDelayNanoSecond(ASC_DVC_VAR *, ASC_DCNT);
STATIC void DvcPutScsiQ(PortAddr, ushort, uchar *, int);
STATIC void DvcGetQinfo(PortAddr, ushort, uchar *, int);
STATIC ushort AscInitGetConfig(ASC_DVC_VAR *);
STATIC ushort AscInitSetConfig(ASC_DVC_VAR *);
STATIC ushort AscInitAsc1000Driver(ASC_DVC_VAR *);
STATIC void AscAsyncFix(ASC_DVC_VAR *, uchar,
ASC_SCSI_INQUIRY *);
STATIC int AscTagQueuingSafe(ASC_SCSI_INQUIRY *);
STATIC void AscInquiryHandling(ASC_DVC_VAR *,
uchar, ASC_SCSI_INQUIRY *);
STATIC int AscExeScsiQueue(ASC_DVC_VAR *, ASC_SCSI_Q *);
STATIC int AscISR(ASC_DVC_VAR *);
STATIC uint AscGetNumOfFreeQueue(ASC_DVC_VAR *, uchar,
uchar);
STATIC int AscSgListToQueue(int);
#ifdef CONFIG_ISA
STATIC void AscEnableIsaDma(uchar);
#endif /* CONFIG_ISA */
STATIC ASC_DCNT AscGetMaxDmaCount(ushort);
/*
* --- Adv Library Constants and Macros
*/
#define ADV_LIB_VERSION_MAJOR 5
#define ADV_LIB_VERSION_MINOR 14
/*
* Define Adv Library required special types.
*/
/*
* Portable Data Types
*
* Any instance where a 32-bit long or pointer type is assumed
* for precision or HW defined structures, the following define
* types must be used. In Linux the char, short, and int types
* are all consistent at 8, 16, and 32 bits respectively. Pointers
* and long types are 64 bits on Alpha and UltraSPARC.
*/
#define ADV_PADDR __u32 /* Physical address data type. */
#define ADV_VADDR __u32 /* Virtual address data type. */
#define ADV_DCNT __u32 /* Unsigned Data count type. */
#define ADV_SDCNT __s32 /* Signed Data count type. */
/*
* These macros are used to convert a virtual address to a
* 32-bit value. This currently can be used on Linux Alpha
* which uses 64-bit virtual address but a 32-bit bus address.
* This is likely to break in the future, but doing this now
* will give us time to change the HW and FW to handle 64-bit
* addresses.
*/
#define ADV_VADDR_TO_U32 virt_to_bus
#define ADV_U32_TO_VADDR bus_to_virt
#define AdvPortAddr ulong /* Virtual memory address size */
/*
* Define Adv Library required memory access macros.
*/
#define ADV_MEM_READB(addr) readb(addr)
#define ADV_MEM_READW(addr) readw(addr)
#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
/*
* For wide boards a CDB length maximum of 16 bytes
* is supported.
*/
#define ADV_MAX_CDB_LEN 16
/*
* Define total number of simultaneous maximum element scatter-gather
* request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
* maximum number of outstanding commands per wide host adapter. Each
* command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
* elements. Allow each command to have at least one ADV_SG_BLOCK structure.
* This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
* structures or 255 scatter-gather elements.
*
*/
#define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
/*
* Define Adv Library required maximum number of scatter-gather
* elements per request.
*/
#define ADV_MAX_SG_LIST 255
/* Number of SG blocks needed. */
#define ADV_NUM_SG_BLOCK \
((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
/* Total contiguous memory needed for SG blocks. */
#define ADV_SG_TOTAL_MEM_SIZE \
(sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
#define ADV_PAGE_SIZE PAGE_SIZE
#define ADV_NUM_PAGE_CROSSING \
((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
/* a_condor.h */
#define ADV_PCI_VENDOR_ID 0x10CD
#define ADV_PCI_DEVICE_ID_REV_A 0x2300
#define ADV_PCI_DEVID_38C0800_REV1 0x2500
#define ADV_PCI_DEVID_38C1600_REV1 0x2700
#define ADV_EEP_DVC_CFG_BEGIN (0x00)
#define ADV_EEP_DVC_CFG_END (0x15)
#define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
#define ADV_EEP_MAX_WORD_ADDR (0x1E)
#define ADV_EEP_DELAY_MS 100
#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
/*
* For the ASC3550 Bit 13 is Termination Polarity control bit.
* For later ICs Bit 13 controls whether the CIS (Card Information
* Service Section) is loaded from EEPROM.
*/
#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
/*
* ASC38C1600 Bit 11
*
* If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
* INT A in the PCI Configuration Space Int Pin field. If it is 1, then
* Function 0 will specify INT B.
*
* If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
* INT B in the PCI Configuration Space Int Pin field. If it is 1, then
* Function 1 will specify INT A.
*/
#define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
typedef struct adveep_3550_config
{
/* Word Offset, Description */
ushort cfg_lsw; /* 00 power up initialization */
/* bit 13 set - Term Polarity Control */
/* bit 14 set - BIOS Enable */
/* bit 15 set - Big Endian Mode */
ushort cfg_msw; /* 01 unused */
ushort disc_enable; /* 02 disconnect enable */
ushort wdtr_able; /* 03 Wide DTR able */
ushort sdtr_able; /* 04 Synchronous DTR able */
ushort start_motor; /* 05 send start up motor */
ushort tagqng_able; /* 06 tag queuing able */
ushort bios_scan; /* 07 BIOS device control */
ushort scam_tolerant; /* 08 no scam */
uchar adapter_scsi_id; /* 09 Host Adapter ID */
uchar bios_boot_delay; /* power up wait */
uchar scsi_reset_delay; /* 10 reset delay */
uchar bios_id_lun; /* first boot device scsi id & lun */
/* high nibble is lun */
/* low nibble is scsi id */
uchar termination; /* 11 0 - automatic */
/* 1 - low off / high off */
/* 2 - low off / high on */
/* 3 - low on / high on */
/* There is no low on / high off */
uchar reserved1; /* reserved byte (not used) */
ushort bios_ctrl; /* 12 BIOS control bits */
/* bit 0 BIOS don't act as initiator. */
/* bit 1 BIOS > 1 GB support */
/* bit 2 BIOS > 2 Disk Support */
/* bit 3 BIOS don't support removables */
/* bit 4 BIOS support bootable CD */
/* bit 5 BIOS scan enabled */
/* bit 6 BIOS support multiple LUNs */
/* bit 7 BIOS display of message */
/* bit 8 SCAM disabled */
/* bit 9 Reset SCSI bus during init. */
/* bit 10 */
/* bit 11 No verbose initialization. */
/* bit 12 SCSI parity enabled */
/* bit 13 */
/* bit 14 */
/* bit 15 */
ushort ultra_able; /* 13 ULTRA speed able */
ushort reserved2; /* 14 reserved */
uchar max_host_qng; /* 15 maximum host queuing */
uchar max_dvc_qng; /* maximum per device queuing */
ushort dvc_cntl; /* 16 control bit for driver */
ushort bug_fix; /* 17 control bit for bug fix */
ushort serial_number_word1; /* 18 Board serial number word 1 */
ushort serial_number_word2; /* 19 Board serial number word 2 */
ushort serial_number_word3; /* 20 Board serial number word 3 */
ushort check_sum; /* 21 EEP check sum */
uchar oem_name[16]; /* 22 OEM name */
ushort dvc_err_code; /* 30 last device driver error code */
ushort adv_err_code; /* 31 last uc and Adv Lib error code */
ushort adv_err_addr; /* 32 last uc error address */
ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
ushort saved_adv_err_addr; /* 35 saved last uc error address */
ushort num_of_err; /* 36 number of error */
} ADVEEP_3550_CONFIG;
typedef struct adveep_38C0800_config
{
/* Word Offset, Description */
ushort cfg_lsw; /* 00 power up initialization */
/* bit 13 set - Load CIS */
/* bit 14 set - BIOS Enable */
/* bit 15 set - Big Endian Mode */
ushort cfg_msw; /* 01 unused */
ushort disc_enable; /* 02 disconnect enable */
ushort wdtr_able; /* 03 Wide DTR able */
ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
ushort start_motor; /* 05 send start up motor */
ushort tagqng_able; /* 06 tag queuing able */
ushort bios_scan; /* 07 BIOS device control */
ushort scam_tolerant; /* 08 no scam */
uchar adapter_scsi_id; /* 09 Host Adapter ID */
uchar bios_boot_delay; /* power up wait */
uchar scsi_reset_delay; /* 10 reset delay */
uchar bios_id_lun; /* first boot device scsi id & lun */
/* high nibble is lun */
/* low nibble is scsi id */
uchar termination_se; /* 11 0 - automatic */
/* 1 - low off / high off */
/* 2 - low off / high on */
/* 3 - low on / high on */
/* There is no low on / high off */
uchar termination_lvd; /* 11 0 - automatic */
/* 1 - low off / high off */
/* 2 - low off / high on */
/* 3 - low on / high on */
/* There is no low on / high off */
ushort bios_ctrl; /* 12 BIOS control bits */
/* bit 0 BIOS don't act as initiator. */
/* bit 1 BIOS > 1 GB support */
/* bit 2 BIOS > 2 Disk Support */
/* bit 3 BIOS don't support removables */
/* bit 4 BIOS support bootable CD */
/* bit 5 BIOS scan enabled */
/* bit 6 BIOS support multiple LUNs */
/* bit 7 BIOS display of message */
/* bit 8 SCAM disabled */
/* bit 9 Reset SCSI bus during init. */
/* bit 10 */
/* bit 11 No verbose initialization. */
/* bit 12 SCSI parity enabled */
/* bit 13 */
/* bit 14 */
/* bit 15 */
ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
uchar max_host_qng; /* 15 maximum host queueing */
uchar max_dvc_qng; /* maximum per device queuing */
ushort dvc_cntl; /* 16 control bit for driver */
ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
ushort serial_number_word1; /* 18 Board serial number word 1 */
ushort serial_number_word2; /* 19 Board serial number word 2 */
ushort serial_number_word3; /* 20 Board serial number word 3 */
ushort check_sum; /* 21 EEP check sum */
uchar oem_name[16]; /* 22 OEM name */
ushort dvc_err_code; /* 30 last device driver error code */
ushort adv_err_code; /* 31 last uc and Adv Lib error code */
ushort adv_err_addr; /* 32 last uc error address */
ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
ushort saved_adv_err_addr; /* 35 saved last uc error address */
ushort reserved36; /* 36 reserved */
ushort reserved37; /* 37 reserved */
ushort reserved38; /* 38 reserved */
ushort reserved39; /* 39 reserved */
ushort reserved40; /* 40 reserved */
ushort reserved41; /* 41 reserved */
ushort reserved42; /* 42 reserved */
ushort reserved43; /* 43 reserved */
ushort reserved44; /* 44 reserved */
ushort reserved45; /* 45 reserved */
ushort reserved46; /* 46 reserved */
ushort reserved47; /* 47 reserved */
ushort reserved48; /* 48 reserved */
ushort reserved49; /* 49 reserved */
ushort reserved50; /* 50 reserved */
ushort reserved51; /* 51 reserved */
ushort reserved52; /* 52 reserved */
ushort reserved53; /* 53 reserved */
ushort reserved54; /* 54 reserved */
ushort reserved55; /* 55 reserved */
ushort cisptr_lsw; /* 56 CIS PTR LSW */
ushort cisprt_msw; /* 57 CIS PTR MSW */
ushort subsysvid; /* 58 SubSystem Vendor ID */
ushort subsysid; /* 59 SubSystem ID */
ushort reserved60; /* 60 reserved */
ushort reserved61; /* 61 reserved */
ushort reserved62; /* 62 reserved */
ushort reserved63; /* 63 reserved */
} ADVEEP_38C0800_CONFIG;
typedef struct adveep_38C1600_config
{
/* Word Offset, Description */
ushort cfg_lsw; /* 00 power up initialization */
/* bit 11 set - Func. 0 INTB, Func. 1 INTA */
/* clear - Func. 0 INTA, Func. 1 INTB */
/* bit 13 set - Load CIS */
/* bit 14 set - BIOS Enable */
/* bit 15 set - Big Endian Mode */
ushort cfg_msw; /* 01 unused */
ushort disc_enable; /* 02 disconnect enable */
ushort wdtr_able; /* 03 Wide DTR able */
ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
ushort start_motor; /* 05 send start up motor */
ushort tagqng_able; /* 06 tag queuing able */
ushort bios_scan; /* 07 BIOS device control */
ushort scam_tolerant; /* 08 no scam */
uchar adapter_scsi_id; /* 09 Host Adapter ID */
uchar bios_boot_delay; /* power up wait */
uchar scsi_reset_delay; /* 10 reset delay */
uchar bios_id_lun; /* first boot device scsi id & lun */
/* high nibble is lun */
/* low nibble is scsi id */
uchar termination_se; /* 11 0 - automatic */
/* 1 - low off / high off */
/* 2 - low off / high on */
/* 3 - low on / high on */
/* There is no low on / high off */
uchar termination_lvd; /* 11 0 - automatic */
/* 1 - low off / high off */
/* 2 - low off / high on */
/* 3 - low on / high on */
/* There is no low on / high off */
ushort bios_ctrl; /* 12 BIOS control bits */
/* bit 0 BIOS don't act as initiator. */
/* bit 1 BIOS > 1 GB support */
/* bit 2 BIOS > 2 Disk Support */
/* bit 3 BIOS don't support removables */
/* bit 4 BIOS support bootable CD */
/* bit 5 BIOS scan enabled */
/* bit 6 BIOS support multiple LUNs */
/* bit 7 BIOS display of message */
/* bit 8 SCAM disabled */
/* bit 9 Reset SCSI bus during init. */
/* bit 10 Basic Integrity Checking disabled */
/* bit 11 No verbose initialization. */
/* bit 12 SCSI parity enabled */
/* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
/* bit 14 */
/* bit 15 */
ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
uchar max_host_qng; /* 15 maximum host queueing */
uchar max_dvc_qng; /* maximum per device queuing */
ushort dvc_cntl; /* 16 control bit for driver */
ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
ushort serial_number_word1; /* 18 Board serial number word 1 */
ushort serial_number_word2; /* 19 Board serial number word 2 */
ushort serial_number_word3; /* 20 Board serial number word 3 */
ushort check_sum; /* 21 EEP check sum */
uchar oem_name[16]; /* 22 OEM name */
ushort dvc_err_code; /* 30 last device driver error code */
ushort adv_err_code; /* 31 last uc and Adv Lib error code */
ushort adv_err_addr; /* 32 last uc error address */
ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
ushort saved_adv_err_addr; /* 35 saved last uc error address */
ushort reserved36; /* 36 reserved */
ushort reserved37; /* 37 reserved */
ushort reserved38; /* 38 reserved */
ushort reserved39; /* 39 reserved */
ushort reserved40; /* 40 reserved */
ushort reserved41; /* 41 reserved */
ushort reserved42; /* 42 reserved */
ushort reserved43; /* 43 reserved */
ushort reserved44; /* 44 reserved */
ushort reserved45; /* 45 reserved */
ushort reserved46; /* 46 reserved */
ushort reserved47; /* 47 reserved */
ushort reserved48; /* 48 reserved */
ushort reserved49; /* 49 reserved */
ushort reserved50; /* 50 reserved */
ushort reserved51; /* 51 reserved */
ushort reserved52; /* 52 reserved */
ushort reserved53; /* 53 reserved */
ushort reserved54; /* 54 reserved */
ushort reserved55; /* 55 reserved */
ushort cisptr_lsw; /* 56 CIS PTR LSW */
ushort cisprt_msw; /* 57 CIS PTR MSW */
ushort subsysvid; /* 58 SubSystem Vendor ID */
ushort subsysid; /* 59 SubSystem ID */
ushort reserved60; /* 60 reserved */
ushort reserved61; /* 61 reserved */
ushort reserved62; /* 62 reserved */
ushort reserved63; /* 63 reserved */
} ADVEEP_38C1600_CONFIG;
/*
* EEPROM Commands
*/
#define ASC_EEP_CMD_DONE 0x0200
#define ASC_EEP_CMD_DONE_ERR 0x0001
/* cfg_word */
#define EEP_CFG_WORD_BIG_ENDIAN 0x8000
/* bios_ctrl */
#define BIOS_CTRL_BIOS 0x0001
#define BIOS_CTRL_EXTENDED_XLAT 0x0002
#define BIOS_CTRL_GT_2_DISK 0x0004
#define BIOS_CTRL_BIOS_REMOVABLE 0x0008
#define BIOS_CTRL_BOOTABLE_CD 0x0010
#define BIOS_CTRL_MULTIPLE_LUN 0x0040
#define BIOS_CTRL_DISPLAY_MSG 0x0080
#define BIOS_CTRL_NO_SCAM 0x0100
#define BIOS_CTRL_RESET_SCSI_BUS 0x0200
#define BIOS_CTRL_INIT_VERBOSE 0x0800
#define BIOS_CTRL_SCSI_PARITY 0x1000
#define BIOS_CTRL_AIPP_DIS 0x2000
#define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
#define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */
#define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
#define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
/*
* XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
* a special 16K Adv Library and Microcode version. After the issue is
* resolved, should restore 32K support.
*
* #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
*/
#define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
#define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */
#define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */
/*
* Byte I/O register address from base of 'iop_base'.
*/
#define IOPB_INTR_STATUS_REG 0x00
#define IOPB_CHIP_ID_1 0x01
#define IOPB_INTR_ENABLES 0x02
#define IOPB_CHIP_TYPE_REV 0x03
#define IOPB_RES_ADDR_4 0x04
#define IOPB_RES_ADDR_5 0x05
#define IOPB_RAM_DATA 0x06
#define IOPB_RES_ADDR_7 0x07
#define IOPB_FLAG_REG 0x08
#define IOPB_RES_ADDR_9 0x09
#define IOPB_RISC_CSR 0x0A
#define IOPB_RES_ADDR_B 0x0B
#define IOPB_RES_ADDR_C 0x0C
#define IOPB_RES_ADDR_D 0x0D
#define IOPB_SOFT_OVER_WR 0x0E
#define IOPB_RES_ADDR_F 0x0F
#define IOPB_MEM_CFG 0x10
#define IOPB_RES_ADDR_11 0x11
#define IOPB_GPIO_DATA 0x12
#define IOPB_RES_ADDR_13 0x13
#define IOPB_FLASH_PAGE 0x14
#define IOPB_RES_ADDR_15 0x15
#define IOPB_GPIO_CNTL 0x16
#define IOPB_RES_ADDR_17 0x17
#define IOPB_FLASH_DATA 0x18
#define IOPB_RES_ADDR_19 0x19
#define IOPB_RES_ADDR_1A 0x1A
#define IOPB_RES_ADDR_1B 0x1B
#define IOPB_RES_ADDR_1C 0x1C
#define IOPB_RES_ADDR_1D 0x1D
#define IOPB_RES_ADDR_1E 0x1E
#define IOPB_RES_ADDR_1F 0x1F
#define IOPB_DMA_CFG0 0x20
#define IOPB_DMA_CFG1 0x21
#define IOPB_TICKLE 0x22
#define IOPB_DMA_REG_WR 0x23
#define IOPB_SDMA_STATUS 0x24
#define IOPB_SCSI_BYTE_CNT 0x25
#define IOPB_HOST_BYTE_CNT 0x26
#define IOPB_BYTE_LEFT_TO_XFER 0x27
#define IOPB_BYTE_TO_XFER_0 0x28
#define IOPB_BYTE_TO_XFER_1 0x29
#define IOPB_BYTE_TO_XFER_2 0x2A
#define IOPB_BYTE_TO_XFER_3 0x2B
#define IOPB_ACC_GRP 0x2C
#define IOPB_RES_ADDR_2D 0x2D
#define IOPB_DEV_ID 0x2E
#define IOPB_RES_ADDR_2F 0x2F
#define IOPB_SCSI_DATA 0x30
#define IOPB_RES_ADDR_31 0x31
#define IOPB_RES_ADDR_32 0x32
#define IOPB_SCSI_DATA_HSHK 0x33
#define IOPB_SCSI_CTRL 0x34
#define IOPB_RES_ADDR_35 0x35
#define IOPB_RES_ADDR_36 0x36
#define IOPB_RES_ADDR_37 0x37
#define IOPB_RAM_BIST 0x38
#define IOPB_PLL_TEST 0x39
#define IOPB_PCI_INT_CFG 0x3A
#define IOPB_RES_ADDR_3B 0x3B
#define IOPB_RFIFO_CNT 0x3C
#define IOPB_RES_ADDR_3D 0x3D
#define IOPB_RES_ADDR_3E 0x3E
#define IOPB_RES_ADDR_3F 0x3F
/*
* Word I/O register address from base of 'iop_base'.
*/
#define IOPW_CHIP_ID_0 0x00 /* CID0 */
#define IOPW_CTRL_REG 0x02 /* CC */
#define IOPW_RAM_ADDR 0x04 /* LA */
#define IOPW_RAM_DATA 0x06 /* LD */
#define IOPW_RES_ADDR_08 0x08
#define IOPW_RISC_CSR 0x0A /* CSR */
#define IOPW_SCSI_CFG0 0x0C /* CFG0 */
#define IOPW_SCSI_CFG1 0x0E /* CFG1 */
#define IOPW_RES_ADDR_10 0x10
#define IOPW_SEL_MASK 0x12 /* SM */
#define IOPW_RES_ADDR_14 0x14
#define IOPW_FLASH_ADDR 0x16 /* FA */
#define IOPW_RES_ADDR_18 0x18
#define IOPW_EE_CMD 0x1A /* EC */
#define IOPW_EE_DATA 0x1C /* ED */
#define IOPW_SFIFO_CNT 0x1E /* SFC */
#define IOPW_RES_ADDR_20 0x20
#define IOPW_Q_BASE 0x22 /* QB */
#define IOPW_QP 0x24 /* QP */
#define IOPW_IX 0x26 /* IX */
#define IOPW_SP 0x28 /* SP */
#define IOPW_PC 0x2A /* PC */
#define IOPW_RES_ADDR_2C 0x2C
#define IOPW_RES_ADDR_2E 0x2E
#define IOPW_SCSI_DATA 0x30 /* SD */
#define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
#define IOPW_SCSI_CTRL 0x34 /* SC */
#define IOPW_HSHK_CFG 0x36 /* HCFG */
#define IOPW_SXFR_STATUS 0x36 /* SXS */
#define IOPW_SXFR_CNTL 0x38 /* SXL */
#define IOPW_SXFR_CNTH 0x3A /* SXH */
#define IOPW_RES_ADDR_3C 0x3C
#define IOPW_RFIFO_DATA 0x3E /* RFD */
/*
* Doubleword I/O register address from base of 'iop_base'.
*/
#define IOPDW_RES_ADDR_0 0x00
#define IOPDW_RAM_DATA 0x04
#define IOPDW_RES_ADDR_8 0x08
#define IOPDW_RES_ADDR_C 0x0C
#define IOPDW_RES_ADDR_10 0x10
#define IOPDW_COMMA 0x14
#define IOPDW_COMMB 0x18
#define IOPDW_RES_ADDR_1C 0x1C
#define IOPDW_SDMA_ADDR0 0x20
#define IOPDW_SDMA_ADDR1 0x24
#define IOPDW_SDMA_COUNT 0x28
#define IOPDW_SDMA_ERROR 0x2C
#define IOPDW_RDMA_ADDR0 0x30
#define IOPDW_RDMA_ADDR1 0x34
#define IOPDW_RDMA_COUNT 0x38
#define IOPDW_RDMA_ERROR 0x3C
#define ADV_CHIP_ID_BYTE 0x25
#define ADV_CHIP_ID_WORD 0x04C1
#define ADV_SC_SCSI_BUS_RESET 0x2000
#define ADV_INTR_ENABLE_HOST_INTR 0x01
#define ADV_INTR_ENABLE_SEL_INTR 0x02
#define ADV_INTR_ENABLE_DPR_INTR 0x04
#define ADV_INTR_ENABLE_RTA_INTR 0x08
#define ADV_INTR_ENABLE_RMA_INTR 0x10
#define ADV_INTR_ENABLE_RST_INTR 0x20
#define ADV_INTR_ENABLE_DPE_INTR 0x40
#define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
#define ADV_INTR_STATUS_INTRA 0x01
#define ADV_INTR_STATUS_INTRB 0x02
#define ADV_INTR_STATUS_INTRC 0x04
#define ADV_RISC_CSR_STOP (0x0000)
#define ADV_RISC_TEST_COND (0x2000)
#define ADV_RISC_CSR_RUN (0x4000)
#define ADV_RISC_CSR_SINGLE_STEP (0x8000)
#define ADV_CTRL_REG_HOST_INTR 0x0100
#define ADV_CTRL_REG_SEL_INTR 0x0200
#define ADV_CTRL_REG_DPR_INTR 0x0400
#define ADV_CTRL_REG_RTA_INTR 0x0800
#define ADV_CTRL_REG_RMA_INTR 0x1000
#define ADV_CTRL_REG_RES_BIT14 0x2000
#define ADV_CTRL_REG_DPE_INTR 0x4000
#define ADV_CTRL_REG_POWER_DONE 0x8000
#define ADV_CTRL_REG_ANY_INTR 0xFF00
#define ADV_CTRL_REG_CMD_RESET 0x00C6
#define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
#define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
#define ADV_TICKLE_NOP 0x00
#define ADV_TICKLE_A 0x01
#define ADV_TICKLE_B 0x02
#define ADV_TICKLE_C 0x03
#define ADV_SCSI_CTRL_RSTOUT 0x2000
#define AdvIsIntPending(port) \
(AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
/*
* SCSI_CFG0 Register bit definitions
*/
#define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
#define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
#define EVEN_PARITY 0x1000 /* Select Even Parity */
#define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
#define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
#define PRIM_MODE 0x0100 /* Primitive SCSI mode */
#define SCAM_EN 0x0080 /* Enable SCAM selection */
#define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
#define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
#define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
#define OUR_ID 0x000F /* SCSI ID */
/*
* SCSI_CFG1 Register bit definitions
*/
#define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
#define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
#define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
#define FILTER_SEL 0x0C00 /* Filter Period Selection */
#define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
#define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
#define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
#define ACTIVE_DBL 0x0200 /* Disable Active Negation */
#define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
#define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
#define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
#define TERM_CTL 0x0030 /* External SCSI Termination Bits */
#define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
#define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
#define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
/*
* Addendum for ASC-38C0800 Chip
*
* The ASC-38C1600 Chip uses the same definitions except that the
* bus mode override bits [12:10] have been moved to byte register
* offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
* SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
* is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
* Also each ASC-38C1600 function or channel uses only cable bits [5:4]
* and [1:0]. Bits [14], [7:6], [3:2] are unused.
*/
#define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
#define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
#define HVD 0x1000 /* HVD Device Detect */
#define LVD 0x0800 /* LVD Device Detect */
#define SE 0x0400 /* SE Device Detect */
#define TERM_LVD 0x00C0 /* LVD Termination Bits */
#define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
#define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
#define TERM_SE 0x0030 /* SE Termination Bits */
#define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
#define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
#define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
#define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
#define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
#define C_DET_SE 0x0003 /* SE Cable Detect Bits */
#define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
#define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
#define CABLE_ILLEGAL_A 0x7
/* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
#define CABLE_ILLEGAL_B 0xB
/* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
/*
* MEM_CFG Register bit definitions
*/
#define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
#define FAST_EE_CLK 0x20 /* Diagnostic Bit */
#define RAM_SZ 0x1C /* Specify size of RAM to RISC */
#define RAM_SZ_2KB 0x00 /* 2 KB */
#define RAM_SZ_4KB 0x04 /* 4 KB */
#define RAM_SZ_8KB 0x08 /* 8 KB */
#define RAM_SZ_16KB 0x0C /* 16 KB */
#define RAM_SZ_32KB 0x10 /* 32 KB */
#define RAM_SZ_64KB 0x14 /* 64 KB */
/*
* DMA_CFG0 Register bit definitions
*
* This register is only accessible to the host.
*/
#define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
#define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
#define FIFO_THRESH_16B 0x00 /* 16 bytes */
#define FIFO_THRESH_32B 0x20 /* 32 bytes */
#define FIFO_THRESH_48B 0x30 /* 48 bytes */
#define FIFO_THRESH_64B 0x40 /* 64 bytes */
#define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
#define FIFO_THRESH_96B 0x60 /* 96 bytes */
#define FIFO_THRESH_112B 0x70 /* 112 bytes */
#define START_CTL 0x0C /* DMA start conditions */
#define START_CTL_TH 0x00 /* Wait threshold level (default) */
#define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
#define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
#define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
#define READ_CMD 0x03 /* Memory Read Method */
#define READ_CMD_MR 0x00 /* Memory Read */
#define READ_CMD_MRL 0x02 /* Memory Read Long */
#define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
/*
* ASC-38C0800 RAM BIST Register bit definitions
*/
#define RAM_TEST_MODE 0x80
#define PRE_TEST_MODE 0x40
#define NORMAL_MODE 0x00
#define RAM_TEST_DONE 0x10
#define RAM_TEST_STATUS 0x0F
#define RAM_TEST_HOST_ERROR 0x08
#define RAM_TEST_INTRAM_ERROR 0x04
#define RAM_TEST_RISC_ERROR 0x02
#define RAM_TEST_SCSI_ERROR 0x01
#define RAM_TEST_SUCCESS 0x00
#define PRE_TEST_VALUE 0x05
#define NORMAL_VALUE 0x00
/*
* ASC38C1600 Definitions
*
* IOPB_PCI_INT_CFG Bit Field Definitions
*/
#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
/*
* Bit 1 can be set to change the interrupt for the Function to operate in
* Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
* Open Drain mode. Both functions of the ASC38C1600 must be set to the same
* mode, otherwise the operating mode is undefined.
*/
#define TOTEMPOLE 0x02
/*
* Bit 0 can be used to change the Int Pin for the Function. The value is
* 0 by default for both Functions with Function 0 using INT A and Function
* B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
* INT A is used.
*
* EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
* value specified in the PCI Configuration Space.
*/
#define INTAB 0x01
/* a_advlib.h */
/*
* Adv Library Status Definitions
*/
#define ADV_TRUE 1
#define ADV_FALSE 0
#define ADV_NOERROR 1
#define ADV_SUCCESS 1
#define ADV_BUSY 0
#define ADV_ERROR (-1)
/*
* ADV_DVC_VAR 'warn_code' values
*/
#define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
#define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
#define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
#define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */
#define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
#define ADV_MAX_TID 15 /* max. target identifier */
#define ADV_MAX_LUN 7 /* max. logical unit number */
/*
* Error code values are set in ADV_DVC_VAR 'err_code'.
*/
#define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
#define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
#define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
#define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
#define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
#define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
#define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
#define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
#define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
#define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
#define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
#define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
#define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
#define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
/*
* Fixed locations of microcode operating variables.
*/
#define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
#define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
#define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
#define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
#define ASC_MC_VERSION_NUM 0x003A /* microcode number */
#define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
#define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
#define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
#define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
#define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
#define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
#define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
#define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
#define ASC_MC_CHIP_TYPE 0x009A
#define ASC_MC_INTRB_CODE 0x009B
#define ASC_MC_WDTR_ABLE 0x009C
#define ASC_MC_SDTR_ABLE 0x009E
#define ASC_MC_TAGQNG_ABLE 0x00A0
#define ASC_MC_DISC_ENABLE 0x00A2
#define ASC_MC_IDLE_CMD_STATUS 0x00A4
#define ASC_MC_IDLE_CMD 0x00A6
#define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
#define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
#define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
#define ASC_MC_DEFAULT_MEM_CFG 0x00B0
#define ASC_MC_DEFAULT_SEL_MASK 0x00B2
#define ASC_MC_SDTR_DONE 0x00B6
#define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
#define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
#define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
#define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
#define ASC_MC_WDTR_DONE 0x0124
#define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
#define ASC_MC_ICQ 0x0160
#define ASC_MC_IRQ 0x0164
#define ASC_MC_PPR_ABLE 0x017A
/*
* BIOS LRAM variable absolute offsets.
*/
#define BIOS_CODESEG 0x54
#define BIOS_CODELEN 0x56
#define BIOS_SIGNATURE 0x58
#define BIOS_VERSION 0x5A
/*
* Microcode Control Flags
*
* Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
* and handled by the microcode.
*/
#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
/*
* ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
*/
#define HSHK_CFG_WIDE_XFR 0x8000
#define HSHK_CFG_RATE 0x0F00
#define HSHK_CFG_OFFSET 0x001F
#define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
#define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
#define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
#define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
#define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
#define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
#define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
#define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
#define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
#define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
#define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
#define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
/*
* Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
* ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
*/
#define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
#define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
/*
* All fields here are accessed by the board microcode and need to be
* little-endian.
*/
typedef struct adv_carr_t
{
ADV_VADDR carr_va; /* Carrier Virtual Address */
ADV_PADDR carr_pa; /* Carrier Physical Address */
ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
/*
* next_vpa [31:4] Carrier Virtual or Physical Next Pointer
*
* next_vpa [3:1] Reserved Bits
* next_vpa [0] Done Flag set in Response Queue.
*/
ADV_VADDR next_vpa;
} ADV_CARR_T;
/*
* Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
*/
#define ASC_NEXT_VPA_MASK 0xFFFFFFF0
#define ASC_RQ_DONE 0x00000001
#define ASC_RQ_GOOD 0x00000002
#define ASC_CQ_STOPPER 0x00000000
#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
#define ADV_CARRIER_NUM_PAGE_CROSSING \
(((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
(ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
#define ADV_CARRIER_BUFSIZE \
((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
/*
* ASC_SCSI_REQ_Q 'a_flag' definitions
*
* The Adv Library should limit use to the lower nibble (4 bits) of
* a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
*/
#define ADV_POLL_REQUEST 0x01 /* poll for request completion */
#define ADV_SCSIQ_DONE 0x02 /* request done */
#define ADV_DONT_RETRY 0x08 /* don't do retry */
#define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
#define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
#define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
/*
* Adapter temporary configuration structure
*
* This structure can be discarded after initialization. Don't add
* fields here needed after initialization.
*
* Field naming convention:
*
* *_enable indicates the field enables or disables a feature. The
* value of the field is never reset.
*/
typedef struct adv_dvc_cfg {
ushort disc_enable; /* enable disconnection */
uchar chip_version; /* chip version */
uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
ushort lib_version; /* Adv Library version number */
ushort control_flag; /* Microcode Control Flag */
ushort mcode_date; /* Microcode date */
ushort mcode_version; /* Microcode version */
ushort pci_slot_info; /* high byte device/function number */
/* bits 7-3 device num., bits 2-0 function num. */
/* low byte bus num. */
ushort serial1; /* EEPROM serial number word 1 */
ushort serial2; /* EEPROM serial number word 2 */
ushort serial3; /* EEPROM serial number word 3 */
struct device *dev; /* pointer to the pci dev structure for this board */
} ADV_DVC_CFG;
struct adv_dvc_var;
struct adv_scsi_req_q;
typedef void (* ADV_ISR_CALLBACK)
(struct adv_dvc_var *, struct adv_scsi_req_q *);
typedef void (* ADV_ASYNC_CALLBACK)
(struct adv_dvc_var *, uchar);
/*
* Adapter operation variable structure.
*
* One structure is required per host adapter.
*
* Field naming convention:
*
* *_able indicates both whether a feature should be enabled or disabled
* and whether a device isi capable of the feature. At initialization
* this field may be set, but later if a device is found to be incapable
* of the feature, the field is cleared.
*/
typedef struct adv_dvc_var {
AdvPortAddr iop_base; /* I/O port address */
ushort err_code; /* fatal error code */
ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
ADV_ISR_CALLBACK isr_callback;
ADV_ASYNC_CALLBACK async_callback;
ushort wdtr_able; /* try WDTR for a device */
ushort sdtr_able; /* try SDTR for a device */
ushort ultra_able; /* try SDTR Ultra speed for a device */
ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
ushort tagqng_able; /* try tagged queuing with a device */
ushort ppr_able; /* PPR message capable per TID bitmask. */
uchar max_dvc_qng; /* maximum number of tagged commands per device */
ushort start_motor; /* start motor command allowed */
uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
uchar chip_no; /* should be assigned by caller */
uchar max_host_qng; /* maximum number of Q'ed command allowed */
uchar irq_no; /* IRQ number */
ushort no_scam; /* scam_tolerant of EEPROM */
struct asc_board *drv_ptr; /* driver pointer to private structure */
uchar chip_scsi_id; /* chip SCSI target ID */
uchar chip_type;
uchar bist_err_code;
ADV_CARR_T *carrier_buf;
ADV_CARR_T *carr_freelist; /* Carrier free list. */
ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
ushort carr_pending_cnt; /* Count of pending carriers. */
/*
* Note: The following fields will not be used after initialization. The
* driver may discard the buffer after initialization is done.
*/
ADV_DVC_CFG *cfg; /* temporary configuration structure */
} ADV_DVC_VAR;
#define NO_OF_SG_PER_BLOCK 15
typedef struct asc_sg_block {
uchar reserved1;
uchar reserved2;
uchar reserved3;
uchar sg_cnt; /* Valid entries in block. */
ADV_PADDR sg_ptr; /* Pointer to next sg block. */
struct {
ADV_PADDR sg_addr; /* SG element address. */
ADV_DCNT sg_count; /* SG element count. */
} sg_list[NO_OF_SG_PER_BLOCK];
} ADV_SG_BLOCK;
/*
* ADV_SCSI_REQ_Q - microcode request structure
*
* All fields in this structure up to byte 60 are used by the microcode.
* The microcode makes assumptions about the size and ordering of fields
* in this structure. Do not change the structure definition here without
* coordinating the change with the microcode.
*
* All fields accessed by microcode must be maintained in little_endian
* order.
*/
typedef struct adv_scsi_req_q {
uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
uchar target_cmd;
uchar target_id; /* Device target identifier. */
uchar target_lun; /* Device target logical unit number. */
ADV_PADDR data_addr; /* Data buffer physical address. */
ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
ADV_PADDR sense_addr;
ADV_PADDR carr_pa;
uchar mflag;
uchar sense_len;
uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
uchar scsi_cntl;
uchar done_status; /* Completion status. */
uchar scsi_status; /* SCSI status byte. */
uchar host_status; /* Ucode host status. */
uchar sg_working_ix;
uchar cdb[12]; /* SCSI CDB bytes 0-11. */
ADV_PADDR sg_real_addr; /* SG list physical address. */
ADV_PADDR scsiq_rptr;
uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
ADV_VADDR scsiq_ptr;
ADV_VADDR carr_va;
/*
* End of microcode structure - 60 bytes. The rest of the structure
* is used by the Adv Library and ignored by the microcode.
*/
ADV_VADDR srb_ptr;
ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
char *vdata_addr; /* Data buffer virtual address. */
uchar a_flag;
uchar pad[2]; /* Pad out to a word boundary. */
} ADV_SCSI_REQ_Q;
/*
* Microcode idle loop commands
*/
#define IDLE_CMD_COMPLETED 0
#define IDLE_CMD_STOP_CHIP 0x0001
#define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
#define IDLE_CMD_SEND_INT 0x0004
#define IDLE_CMD_ABORT 0x0008
#define IDLE_CMD_DEVICE_RESET 0x0010
#define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
#define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
#define IDLE_CMD_SCSIREQ 0x0080
#define IDLE_CMD_STATUS_SUCCESS 0x0001
#define IDLE_CMD_STATUS_FAILURE 0x0002
/*
* AdvSendIdleCmd() flag definitions.
*/
#define ADV_NOWAIT 0x01
/*
* Wait loop time out values.
*/
#define SCSI_WAIT_10_SEC 10UL /* 10 seconds */
#define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
#define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
#define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */
#define SCSI_MAX_RETRY 10 /* retry count */
#define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
#define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
#define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
#define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
/*
* Device drivers must define the following functions.
*/
STATIC inline ulong DvcEnterCritical(void);
STATIC inline void DvcLeaveCritical(ulong);
STATIC void DvcSleepMilliSecond(ADV_DCNT);
STATIC uchar DvcAdvReadPCIConfigByte(ADV_DVC_VAR *, ushort);
STATIC void DvcAdvWritePCIConfigByte(ADV_DVC_VAR *, ushort, uchar);
STATIC ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *,
uchar *, ASC_SDCNT *, int);
STATIC void DvcDelayMicroSecond(ADV_DVC_VAR *, ushort);
/*
* Adv Library functions available to drivers.
*/
STATIC int AdvExeScsiQueue(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
STATIC int AdvISR(ADV_DVC_VAR *);
STATIC int AdvInitGetConfig(ADV_DVC_VAR *);
STATIC int AdvInitAsc3550Driver(ADV_DVC_VAR *);
STATIC int AdvInitAsc38C0800Driver(ADV_DVC_VAR *);
STATIC int AdvInitAsc38C1600Driver(ADV_DVC_VAR *);
STATIC int AdvResetChipAndSB(ADV_DVC_VAR *);
STATIC int AdvResetSB(ADV_DVC_VAR *asc_dvc);
/*
* Internal Adv Library functions.
*/
STATIC int AdvSendIdleCmd(ADV_DVC_VAR *, ushort, ADV_DCNT);
STATIC void AdvInquiryHandling(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
STATIC int AdvInitFrom3550EEP(ADV_DVC_VAR *);
STATIC int AdvInitFrom38C0800EEP(ADV_DVC_VAR *);
STATIC int AdvInitFrom38C1600EEP(ADV_DVC_VAR *);
STATIC ushort AdvGet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
STATIC void AdvSet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
STATIC ushort AdvGet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
STATIC void AdvSet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
STATIC ushort AdvGet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
STATIC void AdvSet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
STATIC void AdvWaitEEPCmd(AdvPortAddr);
STATIC ushort AdvReadEEPWord(AdvPortAddr, int);
/*
* PCI Bus Definitions
*/
#define AscPCICmdRegBits_BusMastering 0x0007
#define AscPCICmdRegBits_ParErrRespCtrl 0x0040
/* Read byte from a register. */
#define AdvReadByteRegister(iop_base, reg_off) \
(ADV_MEM_READB((iop_base) + (reg_off)))
/* Write byte to a register. */
#define AdvWriteByteRegister(iop_base, reg_off, byte) \
(ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
/* Read word (2 bytes) from a register. */
#define AdvReadWordRegister(iop_base, reg_off) \
(ADV_MEM_READW((iop_base) + (reg_off)))
/* Write word (2 bytes) to a register. */
#define AdvWriteWordRegister(iop_base, reg_off, word) \
(ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
/* Write dword (4 bytes) to a register. */
#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
(ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
/* Read byte from LRAM. */
#define AdvReadByteLram(iop_base, addr, byte) \
do { \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
(byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
} while (0)
/* Write byte to LRAM. */
#define AdvWriteByteLram(iop_base, addr, byte) \
(ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
/* Read word (2 bytes) from LRAM. */
#define AdvReadWordLram(iop_base, addr, word) \
do { \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
(word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
} while (0)
/* Write word (2 bytes) to LRAM. */
#define AdvWriteWordLram(iop_base, addr, word) \
(ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
/* Write little-endian double word (4 bytes) to LRAM */
/* Because of unspecified C language ordering don't use auto-increment. */
#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
(ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
/* Read word (2 bytes) from LRAM assuming that the address is already set. */
#define AdvReadWordAutoIncLram(iop_base) \
(ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
/* Write word (2 bytes) to LRAM assuming that the address is already set. */
#define AdvWriteWordAutoIncLram(iop_base, word) \
(ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
/*
* Define macro to check for Condor signature.
*
* Evaluate to ADV_TRUE if a Condor chip is found the specified port
* address 'iop_base'. Otherwise evalue to ADV_FALSE.
*/
#define AdvFindSignature(iop_base) \
(((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
ADV_CHIP_ID_BYTE) && \
(AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
/*
* Define macro to Return the version number of the chip at 'iop_base'.
*
* The second parameter 'bus_type' is currently unused.
*/
#define AdvGetChipVersion(iop_base, bus_type) \
AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
/*
* Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
* match the ASC_SCSI_REQ_Q 'srb_ptr' field.
*
* If the request has not yet been sent to the device it will simply be
* aborted from RISC memory. If the request is disconnected it will be
* aborted on reselection by sending an Abort Message to the target ID.
*
* Return value:
* ADV_TRUE(1) - Queue was successfully aborted.
* ADV_FALSE(0) - Queue was not found on the active queue list.
*/
#define AdvAbortQueue(asc_dvc, scsiq) \
AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
(ADV_DCNT) (scsiq))
/*
* Send a Bus Device Reset Message to the specified target ID.
*
* All outstanding commands will be purged if sending the
* Bus Device Reset Message is successful.
*
* Return Value:
* ADV_TRUE(1) - All requests on the target are purged.
* ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
* are not purged.
*/
#define AdvResetDevice(asc_dvc, target_id) \
AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
(ADV_DCNT) (target_id))
/*
* SCSI Wide Type definition.
*/
#define ADV_SCSI_BIT_ID_TYPE ushort
/*
* AdvInitScsiTarget() 'cntl_flag' options.
*/
#define ADV_SCAN_LUN 0x01
#define ADV_CAPINFO_NOLUN 0x02
/*
* Convert target id to target id bit mask.
*/
#define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
/*
* ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
*/
#define QD_NO_STATUS 0x00 /* Request not completed yet. */
#define QD_NO_ERROR 0x01
#define QD_ABORTED_BY_HOST 0x02
#define QD_WITH_ERROR 0x04
#define QHSTA_NO_ERROR 0x00
#define QHSTA_M_SEL_TIMEOUT 0x11
#define QHSTA_M_DATA_OVER_RUN 0x12
#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
#define QHSTA_M_QUEUE_ABORTED 0x15
#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
#define QHSTA_M_WTM_TIMEOUT 0x41
#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */