| /* |
| * T4240 Silicon/SoC Device Tree Source (post include) |
| * |
| * Copyright 2012 Freescale Semiconductor Inc. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * * Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * * Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * * Neither the name of Freescale Semiconductor nor the |
| * names of its contributors may be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * |
| * ALTERNATIVELY, this software may be distributed under the terms of the |
| * GNU General Public License ("GPL") as published by the Free Software |
| * Foundation, either version 2 of that License or (at your option) any |
| * later version. |
| * |
| * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
| * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
| * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| &ifc { |
| #address-cells = <2>; |
| #size-cells = <1>; |
| compatible = "fsl,ifc", "simple-bus"; |
| interrupts = <25 2 0 0>; |
| }; |
| |
| /* controller at 0x240000 */ |
| &pci0 { |
| compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; |
| device_type = "pci"; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| bus-range = <0x0 0xff>; |
| interrupts = <20 2 0 0>; |
| pcie@0 { |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| reg = <0 0 0 0 0>; |
| interrupts = <20 2 0 0>; |
| interrupt-map-mask = <0xf800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x0 */ |
| 0000 0 0 1 &mpic 40 1 0 0 |
| 0000 0 0 2 &mpic 1 1 0 0 |
| 0000 0 0 3 &mpic 2 1 0 0 |
| 0000 0 0 4 &mpic 3 1 0 0 |
| >; |
| }; |
| }; |
| |
| /* controller at 0x250000 */ |
| &pci1 { |
| compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; |
| device_type = "pci"; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| bus-range = <0 0xff>; |
| interrupts = <21 2 0 0>; |
| pcie@0 { |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| reg = <0 0 0 0 0>; |
| interrupts = <21 2 0 0>; |
| interrupt-map-mask = <0xf800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x0 */ |
| 0000 0 0 1 &mpic 41 1 0 0 |
| 0000 0 0 2 &mpic 5 1 0 0 |
| 0000 0 0 3 &mpic 6 1 0 0 |
| 0000 0 0 4 &mpic 7 1 0 0 |
| >; |
| }; |
| }; |
| |
| /* controller at 0x260000 */ |
| &pci2 { |
| compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; |
| device_type = "pci"; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| bus-range = <0x0 0xff>; |
| interrupts = <22 2 0 0>; |
| pcie@0 { |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| reg = <0 0 0 0 0>; |
| interrupts = <22 2 0 0>; |
| interrupt-map-mask = <0xf800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x0 */ |
| 0000 0 0 1 &mpic 42 1 0 0 |
| 0000 0 0 2 &mpic 9 1 0 0 |
| 0000 0 0 3 &mpic 10 1 0 0 |
| 0000 0 0 4 &mpic 11 1 0 0 |
| >; |
| }; |
| }; |
| |
| /* controller at 0x270000 */ |
| &pci3 { |
| compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; |
| device_type = "pci"; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| bus-range = <0x0 0xff>; |
| interrupts = <23 2 0 0>; |
| pcie@0 { |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| reg = <0 0 0 0 0>; |
| interrupts = <23 2 0 0>; |
| interrupt-map-mask = <0xf800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x0 */ |
| 0000 0 0 1 &mpic 43 1 0 0 |
| 0000 0 0 2 &mpic 0 1 0 0 |
| 0000 0 0 3 &mpic 4 1 0 0 |
| 0000 0 0 4 &mpic 8 1 0 0 |
| >; |
| }; |
| }; |
| |
| &rio { |
| compatible = "fsl,srio"; |
| interrupts = <16 2 1 11>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| port1 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| cell-index = <1>; |
| }; |
| |
| port2 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| cell-index = <2>; |
| }; |
| }; |
| |
| &dcsr { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,dcsr", "simple-bus"; |
| |
| dcsr-epu@0 { |
| compatible = "fsl,t4240-dcsr-epu", "fsl,dcsr-epu"; |
| interrupts = <52 2 0 0 |
| 84 2 0 0 |
| 85 2 0 0 |
| 94 2 0 0 |
| 95 2 0 0>; |
| reg = <0x0 0x1000>; |
| }; |
| dcsr-npc { |
| compatible = "fsl,t4240-dcsr-cnpc", "fsl,dcsr-cnpc"; |
| reg = <0x1000 0x1000 0x1002000 0x10000>; |
| }; |
| dcsr-nxc@2000 { |
| compatible = "fsl,dcsr-nxc"; |
| reg = <0x2000 0x1000>; |
| }; |
| dcsr-corenet { |
| compatible = "fsl,dcsr-corenet"; |
| reg = <0x8000 0x1000 0x1A000 0x1000>; |
| }; |
| dcsr-dpaa@9000 { |
| compatible = "fsl,t4240-dcsr-dpaa", "fsl,dcsr-dpaa"; |
| reg = <0x9000 0x1000>; |
| }; |
| dcsr-ocn@11000 { |
| compatible = "fsl,t4240-dcsr-ocn", "fsl,dcsr-ocn"; |
| reg = <0x11000 0x1000>; |
| }; |
| dcsr-ddr@12000 { |
| compatible = "fsl,dcsr-ddr"; |
| dev-handle = <&ddr1>; |
| reg = <0x12000 0x1000>; |
| }; |
| dcsr-ddr@13000 { |
| compatible = "fsl,dcsr-ddr"; |
| dev-handle = <&ddr2>; |
| reg = <0x13000 0x1000>; |
| }; |
| dcsr-ddr@14000 { |
| compatible = "fsl,dcsr-ddr"; |
| dev-handle = <&ddr3>; |
| reg = <0x14000 0x1000>; |
| }; |
| dcsr-nal@18000 { |
| compatible = "fsl,t4240-dcsr-nal", "fsl,dcsr-nal"; |
| reg = <0x18000 0x1000>; |
| }; |
| dcsr-rcpm@22000 { |
| compatible = "fsl,t4240-dcsr-rcpm", "fsl,dcsr-rcpm"; |
| reg = <0x22000 0x1000>; |
| }; |
| dcsr-snpc@30000 { |
| compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; |
| reg = <0x30000 0x1000 0x1022000 0x10000>; |
| }; |
| dcsr-snpc@31000 { |
| compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; |
| reg = <0x31000 0x1000 0x1042000 0x10000>; |
| }; |
| dcsr-snpc@32000 { |
| compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; |
| reg = <0x32000 0x1000 0x1062000 0x10000>; |
| }; |
| dcsr-cpu-sb-proxy@100000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu0>; |
| reg = <0x100000 0x1000 0x101000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@108000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu1>; |
| reg = <0x108000 0x1000 0x109000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@110000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu2>; |
| reg = <0x110000 0x1000 0x111000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@118000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu3>; |
| reg = <0x118000 0x1000 0x119000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@120000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu4>; |
| reg = <0x120000 0x1000 0x121000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@128000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu5>; |
| reg = <0x128000 0x1000 0x129000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@130000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu6>; |
| reg = <0x130000 0x1000 0x131000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@138000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu7>; |
| reg = <0x138000 0x1000 0x139000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@140000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu8>; |
| reg = <0x140000 0x1000 0x141000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@148000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu9>; |
| reg = <0x148000 0x1000 0x149000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@150000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu10>; |
| reg = <0x150000 0x1000 0x151000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@158000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu11>; |
| reg = <0x158000 0x1000 0x159000 0x1000>; |
| }; |
| }; |
| |
| &soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| compatible = "simple-bus"; |
| |
| soc-sram-error { |
| compatible = "fsl,soc-sram-error"; |
| interrupts = <16 2 1 29>; |
| }; |
| |
| corenet-law@0 { |
| compatible = "fsl,corenet-law"; |
| reg = <0x0 0x1000>; |
| fsl,num-laws = <32>; |
| }; |
| |
| ddr1: memory-controller@8000 { |
| compatible = "fsl,qoriq-memory-controller-v4.7", |
| "fsl,qoriq-memory-controller"; |
| reg = <0x8000 0x1000>; |
| interrupts = <16 2 1 23>; |
| }; |
| |
| ddr2: memory-controller@9000 { |
| compatible = "fsl,qoriq-memory-controller-v4.7", |
| "fsl,qoriq-memory-controller"; |
| reg = <0x9000 0x1000>; |
| interrupts = <16 2 1 22>; |
| }; |
| |
| ddr3: memory-controller@a000 { |
| compatible = "fsl,qoriq-memory-controller-v4.7", |
| "fsl,qoriq-memory-controller"; |
| reg = <0xa000 0x1000>; |
| interrupts = <16 2 1 21>; |
| }; |
| |
| cpc: l3-cache-controller@10000 { |
| compatible = "fsl,t4240-l3-cache-controller", "cache"; |
| reg = <0x10000 0x1000 |
| 0x11000 0x1000 |
| 0x12000 0x1000>; |
| interrupts = <16 2 1 27 |
| 16 2 1 26 |
| 16 2 1 25>; |
| }; |
| |
| corenet-cf@18000 { |
| compatible = "fsl,corenet-cf"; |
| reg = <0x18000 0x1000>; |
| interrupts = <16 2 1 31>; |
| fsl,ccf-num-csdids = <32>; |
| fsl,ccf-num-snoopids = <32>; |
| }; |
| |
| iommu@20000 { |
| compatible = "fsl,pamu-v1.0", "fsl,pamu"; |
| reg = <0x20000 0x6000>; |
| interrupts = < |
| 24 2 0 0 |
| 16 2 1 30>; |
| }; |
| |
| /include/ "qoriq-mpic4.3.dtsi" |
| |
| guts: global-utilities@e0000 { |
| compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0"; |
| reg = <0xe0000 0xe00>; |
| fsl,has-rstcr; |
| fsl,liodn-bits = <12>; |
| }; |
| |
| clockgen: global-utilities@e1000 { |
| compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; |
| reg = <0xe1000 0x1000>; |
| }; |
| |
| rcpm: global-utilities@e2000 { |
| compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; |
| reg = <0xe2000 0x1000>; |
| }; |
| |
| sfp: sfp@e8000 { |
| compatible = "fsl,t4240-sfp"; |
| reg = <0xe8000 0x1000>; |
| }; |
| |
| serdes: serdes@ea000 { |
| compatible = "fsl,t4240-serdes"; |
| reg = <0xea000 0x4000>; |
| }; |
| |
| /include/ "elo3-dma-0.dtsi" |
| /include/ "elo3-dma-1.dtsi" |
| |
| /include/ "qoriq-espi-0.dtsi" |
| spi@110000 { |
| fsl,espi-num-chipselects = <4>; |
| }; |
| |
| /include/ "qoriq-esdhc-0.dtsi" |
| sdhc@114000 { |
| compatible = "fsl,t4240-esdhc", "fsl,esdhc"; |
| sdhci,auto-cmd12; |
| }; |
| /include/ "qoriq-i2c-0.dtsi" |
| /include/ "qoriq-i2c-1.dtsi" |
| /include/ "qoriq-duart-0.dtsi" |
| /include/ "qoriq-duart-1.dtsi" |
| /include/ "qoriq-gpio-0.dtsi" |
| /include/ "qoriq-gpio-1.dtsi" |
| /include/ "qoriq-gpio-2.dtsi" |
| /include/ "qoriq-gpio-3.dtsi" |
| /include/ "qoriq-usb2-mph-0.dtsi" |
| usb0: usb@210000 { |
| compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph"; |
| phy_type = "utmi"; |
| port0; |
| }; |
| /include/ "qoriq-usb2-dr-0.dtsi" |
| usb1: usb@211000 { |
| compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; |
| dr_mode = "host"; |
| phy_type = "utmi"; |
| }; |
| /include/ "qoriq-sata2-0.dtsi" |
| /include/ "qoriq-sata2-1.dtsi" |
| /include/ "qoriq-sec5.0-0.dtsi" |
| |
| L2_1: l2-cache-controller@c20000 { |
| compatible = "fsl,t4240-l2-cache-controller"; |
| reg = <0xc20000 0x40000>; |
| next-level-cache = <&cpc>; |
| }; |
| L2_2: l2-cache-controller@c60000 { |
| compatible = "fsl,t4240-l2-cache-controller"; |
| reg = <0xc60000 0x40000>; |
| next-level-cache = <&cpc>; |
| }; |
| L2_3: l2-cache-controller@ca0000 { |
| compatible = "fsl,t4240-l2-cache-controller"; |
| reg = <0xca0000 0x40000>; |
| next-level-cache = <&cpc>; |
| }; |
| }; |
