| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| // Copyright (C) 2016 ARM Ltd. |
| |
| #include <arm/sunxi-h3-h5.dtsi> |
| |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <0>; |
| enable-method = "psci"; |
| clocks = <&ccu CLK_CPUX>; |
| clock-latency-ns = <244144>; /* 8 32k periods */ |
| #cooling-cells = <2>; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <1>; |
| enable-method = "psci"; |
| clocks = <&ccu CLK_CPUX>; |
| clock-latency-ns = <244144>; /* 8 32k periods */ |
| #cooling-cells = <2>; |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <2>; |
| enable-method = "psci"; |
| clocks = <&ccu CLK_CPUX>; |
| clock-latency-ns = <244144>; /* 8 32k periods */ |
| #cooling-cells = <2>; |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <3>; |
| enable-method = "psci"; |
| clocks = <&ccu CLK_CPUX>; |
| clock-latency-ns = <244144>; /* 8 32k periods */ |
| #cooling-cells = <2>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| arm,no-tick-in-suspend; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| soc { |
| syscon: system-control@1c00000 { |
| compatible = "allwinner,sun50i-h5-system-control"; |
| reg = <0x01c00000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| sram_c1: sram@18000 { |
| compatible = "mmio-sram"; |
| reg = <0x00018000 0x1c000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x00018000 0x1c000>; |
| |
| ve_sram: sram-section@0 { |
| compatible = "allwinner,sun50i-h5-sram-c1", |
| "allwinner,sun4i-a10-sram-c1"; |
| reg = <0x000000 0x1c000>; |
| }; |
| }; |
| }; |
| |
| video-codec@1c0e000 { |
| compatible = "allwinner,sun50i-h5-video-engine"; |
| reg = <0x01c0e000 0x1000>; |
| clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, |
| <&ccu CLK_DRAM_VE>; |
| clock-names = "ahb", "mod", "ram"; |
| resets = <&ccu RST_BUS_VE>; |
| interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; |
| allwinner,sram = <&ve_sram 1>; |
| }; |
| |
| crypto: crypto@1c15000 { |
| compatible = "allwinner,sun50i-h5-crypto"; |
| reg = <0x01c15000 0x1000>; |
| interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; |
| clock-names = "bus", "mod"; |
| resets = <&ccu RST_BUS_CE>; |
| }; |
| |
| deinterlace: deinterlace@1e00000 { |
| compatible = "allwinner,sun8i-h3-deinterlace"; |
| reg = <0x01e00000 0x20000>; |
| clocks = <&ccu CLK_BUS_DEINTERLACE>, |
| <&ccu CLK_DEINTERLACE>, |
| <&ccu CLK_DRAM_DEINTERLACE>; |
| clock-names = "bus", "mod", "ram"; |
| resets = <&ccu RST_BUS_DEINTERLACE>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| interconnects = <&mbus 9>; |
| interconnect-names = "dma-mem"; |
| }; |
| |
| mali: gpu@1e80000 { |
| compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; |
| reg = <0x01e80000 0x30000>; |
| /* |
| * While the datasheet lists an interrupt for the |
| * PMU, the actual silicon does not have the PMU |
| * block. Reads all return zero, and writes are |
| * ignored. |
| */ |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "gp", |
| "gpmmu", |
| "pp", |
| "pp0", |
| "ppmmu0", |
| "pp1", |
| "ppmmu1", |
| "pp2", |
| "ppmmu2", |
| "pp3", |
| "ppmmu3"; |
| clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; |
| clock-names = "bus", "core"; |
| resets = <&ccu RST_BUS_GPU>; |
| |
| assigned-clocks = <&ccu CLK_GPU>; |
| assigned-clock-rates = <384000000>; |
| }; |
| |
| ths: thermal-sensor@1c25000 { |
| compatible = "allwinner,sun50i-h5-ths"; |
| reg = <0x01c25000 0x400>; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&ccu RST_BUS_THS>; |
| clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; |
| clock-names = "bus", "mod"; |
| nvmem-cells = <&ths_calibration>; |
| nvmem-cell-names = "calibration"; |
| #thermal-sensor-cells = <1>; |
| }; |
| }; |
| |
| thermal-zones { |
| cpu_thermal: cpu-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&ths 0>; |
| |
| trips { |
| cpu_hot_trip: cpu-hot { |
| temperature = <80000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu_very_hot_trip: cpu-very-hot { |
| temperature = <100000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| cpu-hot-limit { |
| trip = <&cpu_hot_trip>; |
| cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| gpu_thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&ths 1>; |
| }; |
| }; |
| }; |
| |
| &ccu { |
| compatible = "allwinner,sun50i-h5-ccu"; |
| }; |
| |
| &display_clocks { |
| compatible = "allwinner,sun50i-h5-de2-clk"; |
| }; |
| |
| &mmc0 { |
| compatible = "allwinner,sun50i-h5-mmc", |
| "allwinner,sun50i-a64-mmc"; |
| clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; |
| clock-names = "ahb", "mmc"; |
| }; |
| |
| &mmc1 { |
| compatible = "allwinner,sun50i-h5-mmc", |
| "allwinner,sun50i-a64-mmc"; |
| clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; |
| clock-names = "ahb", "mmc"; |
| }; |
| |
| &mmc2 { |
| compatible = "allwinner,sun50i-h5-emmc", |
| "allwinner,sun50i-a64-emmc"; |
| clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; |
| clock-names = "ahb", "mmc"; |
| }; |
| |
| &pio { |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| compatible = "allwinner,sun50i-h5-pinctrl"; |
| }; |
| |
| &rtc { |
| compatible = "allwinner,sun50i-h5-rtc"; |
| }; |
| |
| &sid { |
| compatible = "allwinner,sun50i-h5-sid"; |
| }; |
