| // SPDX-License-Identifier: GPL-2.0 OR X11 |
| /* |
| * Device Tree Include file for TQ-Systems TQMa7x boards with full mounted PCB. |
| * |
| * Copyright (C) 2016 TQ-Systems GmbH |
| * Author: Markus Niebel <Markus.Niebel@tq-group.com> |
| * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com> |
| */ |
| |
| / { |
| memory@80000000 { |
| device_type = "memory"; |
| /* 512 MB - default configuration */ |
| reg = <0x80000000 0x20000000>; |
| }; |
| }; |
| |
| &cpu0 { |
| cpu-supply = <&sw1a_reg>; |
| }; |
| |
| &gpio2 { |
| /* Configured as pullup by QSPI pin group */ |
| qspi-reset-hog { |
| gpio-hog; |
| gpios = <4 GPIO_ACTIVE_LOW>; |
| input; |
| line-name = "qspi-reset"; |
| }; |
| }; |
| |
| &i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| clock-frequency = <100000>; |
| status = "okay"; |
| |
| pfuze3000: pmic@8 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pmic1>; |
| compatible = "fsl,pfuze3000"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1a { |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| /* use sw1c_reg to align with pfuze100/pfuze200 */ |
| sw1c_reg: sw1b { |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1475000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <1500000>; |
| regulator-max-microvolt = <1850000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3 { |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1650000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vgen1_reg: vldo1 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen2_reg: vldo2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| regulator-always-on; |
| }; |
| |
| vgen3_reg: vccsd { |
| regulator-min-microvolt = <2850000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen4_reg: v33 { |
| regulator-min-microvolt = <2850000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vldo3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen6_reg: vldo4 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| /* NXP SE97BTP with temperature sensor + eeprom */ |
| se97b: temperature-sensor-eeprom@1e { |
| compatible = "nxp,se97b", "jedec,jc-42.4-temp"; |
| reg = <0x1e>; |
| status = "okay"; |
| }; |
| |
| /* ST M24C64 */ |
| m24c64: eeprom@50 { |
| compatible = "atmel,24c64"; |
| reg = <0x50>; |
| pagesize = <32>; |
| status = "okay"; |
| }; |
| |
| at24c02: eeprom@56 { |
| compatible = "atmel,24c02"; |
| reg = <0x56>; |
| pagesize = <16>; |
| status = "okay"; |
| }; |
| |
| ds1339: rtc@68 { |
| compatible = "dallas,ds1339"; |
| reg = <0x68>; |
| }; |
| }; |
| |
| &iomuxc { |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078 |
| MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078 |
| >; |
| }; |
| |
| pinctrl_pmic1: pmic1grp { |
| fsl,pins = < |
| MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C |
| >; |
| }; |
| |
| pinctrl_qspi: qspigrp { |
| fsl,pins = < |
| MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A |
| MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A |
| MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A |
| MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A |
| MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11 |
| MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54 |
| MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54 |
| >; |
| }; |
| |
| pinctrl_qspi_reset: qspi_resetgrp { |
| fsl,pins = < |
| /* #QSPI_RESET */ |
| MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x59 |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x56 |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x5a |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x51 |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x5b |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x51 |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b |
| >; |
| }; |
| }; |
| |
| &iomuxc_lpsr { |
| pinctrl_wdog1: wdog1grp { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 |
| >; |
| }; |
| }; |
| |
| &qspi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>; |
| status = "okay"; |
| |
| flash0: flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <29000000>; |
| spi-rx-bus-width = <4>; |
| spi-tx-bus-width = <4>; |
| }; |
| }; |
| |
| &sdma { |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; |
| assigned-clock-rates = <400000000>; |
| bus-width = <8>; |
| non-removable; |
| vmmc-supply = <&vgen4_reg>; |
| vqmmc-supply = <&sw2_reg>; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog1>; |
| /* |
| * Errata e10574: |
| * WDOG reset needs to run with WDOG_RESET_B signal enabled. |
| * X1-51 (WDOG1#) signal needs carrier board handling to reset |
| * TQMa7 on X1-22 (RESET_IN#). |
| */ |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
