blob: 0bbd4ae1f52466923e9103db8a5b40c7cb822f58 [file] [log] [blame]
/*
Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Trident Microsystems nor Hauppauge Computer Works
nor the names of its contributors may be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/*
***********************************************************************************************************************
* WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE
*
* Filename: drxj_map.h
* Generated on: Mon Jan 18 12:09:24 2010
* Generated by: IDF:x 1.3.0
* Generated from: reg_map
* Output start: [entry point]
*
* filename last modified re-use
* -----------------------------------------------------
* reg_map.1.tmp Mon Jan 18 12:09:24 2010 -
*
*/
#ifndef __DRXJ_MAP__H__
#define __DRXJ_MAP__H__ INCLUDED
#ifdef _REGISTERTABLE_
#include <registertable.h>
extern register_table_t drxj_map[];
extern register_table_info_t drxj_map_info[];
#endif
#define ATV_COMM_EXEC__A 0xC00000
#define ATV_COMM_EXEC__W 2
#define ATV_COMM_EXEC__M 0x3
#define ATV_COMM_EXEC__PRE 0x0
#define ATV_COMM_EXEC_STOP 0x0
#define ATV_COMM_EXEC_ACTIVE 0x1
#define ATV_COMM_EXEC_HOLD 0x2
#define ATV_COMM_STATE__A 0xC00001
#define ATV_COMM_STATE__W 16
#define ATV_COMM_STATE__M 0xFFFF
#define ATV_COMM_STATE__PRE 0x0
#define ATV_COMM_MB__A 0xC00002
#define ATV_COMM_MB__W 16
#define ATV_COMM_MB__M 0xFFFF
#define ATV_COMM_MB__PRE 0x0
#define ATV_COMM_INT_REQ__A 0xC00003
#define ATV_COMM_INT_REQ__W 16
#define ATV_COMM_INT_REQ__M 0xFFFF
#define ATV_COMM_INT_REQ__PRE 0x0
#define ATV_COMM_INT_REQ_COMM_INT_REQ__B 0
#define ATV_COMM_INT_REQ_COMM_INT_REQ__W 1
#define ATV_COMM_INT_REQ_COMM_INT_REQ__M 0x1
#define ATV_COMM_INT_REQ_COMM_INT_REQ__PRE 0x0
#define ATV_COMM_INT_STA__A 0xC00005
#define ATV_COMM_INT_STA__W 16
#define ATV_COMM_INT_STA__M 0xFFFF
#define ATV_COMM_INT_STA__PRE 0x0
#define ATV_COMM_INT_MSK__A 0xC00006
#define ATV_COMM_INT_MSK__W 16
#define ATV_COMM_INT_MSK__M 0xFFFF
#define ATV_COMM_INT_MSK__PRE 0x0
#define ATV_COMM_INT_STM__A 0xC00007
#define ATV_COMM_INT_STM__W 16
#define ATV_COMM_INT_STM__M 0xFFFF
#define ATV_COMM_INT_STM__PRE 0x0
#define ATV_COMM_KEY__A 0xC0000F
#define ATV_COMM_KEY__W 16
#define ATV_COMM_KEY__M 0xFFFF
#define ATV_COMM_KEY__PRE 0x0
#define ATV_COMM_KEY_KEY 0xFABA
#define ATV_COMM_KEY_MIN 0x0
#define ATV_COMM_KEY_MAX 0xFFFF
#define ATV_TOP_COMM_EXEC__A 0xC10000
#define ATV_TOP_COMM_EXEC__W 2
#define ATV_TOP_COMM_EXEC__M 0x3
#define ATV_TOP_COMM_EXEC__PRE 0x0
#define ATV_TOP_COMM_EXEC_STOP 0x0
#define ATV_TOP_COMM_EXEC_ACTIVE 0x1
#define ATV_TOP_COMM_EXEC_HOLD 0x2
#define ATV_TOP_COMM_STATE__A 0xC10001
#define ATV_TOP_COMM_STATE__W 16
#define ATV_TOP_COMM_STATE__M 0xFFFF
#define ATV_TOP_COMM_STATE__PRE 0x0
#define ATV_TOP_COMM_STATE_STATE__B 0
#define ATV_TOP_COMM_STATE_STATE__W 16
#define ATV_TOP_COMM_STATE_STATE__M 0xFFFF
#define ATV_TOP_COMM_STATE_STATE__PRE 0x0
#define ATV_TOP_COMM_MB__A 0xC10002
#define ATV_TOP_COMM_MB__W 16
#define ATV_TOP_COMM_MB__M 0xFFFF
#define ATV_TOP_COMM_MB__PRE 0x0
#define ATV_TOP_COMM_MB_CTL__B 0
#define ATV_TOP_COMM_MB_CTL__W 1
#define ATV_TOP_COMM_MB_CTL__M 0x1
#define ATV_TOP_COMM_MB_CTL__PRE 0x0
#define ATV_TOP_COMM_MB_OBS__B 1
#define ATV_TOP_COMM_MB_OBS__W 1
#define ATV_TOP_COMM_MB_OBS__M 0x2
#define ATV_TOP_COMM_MB_OBS__PRE 0x0
#define ATV_TOP_COMM_MB_MUX_CTRL__B 2
#define ATV_TOP_COMM_MB_MUX_CTRL__W 4
#define ATV_TOP_COMM_MB_MUX_CTRL__M 0x3C
#define ATV_TOP_COMM_MB_MUX_CTRL__PRE 0x0
#define ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S 0x0
#define ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN 0x4
#define ATV_TOP_COMM_MB_MUX_CTRL_CORR_O 0x8
#define ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O 0xC
#define ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ 0x10
#define ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O 0x14
#define ATV_TOP_COMM_MB_MUX_CTRL_SIF_O 0x18
#define ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O 0x1C
#define ATV_TOP_COMM_MB_MUX_CTRL_POST_S 0x20
#define ATV_TOP_COMM_MB_MUX_OBS__B 6
#define ATV_TOP_COMM_MB_MUX_OBS__W 4
#define ATV_TOP_COMM_MB_MUX_OBS__M 0x3C0
#define ATV_TOP_COMM_MB_MUX_OBS__PRE 0x0
#define ATV_TOP_COMM_MB_MUX_OBS_PEAK_S 0x0
#define ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN 0x40
#define ATV_TOP_COMM_MB_MUX_OBS_CORR_O 0x80
#define ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O 0xC0
#define ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ 0x100
#define ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O 0x140
#define ATV_TOP_COMM_MB_MUX_OBS_SIF_O 0x180
#define ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O 0x1C0
#define ATV_TOP_COMM_MB_MUX_OBS_POST_S 0x200
#define ATV_TOP_COMM_INT_REQ__A 0xC10003
#define ATV_TOP_COMM_INT_REQ__W 16
#define ATV_TOP_COMM_INT_REQ__M 0xFFFF
#define ATV_TOP_COMM_INT_REQ__PRE 0x0
#define ATV_TOP_COMM_INT_STA__A 0xC10005
#define ATV_TOP_COMM_INT_STA__W 16
#define ATV_TOP_COMM_INT_STA__M 0xFFFF
#define ATV_TOP_COMM_INT_STA__PRE 0x0
#define ATV_TOP_COMM_INT_STA_FAGC_STA__B 0
#define ATV_TOP_COMM_INT_STA_FAGC_STA__W 1
#define ATV_TOP_COMM_INT_STA_FAGC_STA__M 0x1
#define ATV_TOP_COMM_INT_STA_FAGC_STA__PRE 0x0
#define ATV_TOP_COMM_INT_STA_OVM_STA__B 1
#define ATV_TOP_COMM_INT_STA_OVM_STA__W 1
#define ATV_TOP_COMM_INT_STA_OVM_STA__M 0x2
#define ATV_TOP_COMM_INT_STA_OVM_STA__PRE 0x0
#define ATV_TOP_COMM_INT_STA_AMPTH_STA__B 2
#define ATV_TOP_COMM_INT_STA_AMPTH_STA__W 1
#define ATV_TOP_COMM_INT_STA_AMPTH_STA__M 0x4
#define ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE 0x0
#define ATV_TOP_COMM_INT_MSK__A 0xC10006
#define ATV_TOP_COMM_INT_MSK__W 16
#define ATV_TOP_COMM_INT_MSK__M 0xFFFF
#define ATV_TOP_COMM_INT_MSK__PRE 0x0
#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__B 0
#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__W 1
#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__M 0x1
#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE 0x0
#define ATV_TOP_COMM_INT_MSK_OVM_MSK__B 1
#define ATV_TOP_COMM_INT_MSK_OVM_MSK__W 1
#define ATV_TOP_COMM_INT_MSK_OVM_MSK__M 0x2
#define ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE 0x0
#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B 2
#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W 1
#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M 0x4
#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE 0x0
#define ATV_TOP_COMM_INT_STM__A 0xC10007
#define ATV_TOP_COMM_INT_STM__W 16
#define ATV_TOP_COMM_INT_STM__M 0xFFFF
#define ATV_TOP_COMM_INT_STM__PRE 0x0
#define ATV_TOP_COMM_INT_STM_FAGC_STM__B 0
#define ATV_TOP_COMM_INT_STM_FAGC_STM__W 1
#define ATV_TOP_COMM_INT_STM_FAGC_STM__M 0x1
#define ATV_TOP_COMM_INT_STM_FAGC_STM__PRE 0x0
#define ATV_TOP_COMM_INT_STM_OVM_STM__B 1
#define ATV_TOP_COMM_INT_STM_OVM_STM__W 1
#define ATV_TOP_COMM_INT_STM_OVM_STM__M 0x2
#define ATV_TOP_COMM_INT_STM_OVM_STM__PRE 0x0
#define ATV_TOP_COMM_INT_STM_AMPTH_STM__B 2
#define ATV_TOP_COMM_INT_STM_AMPTH_STM__W 1
#define ATV_TOP_COMM_INT_STM_AMPTH_STM__M 0x4
#define ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE 0x0
#define ATV_TOP_COMM_KEY__A 0xC1000F
#define ATV_TOP_COMM_KEY__W 16
#define ATV_TOP_COMM_KEY__M 0xFFFF
#define ATV_TOP_COMM_KEY__PRE 0x0
#define ATV_TOP_COMM_KEY_KEY__B 0
#define ATV_TOP_COMM_KEY_KEY__W 16
#define ATV_TOP_COMM_KEY_KEY__M 0xFFFF
#define ATV_TOP_COMM_KEY_KEY__PRE 0x0
#define ATV_TOP_COMM_KEY_KEY_KEY 0xFABA
#define ATV_TOP_COMM_KEY_KEY_MIN 0x0
#define ATV_TOP_COMM_KEY_KEY_MAX 0xFFFF
#define ATV_TOP_CR_AMP_TH__A 0xC10010
#define ATV_TOP_CR_AMP_TH__W 8
#define ATV_TOP_CR_AMP_TH__M 0xFF
#define ATV_TOP_CR_AMP_TH__PRE 0x8
#define ATV_TOP_CR_AMP_TH_MN 0x8
#define ATV_TOP_CR_CONT__A 0xC10011
#define ATV_TOP_CR_CONT__W 9
#define ATV_TOP_CR_CONT__M 0x1FF
#define ATV_TOP_CR_CONT__PRE 0x9C
#define ATV_TOP_CR_CONT_CR_P__B 0
#define ATV_TOP_CR_CONT_CR_P__W 3
#define ATV_TOP_CR_CONT_CR_P__M 0x7
#define ATV_TOP_CR_CONT_CR_P__PRE 0x4
#define ATV_TOP_CR_CONT_CR_P_MN 0x4
#define ATV_TOP_CR_CONT_CR_P_FM 0x0
#define ATV_TOP_CR_CONT_CR_D__B 3
#define ATV_TOP_CR_CONT_CR_D__W 3
#define ATV_TOP_CR_CONT_CR_D__M 0x38
#define ATV_TOP_CR_CONT_CR_D__PRE 0x18
#define ATV_TOP_CR_CONT_CR_D_MN 0x18
#define ATV_TOP_CR_CONT_CR_D_FM 0x0
#define ATV_TOP_CR_CONT_CR_I__B 6
#define ATV_TOP_CR_CONT_CR_I__W 3
#define ATV_TOP_CR_CONT_CR_I__M 0x1C0
#define ATV_TOP_CR_CONT_CR_I__PRE 0x80
#define ATV_TOP_CR_CONT_CR_I_MN 0x80
#define ATV_TOP_CR_CONT_CR_I_FM 0x0
#define ATV_TOP_CR_OVM_TH__A 0xC10012
#define ATV_TOP_CR_OVM_TH__W 8
#define ATV_TOP_CR_OVM_TH__M 0xFF
#define ATV_TOP_CR_OVM_TH__PRE 0xA0
#define ATV_TOP_CR_OVM_TH_MN 0xA0
#define ATV_TOP_CR_OVM_TH_FM 0x0
#define ATV_TOP_NOISE_TH__A 0xC10013
#define ATV_TOP_NOISE_TH__W 4
#define ATV_TOP_NOISE_TH__M 0xF
#define ATV_TOP_NOISE_TH__PRE 0x8
#define ATV_TOP_NOISE_TH_MN 0x8
#define ATV_TOP_EQU0__A 0xC10014
#define ATV_TOP_EQU0__W 9
#define ATV_TOP_EQU0__M 0x1FF
#define ATV_TOP_EQU0__PRE 0x1FB
#define ATV_TOP_EQU0_EQU_C0__B 0
#define ATV_TOP_EQU0_EQU_C0__W 9
#define ATV_TOP_EQU0_EQU_C0__M 0x1FF
#define ATV_TOP_EQU0_EQU_C0__PRE 0x1FB
#define ATV_TOP_EQU0_EQU_C0_MN 0xFB
#define ATV_TOP_EQU1__A 0xC10015
#define ATV_TOP_EQU1__W 9
#define ATV_TOP_EQU1__M 0x1FF
#define ATV_TOP_EQU1__PRE 0x1CE
#define ATV_TOP_EQU1_EQU_C1__B 0
#define ATV_TOP_EQU1_EQU_C1__W 9
#define ATV_TOP_EQU1_EQU_C1__M 0x1FF
#define ATV_TOP_EQU1_EQU_C1__PRE 0x1CE
#define ATV_TOP_EQU1_EQU_C1_MN 0xCE
#define ATV_TOP_EQU2__A 0xC10016
#define ATV_TOP_EQU2__W 9
#define ATV_TOP_EQU2__M 0x1FF
#define ATV_TOP_EQU2__PRE 0xD2
#define ATV_TOP_EQU2_EQU_C2__B 0
#define ATV_TOP_EQU2_EQU_C2__W 9
#define ATV_TOP_EQU2_EQU_C2__M 0x1FF
#define ATV_TOP_EQU2_EQU_C2__PRE 0xD2
#define ATV_TOP_EQU2_EQU_C2_MN 0xD2
#define ATV_TOP_EQU3__A 0xC10017
#define ATV_TOP_EQU3__W 9
#define ATV_TOP_EQU3__M 0x1FF
#define ATV_TOP_EQU3__PRE 0x160
#define ATV_TOP_EQU3_EQU_C3__B 0
#define ATV_TOP_EQU3_EQU_C3__W 9
#define ATV_TOP_EQU3_EQU_C3__M 0x1FF
#define ATV_TOP_EQU3_EQU_C3__PRE 0x160
#define ATV_TOP_EQU3_EQU_C3_MN 0x60
#define ATV_TOP_ROT_MODE__A 0xC10018
#define ATV_TOP_ROT_MODE__W 1
#define ATV_TOP_ROT_MODE__M 0x1
#define ATV_TOP_ROT_MODE__PRE 0x0
#define ATV_TOP_ROT_MODE_AMPTH_DEPEND 0x0
#define ATV_TOP_ROT_MODE_ALWAYS 0x1
#define ATV_TOP_MOD_CONTROL__A 0xC10019
#define ATV_TOP_MOD_CONTROL__W 12
#define ATV_TOP_MOD_CONTROL__M 0xFFF
#define ATV_TOP_MOD_CONTROL__PRE 0x5B1
#define ATV_TOP_MOD_CONTROL_MOD_IR__B 0
#define ATV_TOP_MOD_CONTROL_MOD_IR__W 3
#define ATV_TOP_MOD_CONTROL_MOD_IR__M 0x7
#define ATV_TOP_MOD_CONTROL_MOD_IR__PRE 0x1
#define ATV_TOP_MOD_CONTROL_MOD_IR_MN 0x1
#define ATV_TOP_MOD_CONTROL_MOD_IR_FM 0x0
#define ATV_TOP_MOD_CONTROL_MOD_IF__B 3
#define ATV_TOP_MOD_CONTROL_MOD_IF__W 4
#define ATV_TOP_MOD_CONTROL_MOD_IF__M 0x78
#define ATV_TOP_MOD_CONTROL_MOD_IF__PRE 0x30
#define ATV_TOP_MOD_CONTROL_MOD_IF_MN 0x30
#define ATV_TOP_MOD_CONTROL_MOD_IF_FM 0x0
#define ATV_TOP_MOD_CONTROL_MOD_MODE__B 7
#define ATV_TOP_MOD_CONTROL_MOD_MODE__W 1
#define ATV_TOP_MOD_CONTROL_MOD_MODE__M 0x80
#define ATV_TOP_MOD_CONTROL_MOD_MODE__PRE 0x80
#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE 0x0
#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL 0x80
#define ATV_TOP_MOD_CONTROL_MOD_TH__B 8
#define ATV_TOP_MOD_CONTROL_MOD_TH__W 4
#define ATV_TOP_MOD_CONTROL_MOD_TH__M 0xF00
#define ATV_TOP_MOD_CONTROL_MOD_TH__PRE 0x500
#define ATV_TOP_MOD_CONTROL_MOD_TH_MN 0x500
#define ATV_TOP_MOD_CONTROL_MOD_TH_FM 0x0
#define ATV_TOP_STD__A 0xC1001A
#define ATV_TOP_STD__W 2
#define ATV_TOP_STD__M 0x3
#define ATV_TOP_STD__PRE 0x0
#define ATV_TOP_STD_MODE__B 0
#define ATV_TOP_STD_MODE__W 1
#define ATV_TOP_STD_MODE__M 0x1
#define ATV_TOP_STD_MODE__PRE 0x0
#define ATV_TOP_STD_MODE_MN 0x0
#define ATV_TOP_STD_MODE_FM 0x1
#define ATV_TOP_STD_VID_POL__B 1
#define ATV_TOP_STD_VID_POL__W 1
#define ATV_TOP_STD_VID_POL__M 0x2
#define ATV_TOP_STD_VID_POL__PRE 0x0
#define ATV_TOP_STD_VID_POL_NEG 0x0
#define ATV_TOP_STD_VID_POL_POS 0x2
#define ATV_TOP_VID_AMP__A 0xC1001B
#define ATV_TOP_VID_AMP__W 12
#define ATV_TOP_VID_AMP__M 0xFFF
#define ATV_TOP_VID_AMP__PRE 0x380
#define ATV_TOP_VID_AMP_MN 0x380
#define ATV_TOP_VID_AMP_FM 0x0
#define ATV_TOP_VID_PEAK__A 0xC1001C
#define ATV_TOP_VID_PEAK__W 5
#define ATV_TOP_VID_PEAK__M 0x1F
#define ATV_TOP_VID_PEAK__PRE 0x1
#define ATV_TOP_FAGC_TH__A 0xC1001D
#define ATV_TOP_FAGC_TH__W 11
#define ATV_TOP_FAGC_TH__M 0x7FF
#define ATV_TOP_FAGC_TH__PRE 0x2B2
#define ATV_TOP_FAGC_TH_MN 0x2B2
#define ATV_TOP_SYNC_SLICE__A 0xC1001E
#define ATV_TOP_SYNC_SLICE__W 11
#define ATV_TOP_SYNC_SLICE__M 0x7FF
#define ATV_TOP_SYNC_SLICE__PRE 0x243
#define ATV_TOP_SYNC_SLICE_MN 0x243
#define ATV_TOP_SIF_GAIN__A 0xC1001F
#define ATV_TOP_SIF_GAIN__W 11
#define ATV_TOP_SIF_GAIN__M 0x7FF
#define ATV_TOP_SIF_GAIN__PRE 0x0
#define ATV_TOP_SIF_TP__A 0xC10020
#define ATV_TOP_SIF_TP__W 6
#define ATV_TOP_SIF_TP__M 0x3F
#define ATV_TOP_SIF_TP__PRE 0x0
#define ATV_TOP_MOD_ACCU__A 0xC10021
#define ATV_TOP_MOD_ACCU__W 10
#define ATV_TOP_MOD_ACCU__M 0x3FF
#define ATV_TOP_MOD_ACCU__PRE 0x0
#define ATV_TOP_CR_FREQ__A 0xC10022
#define ATV_TOP_CR_FREQ__W 8
#define ATV_TOP_CR_FREQ__M 0xFF
#define ATV_TOP_CR_FREQ__PRE 0x0
#define ATV_TOP_CR_PHAD__A 0xC10023
#define ATV_TOP_CR_PHAD__W 12
#define ATV_TOP_CR_PHAD__M 0xFFF
#define ATV_TOP_CR_PHAD__PRE 0x0
#define ATV_TOP_AF_SIF_ATT__A 0xC10024
#define ATV_TOP_AF_SIF_ATT__W 2
#define ATV_TOP_AF_SIF_ATT__M 0x3
#define ATV_TOP_AF_SIF_ATT__PRE 0x0
#define ATV_TOP_AF_SIF_ATT_0DB 0x0
#define ATV_TOP_AF_SIF_ATT_M3DB 0x1
#define ATV_TOP_AF_SIF_ATT_M6DB 0x2
#define ATV_TOP_AF_SIF_ATT_M9DB 0x3
#define ATV_TOP_STDBY__A 0xC10025
#define ATV_TOP_STDBY__W 2
#define ATV_TOP_STDBY__M 0x3
#define ATV_TOP_STDBY__PRE 0x1
#define ATV_TOP_STDBY_SIF_STDBY__B 0
#define ATV_TOP_STDBY_SIF_STDBY__W 1
#define ATV_TOP_STDBY_SIF_STDBY__M 0x1
#define ATV_TOP_STDBY_SIF_STDBY__PRE 0x1
#define ATV_TOP_STDBY_SIF_STDBY_ACTIVE 0x0
#define ATV_TOP_STDBY_SIF_STDBY_STANDBY 0x1
#define ATV_TOP_STDBY_CVBS_STDBY__B 1
#define ATV_TOP_STDBY_CVBS_STDBY__W 1
#define ATV_TOP_STDBY_CVBS_STDBY__M 0x2
#define ATV_TOP_STDBY_CVBS_STDBY__PRE 0x0
#define ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE 0x0
#define ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY 0x2
#define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0x2
#define ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY 0x0
#define ATV_TOP_OVERRIDE_SFR__A 0xC10026
#define ATV_TOP_OVERRIDE_SFR__W 1
#define ATV_TOP_OVERRIDE_SFR__M 0x1
#define ATV_TOP_OVERRIDE_SFR__PRE 0x0
#define ATV_TOP_OVERRIDE_SFR_ACTIVE 0x0
#define ATV_TOP_OVERRIDE_SFR_OVERRIDE 0x1
#define ATV_TOP_SFR_VID_GAIN__A 0xC10027
#define ATV_TOP_SFR_VID_GAIN__W 16
#define ATV_TOP_SFR_VID_GAIN__M 0xFFFF
#define ATV_TOP_SFR_VID_GAIN__PRE 0x0
#define ATV_TOP_SFR_AGC_RES__A 0xC10028
#define ATV_TOP_SFR_AGC_RES__W 5
#define ATV_TOP_SFR_AGC_RES__M 0x1F
#define ATV_TOP_SFR_AGC_RES__PRE 0x0
#define ATV_TOP_OVM_COMP__A 0xC10029
#define ATV_TOP_OVM_COMP__W 12
#define ATV_TOP_OVM_COMP__M 0xFFF
#define ATV_TOP_OVM_COMP__PRE 0x0
#define ATV_TOP_OUT_CONF__A 0xC1002A
#define ATV_TOP_OUT_CONF__W 5
#define ATV_TOP_OUT_CONF__M 0x1F
#define ATV_TOP_OUT_CONF__PRE 0x0
#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B 0
#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W 1
#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M 0x1
#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE 0x0
#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED 0x0
#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED 0x1
#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B 1
#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W 1
#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M 0x2
#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE 0x0
#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED 0x0
#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED 0x2
#define ATV_TOP_OUT_CONF_SIF20_SIGN__B 2
#define ATV_TOP_OUT_CONF_SIF20_SIGN__W 1
#define ATV_TOP_OUT_CONF_SIF20_SIGN__M 0x4
#define ATV_TOP_OUT_CONF_SIF20_SIGN__PRE 0x0
#define ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED 0x0
#define ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED 0x4
#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__B 3
#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__W 1
#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__M 0x8
#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE 0x0
#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL 0x0
#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED 0x8
#define ATV_TOP_OUT_CONF_SIF_DAC_BR__B 4
#define ATV_TOP_OUT_CONF_SIF_DAC_BR__W 1
#define ATV_TOP_OUT_CONF_SIF_DAC_BR__M 0x10
#define ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE 0x0
#define ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL 0x0
#define ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED 0x10
#define ATV_AFT_COMM_EXEC__A 0xFF0000
#define ATV_AFT_COMM_EXEC__W 2
#define ATV_AFT_COMM_EXEC__M 0x3
#define ATV_AFT_COMM_EXEC__PRE 0x0
#define ATV_AFT_COMM_EXEC_STOP 0x0
#define ATV_AFT_COMM_EXEC_ACTIVE 0x1
#define ATV_AFT_COMM_EXEC_HOLD 0x2
#define ATV_AFT_TST__A 0xFF0010
#define ATV_AFT_TST__W 4
#define ATV_AFT_TST__M 0xF
#define ATV_AFT_TST__PRE 0x0
#define AUD_COMM_EXEC__A 0x1000000
#define AUD_COMM_EXEC__W 2
#define AUD_COMM_EXEC__M 0x3
#define AUD_COMM_EXEC__PRE 0x0
#define AUD_COMM_EXEC_STOP 0x0
#define AUD_COMM_EXEC_ACTIVE 0x1
#define AUD_COMM_MB__A 0x1000002
#define AUD_COMM_MB__W 16
#define AUD_COMM_MB__M 0xFFFF
#define AUD_COMM_MB__PRE 0x0
#define AUD_TOP_COMM_EXEC__A 0x1010000
#define AUD_TOP_COMM_EXEC__W 2
#define AUD_TOP_COMM_EXEC__M 0x3
#define AUD_TOP_COMM_EXEC__PRE 0x0
#define AUD_TOP_COMM_EXEC_STOP 0x0
#define AUD_TOP_COMM_EXEC_ACTIVE 0x1
#define AUD_TOP_COMM_MB__A 0x1010002
#define AUD_TOP_COMM_MB__W 16
#define AUD_TOP_COMM_MB__M 0xFFFF
#define AUD_TOP_COMM_MB__PRE 0x0
#define AUD_TOP_COMM_MB_CTL__B 0
#define AUD_TOP_COMM_MB_CTL__W 1
#define AUD_TOP_COMM_MB_CTL__M 0x1
#define AUD_TOP_COMM_MB_CTL__PRE 0x0
#define AUD_TOP_COMM_MB_CTL_CTR_OFF 0x0
#define AUD_TOP_COMM_MB_CTL_CTR_ON 0x1
#define AUD_TOP_COMM_MB_OBS__B 1
#define AUD_TOP_COMM_MB_OBS__W 1
#define AUD_TOP_COMM_MB_OBS__M 0x2
#define AUD_TOP_COMM_MB_OBS__PRE 0x0
#define AUD_TOP_COMM_MB_OBS_OBS_OFF 0x0
#define AUD_TOP_COMM_MB_OBS_OBS_ON 0x2
#define AUD_TOP_COMM_MB_MUX_CTRL__B 2
#define AUD_TOP_COMM_MB_MUX_CTRL__W 4
#define AUD_TOP_COMM_MB_MUX_CTRL__M 0x3C
#define AUD_TOP_COMM_MB_MUX_CTRL__PRE 0x0
#define AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO 0x0
#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS 0x4
#define AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC 0x8
#define AUD_TOP_COMM_MB_MUX_CTRL_SAOUT 0xC
#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ 0x10
#define AUD_TOP_COMM_MB_MUX_OBS__B 6
#define AUD_TOP_COMM_MB_MUX_OBS__W 4
#define AUD_TOP_COMM_MB_MUX_OBS__M 0x3C0
#define AUD_TOP_COMM_MB_MUX_OBS__PRE 0x0
#define AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO 0x0
#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS 0x40
#define AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC 0x80
#define AUD_TOP_COMM_MB_MUX_OBS_SAOUT 0xC0
#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ 0x100
#define AUD_TOP_TR_MDE__A 0x1010010
#define AUD_TOP_TR_MDE__W 5
#define AUD_TOP_TR_MDE__M 0x1F
#define AUD_TOP_TR_MDE__PRE 0x18
#define AUD_TOP_TR_MDE_FIFO_SIZE__B 0
#define AUD_TOP_TR_MDE_FIFO_SIZE__W 4
#define AUD_TOP_TR_MDE_FIFO_SIZE__M 0xF
#define AUD_TOP_TR_MDE_FIFO_SIZE__PRE 0x8
#define AUD_TOP_TR_MDE_RD_LOCK__B 4
#define AUD_TOP_TR_MDE_RD_LOCK__W 1
#define AUD_TOP_TR_MDE_RD_LOCK__M 0x10
#define AUD_TOP_TR_MDE_RD_LOCK__PRE 0x10
#define AUD_TOP_TR_MDE_RD_LOCK_NORMAL 0x0
#define AUD_TOP_TR_MDE_RD_LOCK_LOCK 0x10
#define AUD_TOP_TR_CTR__A 0x1010011
#define AUD_TOP_TR_CTR__W 4
#define AUD_TOP_TR_CTR__M 0xF
#define AUD_TOP_TR_CTR__PRE 0x0
#define AUD_TOP_TR_CTR_FIFO_RD_RDY__B 0
#define AUD_TOP_TR_CTR_FIFO_RD_RDY__W 1
#define AUD_TOP_TR_CTR_FIFO_RD_RDY__M 0x1
#define AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE 0x0
#define AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY 0x0
#define AUD_TOP_TR_CTR_FIFO_RD_RDY_READY 0x1
#define AUD_TOP_TR_CTR_FIFO_EMPTY__B 1
#define AUD_TOP_TR_CTR_FIFO_EMPTY__W 1
#define AUD_TOP_TR_CTR_FIFO_EMPTY__M 0x2
#define AUD_TOP_TR_CTR_FIFO_EMPTY__PRE 0x0
#define AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY 0x0
#define AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY 0x2
#define AUD_TOP_TR_CTR_FIFO_LOCK__B 2
#define AUD_TOP_TR_CTR_FIFO_LOCK__W 1
#define AUD_TOP_TR_CTR_FIFO_LOCK__M 0x4
#define AUD_TOP_TR_CTR_FIFO_LOCK__PRE 0x0
#define AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED 0x0
#define AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED 0x4
#define AUD_TOP_TR_CTR_FIFO_FULL__B 3
#define AUD_TOP_TR_CTR_FIFO_FULL__W 1
#define AUD_TOP_TR_CTR_FIFO_FULL__M 0x8
#define AUD_TOP_TR_CTR_FIFO_FULL__PRE 0x0
#define AUD_TOP_TR_CTR_FIFO_FULL_EMPTY 0x0
#define AUD_TOP_TR_CTR_FIFO_FULL_FULL 0x8
#define AUD_TOP_TR_RD_REG__A 0x1010012
#define AUD_TOP_TR_RD_REG__W 16
#define AUD_TOP_TR_RD_REG__M 0xFFFF
#define AUD_TOP_TR_RD_REG__PRE 0x0
#define AUD_TOP_TR_RD_REG_RESULT__B 0
#define AUD_TOP_TR_RD_REG_RESULT__W 16
#define AUD_TOP_TR_RD_REG_RESULT__M 0xFFFF
#define AUD_TOP_TR_RD_REG_RESULT__PRE 0x0
#define AUD_TOP_TR_TIMER__A 0x1010013
#define AUD_TOP_TR_TIMER__W 16
#define AUD_TOP_TR_TIMER__M 0xFFFF
#define AUD_TOP_TR_TIMER__PRE 0x0
#define AUD_TOP_TR_TIMER_CYCLES__B 0
#define AUD_TOP_TR_TIMER_CYCLES__W 16
#define AUD_TOP_TR_TIMER_CYCLES__M 0xFFFF
#define AUD_TOP_TR_TIMER_CYCLES__PRE 0x0
#define AUD_TOP_DEMOD_TBO_SEL__A 0x1010014
#define AUD_TOP_DEMOD_TBO_SEL__W 5
#define AUD_TOP_DEMOD_TBO_SEL__M 0x1F
#define AUD_TOP_DEMOD_TBO_SEL__PRE 0x0
#define AUD_DEM_WR_MODUS__A 0x1030030
#define AUD_DEM_WR_MODUS__W 16
#define AUD_DEM_WR_MODUS__M 0xFFFF
#define AUD_DEM_WR_MODUS__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_ASS__B 0
#define AUD_DEM_WR_MODUS_MOD_ASS__W 1
#define AUD_DEM_WR_MODUS_MOD_ASS__M 0x1
#define AUD_DEM_WR_MODUS_MOD_ASS__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_ASS_OFF 0x0
#define AUD_DEM_WR_MODUS_MOD_ASS_ON 0x1
#define AUD_DEM_WR_MODUS_MOD_STATINTERR__B 1
#define AUD_DEM_WR_MODUS_MOD_STATINTERR__W 1
#define AUD_DEM_WR_MODUS_MOD_STATINTERR__M 0x2
#define AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE 0x0
#define AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE 0x2
#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B 2
#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W 1
#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M 0x4
#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED 0x0
#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED 0x4
#define AUD_DEM_WR_MODUS_MOD_HDEV_A__B 8
#define AUD_DEM_WR_MODUS_MOD_HDEV_A__W 1
#define AUD_DEM_WR_MODUS_MOD_HDEV_A__M 0x100
#define AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL 0x0
#define AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION 0x100
#define AUD_DEM_WR_MODUS_MOD_CM_A__B 9
#define AUD_DEM_WR_MODUS_MOD_CM_A__W 1
#define AUD_DEM_WR_MODUS_MOD_CM_A__M 0x200
#define AUD_DEM_WR_MODUS_MOD_CM_A__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_CM_A_MUTE 0x0
#define AUD_DEM_WR_MODUS_MOD_CM_A_NOISE 0x200
#define AUD_DEM_WR_MODUS_MOD_CM_B__B 10
#define AUD_DEM_WR_MODUS_MOD_CM_B__W 1
#define AUD_DEM_WR_MODUS_MOD_CM_B__M 0x400
#define AUD_DEM_WR_MODUS_MOD_CM_B__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_CM_B_MUTE 0x0
#define AUD_DEM_WR_MODUS_MOD_CM_B_NOISE 0x400
#define AUD_DEM_WR_MODUS_MOD_FMRADIO__B 11
#define AUD_DEM_WR_MODUS_MOD_FMRADIO__W 1
#define AUD_DEM_WR_MODUS_MOD_FMRADIO__M 0x800
#define AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U 0x0
#define AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U 0x800
#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__B 12
#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__W 1
#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__M 0x1000
#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM 0x0
#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K 0x1000
#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__B 13
#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__W 2
#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__M 0x6000
#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA 0x0
#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC 0x2000
#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ 0x4000
#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA 0x6000
#define AUD_DEM_WR_MODUS_MOD_BTSC__B 15
#define AUD_DEM_WR_MODUS_MOD_BTSC__W 1
#define AUD_DEM_WR_MODUS_MOD_BTSC__M 0x8000
#define AUD_DEM_WR_MODUS_MOD_BTSC__PRE 0x0
#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO 0x0
#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP 0x8000
#define AUD_DEM_WR_STANDARD_SEL__A 0x1030020
#define AUD_DEM_WR_STANDARD_SEL__W 16
#define AUD_DEM_WR_STANDARD_SEL__M 0xFFFF
#define AUD_DEM_WR_STANDARD_SEL__PRE 0x0
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__B 0
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__W 12
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__M 0xFFF
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE 0x0
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO 0x1
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA 0x2
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM 0x3
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1 0x4
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2 0x5
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3 0x7
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM 0x8
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM 0x9
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM 0xA
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM 0xB
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO 0x20
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP 0x21
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J 0x30
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO 0x40
#define AUD_DEM_RD_STANDARD_RES__A 0x102007E
#define AUD_DEM_RD_STANDARD_RES__W 16
#define AUD_DEM_RD_STANDARD_RES__M 0xFFFF
#define AUD_DEM_RD_STANDARD_RES__PRE 0x0
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__B 0
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__W 16
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__M 0xFFFF
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE 0x0
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD 0x0
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM 0x2
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM 0x3
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM 0x4
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM 0x5
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM 0x7
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM 0x8
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM 0x9
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM 0xA
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM 0xB
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO 0x20
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP 0x21
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J 0x30
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO 0x40
#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE 0x7FF
#define AUD_DEM_RD_STATUS__A 0x1020200
#define AUD_DEM_RD_STATUS__W 16
#define AUD_DEM_RD_STATUS__M 0xFFFF
#define AUD_DEM_RD_STATUS__PRE 0x0
#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__B 0
#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__W 1
#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__M 0x1
#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE 0x0
#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA 0x0
#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA 0x1
#define AUD_DEM_RD_STATUS_STAT_CARR_A__B 1
#define AUD_DEM_RD_STATUS_STAT_CARR_A__W 1
#define AUD_DEM_RD_STATUS_STAT_CARR_A__M 0x2
#define AUD_DEM_RD_STATUS_STAT_CARR_A__PRE 0x0
#define AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED 0x0
#define AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED 0x2
#define AUD_DEM_RD_STATUS_STAT_CARR_B__B 2
#define AUD_DEM_RD_STATUS_STAT_CARR_B__W 1
#define AUD_DEM_RD_STATUS_STAT_CARR_B__M 0x4
#define AUD_DEM_RD_STATUS_STAT_CARR_B__PRE 0x0
#define AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED 0x0
#define AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED 0x4
#define AUD_DEM_RD_STATUS_STAT_NICAM__B 5
#define AUD_DEM_RD_STATUS_STAT_NICAM__W 1
#define AUD_DEM_RD_STATUS_STAT_NICAM__M 0x20
#define AUD_DEM_RD_STATUS_STAT_NICAM__PRE 0x0
#define AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM 0x0
#define AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED 0x20
#define AUD_DEM_RD_STATUS_STAT_STEREO__B 6
#define AUD_DEM_RD_STATUS_STAT_STEREO__W 1
#define AUD_DEM_RD_STATUS_STAT_STEREO__M 0x40
#define AUD_DEM_RD_STATUS_STAT_STEREO__PRE 0x0
#define AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO 0x0
#define AUD_DEM_RD_STATUS_STAT_STEREO_STEREO 0x40
#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B 7
#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W 1
#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M 0x80
#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE 0x0
#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM 0x0
#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM 0x80
#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B 8
#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W 1
#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M 0x100
#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE 0x0
#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP 0x0
#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP 0x100
#define AUD_DEM_RD_STATUS_BAD_NICAM__B 9
#define AUD_DEM_RD_STATUS_BAD_NICAM__W 1
#define AUD_DEM_RD_STATUS_BAD_NICAM__M 0x200
#define AUD_DEM_RD_STATUS_BAD_NICAM__PRE 0x0
#define AUD_DEM_RD_STATUS_BAD_NICAM_OK 0x0
#define AUD_DEM_RD_STATUS_BAD_NICAM_BAD 0x200
#define AUD_DEM_RD_RDS_ARRAY_CNT__A 0x102020F
#define AUD_DEM_RD_RDS_ARRAY_CNT__W 12
#define AUD_DEM_RD_RDS_ARRAY_CNT__M 0xFFF
#define AUD_DEM_RD_RDS_ARRAY_CNT__PRE 0x0
#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B 0
#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W 12
#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M 0xFFF
#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE 0x0
#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID 0xFFF
#define AUD_DEM_RD_RDS_DATA__A 0x1020210
#define AUD_DEM_RD_RDS_DATA__W 12
#define AUD_DEM_RD_RDS_DATA__M 0xFFF
#define AUD_DEM_RD_RDS_DATA__PRE 0x0
#define AUD_DSP_WR_FM_PRESC__A 0x105000E
#define AUD_DSP_WR_FM_PRESC__W 16
#define AUD_DSP_WR_FM_PRESC__M 0xFFFF
#define AUD_DSP_WR_FM_PRESC__PRE 0x0
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B 8
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W 8
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M 0xFF00
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE 0x0
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION 0x7F00
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION 0x4800
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION 0x3000
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION 0x2400
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION 0x1800
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION 0x1300
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION 0x900
#define AUD_DSP_WR_NICAM_PRESC__A 0x1050010
#define AUD_DSP_WR_NICAM_PRESC__W 16
#define AUD_DSP_WR_NICAM_PRESC__M 0xFFFF
#define AUD_DSP_WR_NICAM_PRESC__PRE 0x0
#define AUD_DSP_WR_VOLUME__A 0x1050000
#define AUD_DSP_WR_VOLUME__W 16
#define AUD_DSP_WR_VOLUME__M 0xFFFF
#define AUD_DSP_WR_VOLUME__PRE 0x0
#define AUD_DSP_WR_VOLUME_VOL_MAIN__B 8
#define AUD_DSP_WR_VOLUME_VOL_MAIN__W 8
#define AUD_DSP_WR_VOLUME_VOL_MAIN__M 0xFF00
#define AUD_DSP_WR_VOLUME_VOL_MAIN__PRE 0x0
#define AUD_DSP_WR_SRC_I2S_MATR__A 0x1050038
#define AUD_DSP_WR_SRC_I2S_MATR__W 16
#define AUD_DSP_WR_SRC_I2S_MATR__M 0xFFFF
#define AUD_DSP_WR_SRC_I2S_MATR__PRE 0x0
#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B 8
#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W 8
#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M 0xFF00
#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE 0x0
#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO 0x0
#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB 0x100
#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A 0x300
#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B 0x400
#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B 0
#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W 8
#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M 0xFF
#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE 0x0
#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A 0x0
#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B 0x10
#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO 0x20
#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO 0x30
#define AUD_DSP_WR_AVC__A 0x1050029
#define AUD_DSP_WR_AVC__W 16
#define AUD_DSP_WR_AVC__M 0xFFFF
#define AUD_DSP_WR_AVC__PRE 0x0
#define AUD_DSP_WR_AVC_AVC_ON__B 14
#define AUD_DSP_WR_AVC_AVC_ON__W 2
#define AUD_DSP_WR_AVC_AVC_ON__M 0xC000
#define AUD_DSP_WR_AVC_AVC_ON__PRE 0x0
#define AUD_DSP_WR_AVC_AVC_ON_OFF 0x0
#define AUD_DSP_WR_AVC_AVC_ON_ON 0xC000
#define AUD_DSP_WR_AVC_AVC_DECAY__B 8
#define AUD_DSP_WR_AVC_AVC_DECAY__W 4
#define AUD_DSP_WR_AVC_AVC_DECAY__M 0xF00
#define AUD_DSP_WR_AVC_AVC_DECAY__PRE 0x0
#define AUD_DSP_WR_AVC_AVC_DECAY_8_SEC 0x800
#define AUD_DSP_WR_AVC_AVC_DECAY_4_SEC 0x400
#define AUD_DSP_WR_AVC_AVC_DECAY_2_SEC 0x200
#define AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC 0x100
#define AUD_DSP_WR_AVC_AVC_REF_LEV__B 4
#define AUD_DSP_WR_AVC_AVC_REF_LEV__W 4
#define AUD_DSP_WR_AVC_AVC_REF_LEV__M 0xF0
#define AUD_DSP_WR_AVC_AVC_REF_LEV__PRE 0x0
#define AUD_DSP_WR_AVC_AVC_MAX_ATT__B 2
#define AUD_DSP_WR_AVC_AVC_MAX_ATT__W 2
#define AUD_DSP_WR_AVC_AVC_MAX_ATT__M 0xC
#define AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE 0x0
#define AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB 0x0
#define AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB 0x4
#define AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB 0x8
#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__B 0
#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__W 2
#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__M 0x3
#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE 0x0
#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB 0x0
#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB 0x1
#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB 0x3
#define AUD_DSP_WR_QPEAK__A 0x105000C
#define AUD_DSP_WR_QPEAK__W 16
#define AUD_DSP_WR_QPEAK__M 0xFFFF
#define AUD_DSP_WR_QPEAK__PRE 0x0
#define AUD_DSP_WR_QPEAK_SRC_QP__B 8
#define AUD_DSP_WR_QPEAK_SRC_QP__W 8
#define AUD_DSP_WR_QPEAK_SRC_QP__M 0xFF00
#define AUD_DSP_WR_QPEAK_SRC_QP__PRE 0x0
#define AUD_DSP_WR_QPEAK_SRC_QP_MONO 0x0
#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB 0x100
#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A 0x300
#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B 0x400
#define AUD_DSP_WR_QPEAK_MAT_QP__B 0
#define AUD_DSP_WR_QPEAK_MAT_QP__W 8
#define AUD_DSP_WR_QPEAK_MAT_QP__M 0xFF
#define AUD_DSP_WR_QPEAK_MAT_QP__PRE 0x0
#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A 0x0
#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B 0x10
#define AUD_DSP_WR_QPEAK_MAT_QP_STEREO 0x20
#define AUD_DSP_WR_QPEAK_MAT_QP_MONO 0x30
#define AUD_DSP_RD_QPEAK_L__A 0x1040019
#define AUD_DSP_RD_QPEAK_L__W 16
#define AUD_DSP_RD_QPEAK_L__M 0xFFFF
#define AUD_DSP_RD_QPEAK_L__PRE 0x0
#define AUD_DSP_RD_QPEAK_R__A 0x104001A
#define AUD_DSP_RD_QPEAK_R__W 16
#define AUD_DSP_RD_QPEAK_R__M 0xFFFF
#define AUD_DSP_RD_QPEAK_R__PRE 0x0
#define AUD_DSP_WR_BEEPER__A 0x1050014
#define AUD_DSP_WR_BEEPER__W 16
#define AUD_DSP_WR_BEEPER__M 0xFFFF
#define AUD_DSP_WR_BEEPER__PRE 0x0
#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__B 8
#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__W 7
#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__M 0x7F00
#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE 0x0
#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B 0
#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W 7
#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M 0x7F
#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE 0x0
#define AUD_DEM_WR_I2S_CONFIG2__A 0x1030050
#define AUD_DEM_WR_I2S_CONFIG2__W 16
#define AUD_DEM_WR_I2S_CONFIG2__M 0xFFFF
#define AUD_DEM_WR_I2S_CONFIG2__PRE 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B 6
#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W 1
#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M 0x40
#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED 0x40
#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B 4
#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W 1
#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M 0x10
#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE 0x10
#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B 3
#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W 1
#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M 0x8
#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE 0x8
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B 2
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W 1
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M 0x4
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH 0x4
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B 1
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W 1
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M 0x2
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY 0x2
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B 0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W 1
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M 0x1
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16 0x1
#define AUD_DSP_WR_I2S_OUT_FS__A 0x105002A
#define AUD_DSP_WR_I2S_OUT_FS__W 16
#define AUD_DSP_WR_I2S_OUT_FS__M 0xFFFF
#define AUD_DSP_WR_I2S_OUT_FS__PRE 0x0
#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B 0
#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W 16
#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M 0xFFFF
#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE 0x0
#define AUD_DSP_WR_AV_SYNC__A 0x105002B
#define AUD_DSP_WR_AV_SYNC__W 16
#define AUD_DSP_WR_AV_SYNC__M 0xFFFF
#define AUD_DSP_WR_AV_SYNC__PRE 0x0
#define AUD_DSP_WR_AV_SYNC_AV_ON__B 15
#define AUD_DSP_WR_AV_SYNC_AV_ON__W 1
#define AUD_DSP_WR_AV_SYNC_AV_ON__M 0x8000
#define AUD_DSP_WR_AV_SYNC_AV_ON__PRE 0x0
#define AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE 0x0
#define AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE 0x8000
#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B 14
#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W 1
#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M 0x4000
#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE 0x0
#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME 0x0
#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC 0x4000
#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B 0
#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W 2
#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M 0x3
#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE 0x0
#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO 0x0
#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM 0x1
#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC 0x2
#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME 0x3
#define AUD_DSP_RD_STATUS2__A 0x104007B
#define AUD_DSP_RD_STATUS2__W 16
#define AUD_DSP_RD_STATUS2__M 0xFFFF
#define AUD_DSP_RD_STATUS2__PRE 0x0
#define AUD_DSP_RD_STATUS2_AV_ACTIVE__B 15
#define AUD_DSP_RD_STATUS2_AV_ACTIVE__W 1
#define AUD_DSP_RD_STATUS2_AV_ACTIVE__M 0x8000
#define AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE 0x0
#define AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC 0x0
#define AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE 0x8000
#define AUD_DSP_RD_XDFP_FW__A 0x104001D
#define AUD_DSP_RD_XDFP_FW__W 16
#define AUD_DSP_RD_XDFP_FW__M 0xFFFF
#define AUD_DSP_RD_XDFP_FW__PRE 0x344
#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B 0
#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W 16
#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M 0xFFFF
#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE 0x344
#define AUD_DSP_RD_XFP_FW__A 0x10404B8
#define AUD_DSP_RD_XFP_FW__W 16
#define AUD_DSP_RD_XFP_FW__M 0xFFFF
#define AUD_DSP_RD_XFP_FW__PRE 0x42
#define AUD_DSP_RD_XFP_FW_FP_FW_REV__B 0
#define AUD_DSP_RD_XFP_FW_FP_FW_REV__W 16
#define AUD_DSP_RD_XFP_FW_FP_FW_REV__M 0xFFFF
#define AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE 0x42
#define AUD_DEM_WR_DCO_B_HI__A 0x103009B
#define AUD_DEM_WR_DCO_B_HI__W 16
#define AUD_DEM_WR_DCO_B_HI__M 0xFFFF
#define AUD_DEM_WR_DCO_B_HI__PRE 0x0
#define AUD_DEM_WR_DCO_B_LO__A 0x1030093
#define AUD_DEM_WR_DCO_B_LO__W 16
#define AUD_DEM_WR_DCO_B_LO__M 0xFFFF
#define AUD_DEM_WR_DCO_B_LO__PRE 0x0
#define AUD_DEM_WR_DCO_A_HI__A 0x10300AB
#define AUD_DEM_WR_DCO_A_HI__W 16
#define AUD_DEM_WR_DCO_A_HI__M 0xFFFF
#define AUD_DEM_WR_DCO_A_HI__PRE 0x0
#define AUD_DEM_WR_DCO_A_LO__A 0x10300A3
#define AUD_DEM_WR_DCO_A_LO__W 16
#define AUD_DEM_WR_DCO_A_LO__M 0xFFFF
#define AUD_DEM_WR_DCO_A_LO__PRE 0x0
#define AUD_DEM_WR_NICAM_THRSHLD__A 0x1030021
#define AUD_DEM_WR_NICAM_THRSHLD__W 16
#define AUD_DEM_WR_NICAM_THRSHLD__M 0xFFFF
#define AUD_DEM_WR_NICAM_THRSHLD__PRE 0x2BC
#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B 0
#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W 12
#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M 0xFFF
#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE 0x2BC
#define AUD_DEM_WR_A2_THRSHLD__A 0x1030022
#define AUD_DEM_WR_A2_THRSHLD__W 16
#define AUD_DEM_WR_A2_THRSHLD__M 0xFFFF
#define AUD_DEM_WR_A2_THRSHLD__PRE 0x190
#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__B 0
#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__W 12
#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__M 0xFFF
#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE 0x190
#define AUD_DEM_WR_BTSC_THRSHLD__A 0x1030023
#define AUD_DEM_WR_BTSC_THRSHLD__W 16
#define AUD_DEM_WR_BTSC_THRSHLD__M 0xFFFF
#define AUD_DEM_WR_BTSC_THRSHLD__PRE 0xC
#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B 0
#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W 12
#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M 0xFFF
#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE 0xC
#define AUD_DEM_WR_CM_A_THRSHLD__A 0x1030024
#define AUD_DEM_WR_CM_A_THRSHLD__W 16
#define AUD_DEM_WR_CM_A_THRSHLD__M 0xFFFF
#define AUD_DEM_WR_CM_A_THRSHLD__PRE 0x2A
#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B 0
#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W 12
#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M 0xFFF
#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE 0x2A
#define AUD_DEM_WR_CM_B_THRSHLD__A 0x1030025
#define AUD_DEM_WR_CM_B_THRSHLD__W 16
#define AUD_DEM_WR_CM_B_THRSHLD__M 0xFFFF
#define AUD_DEM_WR_CM_B_THRSHLD__PRE 0x2A
#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B 0
#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W 12
#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M 0xFFF
#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE 0x2A
#define AUD_DEM_RD_NIC_C_AD_BITS__A 0x1020023
#define AUD_DEM_RD_NIC_C_AD_BITS__W 16
#define AUD_DEM_RD_NIC_C_AD_BITS__M 0xFFFF
#define AUD_DEM_RD_NIC_C_AD_BITS__PRE 0x0
#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B 0
#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W 1
#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M 0x1
#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE 0x0
#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED 0x0
#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED 0x1
#define AUD_DEM_RD_NIC_C_AD_BITS_C__B 1
#define AUD_DEM_RD_NIC_C_AD_BITS_C__W 4
#define AUD_DEM_RD_NIC_C_AD_BITS_C__M 0x1E
#define AUD_DEM_RD_NIC_C_AD_BITS_C__PRE 0x0
#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B 5
#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W 3
#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M 0xE0
#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE 0x0
#define AUD_DEM_RD_NIC_ADD_BITS_HI__A 0x1020038
#define AUD_DEM_RD_NIC_ADD_BITS_HI__W 16
#define AUD_DEM_RD_NIC_ADD_BITS_HI__M 0xFFFF
#define AUD_DEM_RD_NIC_ADD_BITS_HI__PRE 0x0
#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B 0
#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W 8
#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M 0xFF
#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE 0x0
#define AUD_DEM_RD_NIC_CIB__A 0x1020038
#define AUD_DEM_RD_NIC_CIB__W 16
#define AUD_DEM_RD_NIC_CIB__M 0xFFFF
#define AUD_DEM_RD_NIC_CIB__PRE 0x0
#define AUD_DEM_RD_NIC_CIB_CIB2__B 0
#define AUD_DEM_RD_NIC_CIB_CIB2__W 1
#define AUD_DEM_RD_NIC_CIB_CIB2__M 0x1
#define AUD_DEM_RD_NIC_CIB_CIB2__PRE 0x0
#define AUD_DEM_RD_NIC_CIB_CIB1__B 1
#define AUD_DEM_RD_NIC_CIB_CIB1__W 1
#define AUD_DEM_RD_NIC_CIB_CIB1__M 0x2
#define AUD_DEM_RD_NIC_CIB_CIB1__PRE 0x0
#define AUD_DEM_RD_NIC_ERROR_RATE__A 0x1020057
#define AUD_DEM_RD_NIC_ERROR_RATE__W 16
#define AUD_DEM_RD_NIC_ERROR_RATE__M 0xFFFF
#define AUD_DEM_RD_NIC_ERROR_RATE__PRE 0x0
#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B 0
#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W 12
#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M 0xFFF
#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE 0x0
#define AUD_DEM_WR_FM_DEEMPH__A 0x103000F
#define AUD_DEM_WR_FM_DEEMPH__W 16
#define AUD_DEM_WR_FM_DEEMPH__M 0xFFFF
#define AUD_DEM_WR_FM_DEEMPH__PRE 0x0
#define AUD_DEM_WR_FM_DEEMPH_50US 0x0
#define AUD_DEM_WR_FM_DEEMPH_75US 0x1
#define AUD_DEM_WR_FM_DEEMPH_OFF 0x3F
#define AUD_DEM_WR_FM_MATRIX__A 0x103006F
#define AUD_DEM_WR_FM_MATRIX__W 16
#define AUD_DEM_WR_FM_MATRIX__M 0xFFFF
#define AUD_DEM_WR_FM_MATRIX__PRE 0x0
#define AUD_DEM_WR_FM_MATRIX_NO_MATRIX 0x0
#define AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX 0x1
#define AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX 0x2
#define AUD_DEM_WR_FM_MATRIX_SOUND_A 0x3
#define AUD_DEM_WR_FM_MATRIX_SOUND_B 0x4
#define AUD_DSP_RD_FM_IDENT_VALUE__A 0x1040018
#define AUD_DSP_RD_FM_IDENT_VALUE__W 16
#define AUD_DSP_RD_FM_IDENT_VALUE__M 0xFFFF
#define AUD_DSP_RD_FM_IDENT_VALUE__PRE 0x0
#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B 8
#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W 8
#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M 0xFF00
#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE 0x0
#define AUD_DSP_RD_FM_DC_LEVEL_A__A 0x104001B
#define AUD_DSP_RD_FM_DC_LEVEL_A__W 16
#define AUD_DSP_RD_FM_DC_LEVEL_A__M 0xFFFF
#define AUD_DSP_RD_FM_DC_LEVEL_A__PRE 0x0
#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B 0
#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W 16
#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M 0xFFFF
#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE 0x0
#define AUD_DSP_RD_FM_DC_LEVEL_B__A 0x104001C
#define AUD_DSP_RD_FM_DC_LEVEL_B__W 16
#define AUD_DSP_RD_FM_DC_LEVEL_B__M 0xFFFF
#define AUD_DSP_RD_FM_DC_LEVEL_B__PRE 0x0
#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B 0
#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W 16
#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M 0xFFFF
#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE 0x0
#define AUD_DEM_WR_FM_DC_NOTCH_SW__A 0x1030017
#define AUD_DEM_WR_FM_DC_NOTCH_SW__W 16
#define AUD_DEM_WR_FM_DC_NOTCH_SW__M 0xFFFF
#define AUD_DEM_WR_FM_DC_NOTCH_SW__PRE 0x0
#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B 0
#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W 16
#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M 0xFFFF
#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE 0x0
#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON 0x0
#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF 0x3F
#define AUD_DSP_WR_SYNC_OUT__A 0x1050026
#define AUD_DSP_WR_SYNC_OUT__W 16
#define AUD_DSP_WR_SYNC_OUT__M 0xFFFF
#define AUD_DSP_WR_SYNC_OUT__PRE 0x0
#define AUD_DSP_WR_SYNC_OUT_OFF 0x0
#define AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS 0x1
#define AUD_XFP_DRAM_1K__A 0x1060000
#define AUD_XFP_DRAM_1K__W 16
#define AUD_XFP_DRAM_1K__M 0xFFFF
#define AUD_XFP_DRAM_1K__PRE 0x0
#define AUD_XFP_DRAM_1K_D__B 0
#define AUD_XFP_DRAM_1K_D__W 16
#define AUD_XFP_DRAM_1K_D__M 0xFFFF
#define AUD_XFP_DRAM_1K_D__PRE 0x0
#define AUD_XFP_PRAM_4K__A 0x1070000
#define AUD_XFP_PRAM_4K__W 16
#define AUD_XFP_PRAM_4K__M 0xFFFF
#define AUD_XFP_PRAM_4K__PRE 0x0
#define AUD_XFP_PRAM_4K_D__B 0
#define AUD_XFP_PRAM_4K_D__W 16
#define AUD_XFP_PRAM_4K_D__M 0xFFFF
#define AUD_XFP_PRAM_4K_D__PRE 0x0
#define AUD_XDFP_DRAM_1K__A 0x1080000
#define AUD_XDFP_DRAM_1K__W 16
#define AUD_XDFP_DRAM_1K__M 0xFFFF
#define AUD_XDFP_DRAM_1K__PRE 0x0
#define AUD_XDFP_DRAM_1K_D__B 0
#define AUD_XDFP_DRAM_1K_D__W 16
#define AUD_XDFP_DRAM_1K_D__M 0xFFFF
#define AUD_XDFP_DRAM_1K_D__PRE 0x0
#define AUD_XDFP_PRAM_4K__A 0x1090000
#define AUD_XDFP_PRAM_4K__W 16
#define AUD_XDFP_PRAM_4K__M 0xFFFF
#define AUD_XDFP_PRAM_4K__PRE 0x0
#define AUD_XDFP_PRAM_4K_D__B 0
#define AUD_XDFP_PRAM_4K_D__W 16
#define AUD_XDFP_PRAM_4K_D__M 0xFFFF
#define AUD_XDFP_PRAM_4K_D__PRE 0x0
#define FEC_COMM_EXEC__A 0x2400000
#define FEC_COMM_EXEC__W 2
#define FEC_COMM_EXEC__M 0x3
#define FEC_COMM_EXEC__PRE 0x0
#define FEC_COMM_EXEC_STOP 0x0
#define FEC_COMM_EXEC_ACTIVE 0x1
#define FEC_COMM_EXEC_HOLD 0x2
#define FEC_COMM_MB__A 0x2400002
#define FEC_COMM_MB__W 16
#define FEC_COMM_MB__M 0xFFFF
#define FEC_COMM_MB__PRE 0x0
#define FEC_COMM_INT_REQ__A 0x2400003
#define FEC_COMM_INT_REQ__W 16
#define FEC_COMM_INT_REQ__M 0xFFFF
#define FEC_COMM_INT_REQ__PRE 0x0
#define FEC_COMM_INT_REQ_OC_REQ__B 0
#define FEC_COMM_INT_REQ_OC_REQ__W 1
#define FEC_COMM_INT_REQ_OC_REQ__M 0x1
#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0
#define FEC_COMM_INT_REQ_RS_REQ__B 1
#define FEC_COMM_INT_REQ_RS_REQ__W 1
#define FEC_COMM_INT_REQ_RS_REQ__M 0x2
#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0
#define FEC_COMM_INT_REQ_DI_REQ__B 2
#define FEC_COMM_INT_REQ_DI_REQ__W 1
#define FEC_COMM_INT_REQ_DI_REQ__M 0x4
#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0
#define FEC_COMM_INT_STA__A 0x2400005
#define FEC_COMM_INT_STA__W 16
#define FEC_COMM_INT_STA__M 0xFFFF
#define FEC_COMM_INT_STA__PRE 0x0
#define FEC_COMM_INT_MSK__A 0x2400006
#define FEC_COMM_INT_MSK__W 16
#define FEC_COMM_INT_MSK__M 0xFFFF
#define FEC_COMM_INT_MSK__PRE 0x0
#define FEC_COMM_INT_STM__A 0x2400007
#define FEC_COMM_INT_STM__W 16
#define FEC_COMM_INT_STM__M 0xFFFF
#define FEC_COMM_INT_STM__PRE 0x0
#define FEC_TOP_COMM_EXEC__A 0x2410000
#define FEC_TOP_COMM_EXEC__W 2
#define FEC_TOP_COMM_EXEC__M 0x3
#define FEC_TOP_COMM_EXEC__PRE 0x0
#define FEC_TOP_COMM_EXEC_STOP 0x0
#define FEC_TOP_COMM_EXEC_ACTIVE 0x1
#define FEC_TOP_COMM_EXEC_HOLD 0x2
#define FEC_TOP_ANNEX__A 0x2410010
#define FEC_TOP_ANNEX__W 2
#define FEC_TOP_ANNEX__M 0x3
#define FEC_TOP_ANNEX__PRE 0x0
#define FEC_TOP_ANNEX_A 0x0
#define FEC_TOP_ANNEX_B 0x1
#define FEC_TOP_ANNEX_C 0x2
#define FEC_TOP_ANNEX_D 0x3
#define FEC_DI_COMM_EXEC__A 0x2420000
#define FEC_DI_COMM_EXEC__W 2
#define FEC_DI_COMM_EXEC__M 0x3
#define FEC_DI_COMM_EXEC__PRE 0x0
#define FEC_DI_COMM_EXEC_STOP 0x0
#define FEC_DI_COMM_EXEC_ACTIVE 0x1
#define FEC_DI_COMM_EXEC_HOLD 0x2
#define FEC_DI_COMM_MB__A 0x2420002
#define FEC_DI_COMM_MB__W 2
#define FEC_DI_COMM_MB__M 0x3
#define FEC_DI_COMM_MB__PRE 0x0
#define FEC_DI_COMM_MB_CTL__B 0
#define FEC_DI_COMM_MB_CTL__W 1
#define FEC_DI_COMM_MB_CTL__M 0x1
#define FEC_DI_COMM_MB_CTL__PRE 0x0
#define FEC_DI_COMM_MB_CTL_OFF 0x0
#define FEC_DI_COMM_MB_CTL_ON 0x1
#define FEC_DI_COMM_MB_OBS__B 1
#define FEC_DI_COMM_MB_OBS__W 1
#define FEC_DI_COMM_MB_OBS__M 0x2
#define FEC_DI_COMM_MB_OBS__PRE 0x0
#define FEC_DI_COMM_MB_OBS_OFF 0x0
#define FEC_DI_COMM_MB_OBS_ON 0x2
#define FEC_DI_COMM_INT_REQ__A 0x2420003
#define FEC_DI_COMM_INT_REQ__W 1
#define FEC_DI_COMM_INT_REQ__M 0x1
#define FEC_DI_COMM_INT_REQ__PRE 0x0
#define FEC_DI_COMM_INT_STA__A 0x2420005
#define FEC_DI_COMM_INT_STA__W 2
#define FEC_DI_COMM_INT_STA__M 0x3
#define FEC_DI_COMM_INT_STA__PRE 0x0
#define FEC_DI_COMM_INT_STA_STAT_INT__B 0
#define FEC_DI_COMM_INT_STA_STAT_INT__W 1
#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1
#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0
#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1
#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1
#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2
#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0
#define FEC_DI_COMM_INT_MSK__A 0x2420006
#define FEC_DI_COMM_INT_MSK__W 2
#define FEC_DI_COMM_INT_MSK__M 0x3
#define FEC_DI_COMM_INT_MSK__PRE 0x0
#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0
#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1
#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1
#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0
#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1
#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1
#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2
#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0
#define FEC_DI_COMM_INT_STM__A 0x2420007
#define FEC_DI_COMM_INT_STM__W 2
#define FEC_DI_COMM_INT_STM__M 0x3
#define FEC_DI_COMM_INT_STM__PRE 0x0
#define FEC_DI_COMM_INT_STM_STAT_INT__B 0
#define FEC_DI_COMM_INT_STM_STAT_INT__W 1
#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1
#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0
#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1
#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1
#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2
#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0
#define FEC_DI_STATUS__A 0x2420010
#define FEC_DI_STATUS__W 1
#define FEC_DI_STATUS__M 0x1
#define FEC_DI_STATUS__PRE 0x0
#define FEC_DI_MODE__A 0x2420011
#define FEC_DI_MODE__W 3
#define FEC_DI_MODE__M 0x7
#define FEC_DI_MODE__PRE 0x0
#define FEC_DI_MODE_NO_SYNC__B 0
#define FEC_DI_MODE_NO_SYNC__W 1
#define FEC_DI_MODE_NO_SYNC__M 0x1
#define FEC_DI_MODE_NO_SYNC__PRE 0x0
#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1
#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1
#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2
#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0
#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2
#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1
#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4
#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0
#define FEC_DI_CONTROL_WORD__A 0x2420012
#define FEC_DI_CONTROL_WORD__W 4
#define FEC_DI_CONTROL_WORD__M 0xF
#define FEC_DI_CONTROL_WORD__PRE 0x0
#define FEC_DI_RESTART__A 0x2420013
#define FEC_DI_RESTART__W 1
#define FEC_DI_RESTART__M 0x1
#define FEC_DI_RESTART__PRE 0x0
#define FEC_DI_TIMEOUT_LO__A 0x2420014
#define FEC_DI_TIMEOUT_LO__W 16
#define FEC_DI_TIMEOUT_LO__M 0xFFFF
#define FEC_DI_TIMEOUT_LO__PRE 0x0
#define FEC_DI_TIMEOUT_HI__A 0x2420015
#define FEC_DI_TIMEOUT_HI__W 8
#define FEC_DI_TIMEOUT_HI__M 0xFF
#define FEC_DI_TIMEOUT_HI__PRE 0xA
#define FEC_RS_COMM_EXEC__A 0x2430000
#define FEC_RS_COMM_EXEC__W 2
#define FEC_RS_COMM_EXEC__M 0x3
#define FEC_RS_COMM_EXEC__PRE 0x0
#define FEC_RS_COMM_EXEC_STOP 0x0
#define FEC_RS_COMM_EXEC_ACTIVE 0x1
#define FEC_RS_COMM_EXEC_HOLD 0x2
#define FEC_RS_COMM_MB__A 0x2430002
#define FEC_RS_COMM_MB__W 2
#define FEC_RS_COMM_MB__M 0x3
#define FEC_RS_COMM_MB__PRE 0x0
#define FEC_RS_COMM_MB_CTL__B 0
#define FEC_RS_COMM_MB_CTL__W 1
#define FEC_RS_COMM_MB_CTL__M 0x1
#define FEC_RS_COMM_MB_CTL__PRE 0x0
#define FEC_RS_COMM_MB_CTL_OFF 0x0
#define FEC_RS_COMM_MB_CTL_ON 0x1
#define FEC_RS_COMM_MB_OBS__B 1
#define FEC_RS_COMM_MB_OBS__W 1
#define FEC_RS_COMM_MB_OBS__M 0x2
#define FEC_RS_COMM_MB_OBS__PRE 0x0
#define FEC_RS_COMM_MB_OBS_OFF 0x0
#define FEC_RS_COMM_MB_OBS_ON 0x2
#define FEC_RS_COMM_INT_REQ__A 0x2430003
#define FEC_RS_COMM_INT_REQ__W 1
#define FEC_RS_COMM_INT_REQ__M 0x1
#define FEC_RS_COMM_INT_REQ__PRE 0x0
#define FEC_RS_COMM_INT_STA__A 0x2430005
#define FEC_RS_COMM_INT_STA__W 2
#define FEC_RS_COMM_INT_STA__M 0x3
#define FEC_RS_COMM_INT_STA__PRE 0x0
#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0
#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1
#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1
#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0
#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1
#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1
#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2
#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0
#define FEC_RS_COMM_INT_MSK__A 0x2430006
#define FEC_RS_COMM_INT_MSK__W 2
#define FEC_RS_COMM_INT_MSK__M 0x3
#define FEC_RS_COMM_INT_MSK__PRE 0x0
#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0
#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1
#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1
#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0
#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1
#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1
#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2
#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0
#define FEC_RS_COMM_INT_STM__A 0x2430007
#define FEC_RS_COMM_INT_STM__W 2
#define FEC_RS_COMM_INT_STM__M 0x3
#define FEC_RS_COMM_INT_STM__PRE 0x0
#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0
#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1
#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1
#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0
#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1
#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1
#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2
#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0
#define FEC_RS_STATUS__A 0x2430010
#define FEC_RS_STATUS__W 1
#define FEC_RS_STATUS__M 0x1
#define FEC_RS_STATUS__PRE 0x0
#define FEC_RS_MODE__A 0x2430011
#define FEC_RS_MODE__W 1
#define FEC_RS_MODE__M 0x1
#define FEC_RS_MODE__PRE 0x0
#define FEC_RS_MODE_BYPASS__B 0
#define FEC_RS_MODE_BYPASS__W 1
#define FEC_RS_MODE_BYPASS__M 0x1
#define FEC_RS_MODE_BYPASS__PRE 0x0
#define FEC_RS_MEASUREMENT_PERIOD__A 0x2430012
#define FEC_RS_MEASUREMENT_PERIOD__W 16
#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF
#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x1171
#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0
#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16
#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF
#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x1171
#define FEC_RS_MEASUREMENT_PRESCALE__A 0x2430013
#define FEC_RS_MEASUREMENT_PRESCALE__W 16
#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF
#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1
#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0
#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16
#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF
#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1
#define FEC_RS_NR_BIT_ERRORS__A 0x2430014
#define FEC_RS_NR_BIT_ERRORS__W 16
#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF
#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF
#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0
#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12
#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF
#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF
#define FEC_RS_NR_BIT_ERRORS_EXP__B 12
#define FEC_RS_NR_BIT_ERRORS_EXP__W 4
#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000
#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000
#define FEC_RS_NR_SYMBOL_ERRORS__A 0x2430015
#define FEC_RS_NR_SYMBOL_ERRORS__W 16
#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF
#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF
#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0
#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12
#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF
#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF
#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12
#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4
#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000
#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000
#define FEC_RS_NR_PACKET_ERRORS__A 0x2430016
#define FEC_RS_NR_PACKET_ERRORS__W 16
#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF
#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF
#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0
#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12
#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF
#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF
#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12
#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4
#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000
#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000
#define FEC_RS_NR_FAILURES__A 0x2430017
#define FEC_RS_NR_FAILURES__W 16
#define FEC_RS_NR_FAILURES__M 0xFFFF
#define FEC_RS_NR_FAILURES__PRE 0x0
#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0
#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12
#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF
#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0
#define FEC_RS_NR_FAILURES_EXP__B 12
#define FEC_RS_NR_FAILURES_EXP__W 4
#define FEC_RS_NR_FAILURES_EXP__M 0xF000
#define FEC_RS_NR_FAILURES_EXP__PRE 0x0
#define FEC_OC_COMM_EXEC__A 0x2440000
#define FEC_OC_COMM_EXEC__W 2
#define FEC_OC_COMM_EXEC__M 0x3
#define FEC_OC_COMM_EXEC__PRE 0x0
#define FEC_OC_COMM_EXEC_STOP 0x0
#define FEC_OC_COMM_EXEC_ACTIVE 0x1
#define FEC_OC_COMM_EXEC_HOLD 0x2
#define FEC_OC_COMM_MB__A 0x2440002
#define FEC_OC_COMM_MB__W 2
#define FEC_OC_COMM_MB__M 0x3
#define FEC_OC_COMM_MB__PRE 0x0
#define FEC_OC_COMM_MB_CTL__B 0
#define FEC_OC_COMM_MB_CTL__W 1
#define FEC_OC_COMM_MB_CTL__M 0x1
#define FEC_OC_COMM_MB_CTL__PRE 0x0
#define FEC_OC_COMM_MB_CTL_OFF 0x0
#define FEC_OC_COMM_MB_CTL_ON 0x1
#define FEC_OC_COMM_MB_OBS__B 1
#define FEC_OC_COMM_MB_OBS__W 1
#define FEC_OC_COMM_MB_OBS__M 0x2
#define FEC_OC_COMM_MB_OBS__PRE 0x0
#define FEC_OC_COMM_MB_OBS_OFF 0x0
#define FEC_OC_COMM_MB_OBS_ON 0x2
#define FEC_OC_COMM_INT_REQ__A 0x2440003
#define FEC_OC_COMM_INT_REQ__W 1
#define FEC_OC_COMM_INT_REQ__M 0x1
#define FEC_OC_COMM_INT_REQ__PRE 0x0
#define FEC_OC_COMM_INT_STA__A 0x2440005
#define FEC_OC_COMM_INT_STA__W 8
#define FEC_OC_COMM_INT_STA__M 0xFF
#define FEC_OC_COMM_INT_STA__PRE 0x0
#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0
#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1
#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1
#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0
#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1
#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1
#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2
#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0
#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2
#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1
#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4
#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0
#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3
#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1
#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8
#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0
#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4
#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1
#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10
#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0
#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5
#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1
#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20
#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0
#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6
#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1
#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40
#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0
#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7
#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1
#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80
#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0
#define FEC_OC_COMM_INT_MSK__A 0x2440006
#define FEC_OC_COMM_INT_MSK__W 8
#define FEC_OC_COMM_INT_MSK__M 0xFF
#define FEC_OC_COMM_INT_MSK__PRE 0x0
#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0
#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1
#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1
#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0
#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1
#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1
#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2
#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0
#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2
#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1
#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4
#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0
#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3
#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1
#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8
#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0
#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4
#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1
#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10
#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0
#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5
#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1
#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20
#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0
#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6
#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1
#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40
#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0
#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7
#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1
#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80
#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0
#define FEC_OC_COMM_INT_STM__A 0x2440007
#define FEC_OC_COMM_INT_STM__W 8
#define FEC_OC_COMM_INT_STM__M 0xFF
#define FEC_OC_COMM_INT_STM__PRE 0x0
#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0
#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1
#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1
#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0
#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1
#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1
#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2
#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0
#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2
#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1
#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4
#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0
#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3
#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1
#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8
#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0
#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4
#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1
#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10
#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0
#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5
#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1
#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20
#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0
#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6
#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1
#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40
#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0
#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7
#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1
#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80
#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0
#define FEC_OC_STATUS__A 0x2440010
#define FEC_OC_STATUS__W 5
#define FEC_OC_STATUS__M 0x1F
#define FEC_OC_STATUS__PRE 0x0
#define FEC_OC_STATUS_DPR_STATUS__B 0
#define FEC_OC_STATUS_DPR_STATUS__W 1
#define FEC_OC_STATUS_DPR_STATUS__M 0x1
#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0
#define FEC_OC_STATUS_SNC_STATUS__B 1
#define FEC_OC_STATUS_SNC_STATUS__W 2
#define FEC_OC_STATUS_SNC_STATUS__M 0x6
#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0
#define FEC_OC_STATUS_FIFO_FULL__B 3
#define FEC_OC_STATUS_FIFO_FULL__W 1
#define FEC_OC_STATUS_FIFO_FULL__M 0x8
#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0
#define FEC_OC_STATUS_FIFO_EMPTY__B 4
#define FEC_OC_STATUS_FIFO_EMPTY__W 1
#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10
#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0
#define FEC_OC_MODE__A 0x2440011
#define FEC_OC_MODE__W 4
#define FEC_OC_MODE__M 0xF
#define FEC_OC_MODE__PRE 0x0
#define FEC_OC_MODE_PARITY__B 0
#define FEC_OC_MODE_PARITY__W 1
#define FEC_OC_MODE_PARITY__M 0x1
#define FEC_OC_MODE_PARITY__PRE 0x0
#define FEC_OC_MODE_TRANSPARENT__B 1
#define FEC_OC_MODE_TRANSPARENT__W 1
#define FEC_OC_MODE_TRANSPARENT__M 0x2
#define FEC_OC_MODE_TRANSPARENT__PRE 0x0
#define FEC_OC_MODE_CLEAR__B 2
#define FEC_OC_MODE_CLEAR__W 1
#define FEC_OC_MODE_CLEAR__M 0x4
#define FEC_OC_MODE_CLEAR__PRE 0x0
#define FEC_OC_MODE_RETAIN_FRAMING__B 3
#define FEC_OC_MODE_RETAIN_FRAMING__W 1
#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8
#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0
#define FEC_OC_DPR_MODE__A 0x2440012
#define FEC_OC_DPR_MODE__W 2
#define FEC_OC_DPR_MODE__M 0x3
#define FEC_OC_DPR_MODE__PRE 0x0
#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0
#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1
#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1
#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0
#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1
#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1
#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2
#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0
#define FEC_OC_DPR_UNLOCK__A 0x2440013
#define FEC_OC_DPR_UNLOCK__W 1
#define FEC_OC_DPR_UNLOCK__M 0x1
#define FEC_OC_DPR_UNLOCK__PRE 0x0
#define FEC_OC_DTO_MODE__A 0x2440014
#define FEC_OC_DTO_MODE__W 3
#define FEC_OC_DTO_MODE__M 0x7
#define FEC_OC_DTO_MODE__PRE 0x0
#define FEC_OC_DTO_MODE_DYNAMIC__B 0
#define FEC_OC_DTO_MODE_DYNAMIC__W 1
#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1
#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0
#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1
#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1
#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2
#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0
#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2
#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1
#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4
#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0
#define FEC_OC_DTO_PERIOD__A 0x2440015
#define FEC_OC_DTO_PERIOD__W 8
#define FEC_OC_DTO_PERIOD__M 0xFF
#define FEC_OC_DTO_PERIOD__PRE 0x0
#define FEC_OC_DTO_RATE_LO__A 0x2440016
#define FEC_OC_DTO_RATE_LO__W 16
#define FEC_OC_DTO_RATE_LO__M 0xFFFF
#define FEC_OC_DTO_RATE_LO__PRE 0x0
#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0
#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16
#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF
#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0
#define FEC_OC_DTO_RATE_HI__A 0x2440017
#define FEC_OC_DTO_RATE_HI__W 10
#define FEC_OC_DTO_RATE_HI__M 0x3FF
#define FEC_OC_DTO_RATE_HI__PRE 0xC0
#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0
#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10
#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF
#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0
#define FEC_OC_DTO_BURST_LEN__A 0x2440018
#define FEC_OC_DTO_BURST_LEN__W 8
#define FEC_OC_DTO_BURST_LEN__M 0xFF
#define FEC_OC_DTO_BURST_LEN__PRE 0xBC
#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0
#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8
#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF
#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC
#define FEC_OC_FCT_MODE__A 0x244001A
#define FEC_OC_FCT_MODE__W 2
#define FEC_OC_FCT_MODE__M 0x3
#define FEC_OC_FCT_MODE__PRE 0x0
#define FEC_OC_FCT_MODE_RAT_ENA__B 0
#define FEC_OC_FCT_MODE_RAT_ENA__W 1
#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1
#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0
#define FEC_OC_FCT_MODE_VIRT_ENA__B 1
#define FEC_OC_FCT_MODE_VIRT_ENA__W 1
#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2
#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0
#define FEC_OC_FCT_USAGE__A 0x244001B
#define FEC_OC_FCT_USAGE__W 3
#define FEC_OC_FCT_USAGE__M 0x7
#define FEC_OC_FCT_USAGE__PRE 0x2
#define FEC_OC_FCT_USAGE_USAGE__B 0
#define FEC_OC_FCT_USAGE_USAGE__W 3
#define FEC_OC_FCT_USAGE_USAGE__M 0x7
#define FEC_OC_FCT_USAGE_USAGE__PRE 0x2
#define FEC_OC_FCT_OCCUPATION__A 0x244001C
#define FEC_OC_FCT_OCCUPATION__W 12
#define FEC_OC_FCT_OCCUPATION__M 0xFFF
#define FEC_OC_FCT_OCCUPATION__PRE 0x0
#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0
#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12
#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF
#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0
#define FEC_OC_TMD_MODE__A 0x244001E
#define FEC_OC_TMD_MODE__W 3
#define FEC_OC_TMD_MODE__M 0x7
#define FEC_OC_TMD_MODE__PRE 0x4
#define FEC_OC_TMD_MODE_MODE__B 0
#define FEC_OC_TMD_MODE_MODE__W 3
#define FEC_OC_TMD_MODE_MODE__M 0x7
#define FEC_OC_TMD_MODE_MODE__PRE 0x4
#define FEC_OC_TMD_COUNT__A 0x244001F
#define FEC_OC_TMD_COUNT__W 10
#define FEC_OC_TMD_COUNT__M 0x3FF
#define FEC_OC_TMD_COUNT__PRE 0x1F4
#define FEC_OC_TMD_COUNT_COUNT__B 0
#define FEC_OC_TMD_COUNT_COUNT__W 10
#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF
#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4
#define FEC_OC_TMD_HI_MARGIN__A 0x2440020
#define FEC_OC_TMD_HI_MARGIN__W 11
#define FEC_OC_TMD_HI_MARGIN__M 0x7FF
#define FEC_OC_TMD_HI_MARGIN__PRE 0x200
#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0
#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11
#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF
#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x200
#define FEC_OC_TMD_LO_MARGIN__A 0x2440021
#define FEC_OC_TMD_LO_MARGIN__W 11
#define FEC_OC_TMD_LO_MARGIN__M 0x7FF
#define FEC_OC_TMD_LO_MARGIN__PRE 0x100
#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0
#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11
#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF
#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x100
#define FEC_OC_TMD_CTL_UPD_RATE__A 0x2440022
#define FEC_OC_TMD_CTL_UPD_RATE__W 4
#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF
#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1
#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0
#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4
#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF
#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1
#define FEC_OC_TMD_INT_UPD_RATE__A 0x2440023
#define FEC_OC_TMD_INT_UPD_RATE__W 4
#define FEC_OC_TMD_INT_UPD_RATE__M 0xF
#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4
#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0
#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4
#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF
#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4
#define FEC_OC_AVR_PARM_A__A 0x2440026
#define FEC_OC_AVR_PARM_A__W 4
#define FEC_OC_AVR_PARM_A__M 0xF
#define FEC_OC_AVR_PARM_A__PRE 0x6
#define FEC_OC_AVR_PARM_A_PARM__B 0
#define FEC_OC_AVR_PARM_A_PARM__W 4
#define FEC_OC_AVR_PARM_A_PARM__M 0xF
#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6
#define FEC_OC_AVR_PARM_B__A 0x2440027
#define FEC_OC_AVR_PARM_B__W 4
#define FEC_OC_AVR_PARM_B__M 0xF
#define FEC_OC_AVR_PARM_B__PRE 0x4
#define FEC_OC_AVR_PARM_B_PARM__B 0
#define FEC_OC_AVR_PARM_B_PARM__W 4
#define FEC_OC_AVR_PARM_B_PARM__M 0xF
#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4
#define FEC_OC_AVR_AVG_LO__A 0x2440028
#define FEC_OC_AVR_AVG_LO__W 16
#define FEC_OC_AVR_AVG_LO__M 0xFFFF
#define FEC_OC_AVR_AVG_LO__PRE 0x0
#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0
#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16
#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF
#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0
#define FEC_OC_AVR_AVG_HI__A 0x2440029
#define FEC_OC_AVR_AVG_HI__W 6
#define FEC_OC_AVR_AVG_HI__M 0x3F
#define FEC_OC_AVR_AVG_HI__PRE 0x0
#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0
#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6
#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F
#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0
#define FEC_OC_RCN_MODE__A 0x244002C
#define FEC_OC_RCN_MODE__W 5
#define FEC_OC_RCN_MODE__M 0x1F
#define FEC_OC_RCN_MODE__PRE 0x1F
#define FEC_OC_RCN_MODE_MODE__B 0
#define FEC_OC_RCN_MODE_MODE__W 5
#define FEC_OC_RCN_MODE_MODE__M 0x1F
#define FEC_OC_RCN_MODE_MODE__PRE 0x1F
#define FEC_OC_RCN_OCC_SETTLE__A 0x244002D
#define FEC_OC_RCN_OCC_SETTLE__W 11
#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF
#define FEC_OC_RCN_OCC_SETTLE__PRE 0x180
#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0
#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11
#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF
#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x180
#define FEC_OC_RCN_GAIN__A 0x244002E
#define FEC_OC_RCN_GAIN__W 4
#define FEC_OC_RCN_GAIN__M 0xF
#define FEC_OC_RCN_GAIN__PRE 0xC
#define FEC_OC_RCN_GAIN_GAIN__B 0
#define FEC_OC_RCN_GAIN_GAIN__W 4
#define FEC_OC_RCN_GAIN_GAIN__M 0xF
#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC
#define FEC_OC_RCN_CTL_RATE_LO__A 0x2440030
#define FEC_OC_RCN_CTL_RATE_LO__W 16
#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF
#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0
#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0
#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16
#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF
#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0
#define FEC_OC_RCN_CTL_RATE_HI__A 0x2440031
#define FEC_OC_RCN_CTL_RATE_HI__W 8
#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF
#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0
#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0
#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8
#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF
#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0
#define FEC_OC_RCN_CTL_STEP_LO__A 0x2440032
#define FEC_OC_RCN_CTL_STEP_LO__W 16
#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF
#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0
#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0
#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16
#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF
#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0
#define FEC_OC_RCN_CTL_STEP_HI__A 0x2440033
#define FEC_OC_RCN_CTL_STEP_HI__W 8
#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF
#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8
#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0
#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8
#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF
#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8
#define FEC_OC_RCN_DTO_OFS_LO__A 0x2440034
#define FEC_OC_RCN_DTO_OFS_LO__W 16
#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF
#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0
#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0
#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16
#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF
#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0
#define FEC_OC_RCN_DTO_OFS_HI__A 0x2440035
#define FEC_OC_RCN_DTO_OFS_HI__W 8
#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF
#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0
#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0
#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8
#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF
#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0
#define FEC_OC_RCN_DTO_RATE_LO__A 0x2440036
#define FEC_OC_RCN_DTO_RATE_LO__W 16
#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF
#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0
#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0
#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16
#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF
#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0
#define FEC_OC_RCN_DTO_RATE_HI__A 0x2440037
#define FEC_OC_RCN_DTO_RATE_HI__W 8
#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF
#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0
#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0
#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8
#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF
#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0
#define FEC_OC_RCN_RATE_CLIP_LO__A 0x2440038
#define FEC_OC_RCN_RATE_CLIP_LO__W 16
#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF
#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0
#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0
#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16
#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF
#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0
#define FEC_OC_RCN_RATE_CLIP_HI__A 0x2440039
#define FEC_OC_RCN_RATE_CLIP_HI__W 8
#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF
#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0
#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0
#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8
#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF
#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0
#define FEC_OC_RCN_DYN_RATE_LO__A 0x244003A
#define FEC_OC_RCN_DYN_RATE_LO__W 16
#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF
#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0
#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0
#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16
#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF
#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0
#define FEC_OC_RCN_DYN_RATE_HI__A 0x244003B
#define FEC_OC_RCN_DYN_RATE_HI__W 8
#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF
#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0
#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0
#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8
#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF
#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0
#define FEC_OC_SNC_MODE__A 0x2440040
#define FEC_OC_SNC_MODE__W 4
#define FEC_OC_SNC_MODE__M 0xF
#define FEC_OC_SNC_MODE__PRE 0x0
#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0
#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1
#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1
#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0
#define FEC_OC_SNC_MODE_ERROR_CTL__B 1
#define FEC_OC_SNC_MODE_ERROR_CTL__W 2
#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6
#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0
#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3
#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1
#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8
#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0
#define FEC_OC_SNC_LWM__A 0x2440041
#define FEC_OC_SNC_LWM__W 4
#define FEC_OC_SNC_LWM__M 0xF
#define FEC_OC_SNC_LWM__PRE 0x3
#define FEC_OC_SNC_LWM_MARK__B 0
#define FEC_OC_SNC_LWM_MARK__W 4
#define FEC_OC_SNC_LWM_MARK__M 0xF
#define FEC_OC_SNC_LWM_MARK__PRE 0x3
#define FEC_OC_SNC_HWM__A 0x2440042
#define FEC_OC_SNC_HWM__W 4
#define FEC_OC_SNC_HWM__M 0xF
#define FEC_OC_SNC_HWM__PRE 0x5
#define FEC_OC_SNC_HWM_MARK__B 0
#define FEC_OC_SNC_HWM_MARK__W 4
#define FEC_OC_SNC_HWM_MARK__M 0xF
#define FEC_OC_SNC_HWM_MARK__PRE 0x5
#define FEC_OC_SNC_UNLOCK__A 0x2440043
#define FEC_OC_SNC_UNLOCK__W 1
#define FEC_OC_SNC_UNLOCK__M 0x1
#define FEC_OC_SNC_UNLOCK__PRE 0x0
#define FEC_OC_SNC_UNLOCK_RESTART__B 0
#define FEC_OC_SNC_UNLOCK_RESTART__W 1
#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1
#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0
#define FEC_OC_SNC_LOCK_COUNT__A 0x2440044
#define FEC_OC_SNC_LOCK_COUNT__W 12
#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF
#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0
#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0
#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12
#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF
#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0
#define FEC_OC_SNC_FAIL_COUNT__A 0x2440045
#define FEC_OC_SNC_FAIL_COUNT__W 12
#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF
#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0
#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0
#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12
#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF
#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0
#define FEC_OC_SNC_FAIL_PERIOD__A 0x2440046
#define FEC_OC_SNC_FAIL_PERIOD__W 16
#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF
#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171
#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0
#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16
#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF
#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171
#define FEC_OC_EMS_MODE__A 0x2440047
#define FEC_OC_EMS_MODE__W 2
#define FEC_OC_EMS_MODE__M 0x3
#define FEC_OC_EMS_MODE__PRE 0x0
#define FEC_OC_EMS_MODE_MODE__B 0
#define FEC_OC_EMS_MODE_MODE__W 2
#define FEC_OC_EMS_MODE_MODE__M 0x3
#define FEC_OC_EMS_MODE_MODE__PRE 0x0
#define FEC_OC_IPR_MODE__A 0x2440048
#define FEC_OC_IPR_MODE__W 12
#define FEC_OC_IPR_MODE__M 0xFFF
#define FEC_OC_IPR_MODE__PRE 0x0
#define FEC_OC_IPR_MODE_SERIAL__B 0
#define FEC_OC_IPR_MODE_SERIAL__W 1
#define FEC_OC_IPR_MODE_SERIAL__M 0x1
#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0
#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1
#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1
#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2
#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0
#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2
#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1
#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4
#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0
#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3
#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1
#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8
#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0
#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4
#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1
#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10
#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0
#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5
#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1
#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20
#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0
#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6
#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1
#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40
#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0
#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7
#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1
#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80
#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0
#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8
#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1
#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100
#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0
#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9
#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1
#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200
#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0
#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10
#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1
#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400
#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0
#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11
#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1
#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800
#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0
#define FEC_OC_IPR_INVERT__A 0x2440049
#define FEC_OC_IPR_INVERT__W 12
#define FEC_OC_IPR_INVERT__M 0xFFF
#define FEC_OC_IPR_INVERT__PRE 0x0
#define FEC_OC_IPR_INVERT_MD0__B 0
#define FEC_OC_IPR_INVERT_MD0__W 1
#define FEC_OC_IPR_INVERT_MD0__M 0x1
#define FEC_OC_IPR_INVERT_MD0__PRE 0x0
#define FEC_OC_IPR_INVERT_MD1__B 1
#define FEC_OC_IPR_INVERT_MD1__W 1
#define FEC_OC_IPR_INVERT_MD1__M 0x2
#define FEC_OC_IPR_INVERT_MD1__PRE 0x0
#define FEC_OC_IPR_INVERT_MD2__B 2
#define FEC_OC_IPR_INVERT_MD2__W 1
#define FEC_OC_IPR_INVERT_MD2__M 0x4
#define FEC_OC_IPR_INVERT_MD2__PRE 0x0
#define FEC_OC_IPR_INVERT_MD3__B 3
#define FEC_OC_IPR_INVERT_MD3__W 1
#define FEC_OC_IPR_INVERT_MD3__M 0x8
#define FEC_OC_IPR_INVERT_MD3__PRE 0x0
#define FEC_OC_IPR_INVERT_MD4__B 4
#define FEC_OC_IPR_INVERT_MD4__W 1
#define FEC_OC_IPR_INVERT_MD4__M 0x10
#define FEC_OC_IPR_INVERT_MD4__PRE 0x0
#define FEC_OC_IPR_INVERT_MD5__B 5
#define FEC_OC_IPR_INVERT_MD5__W 1
#define FEC_OC_IPR_INVERT_MD5__M 0x20
#define FEC_OC_IPR_INVERT_MD5__PRE 0x0
#define FEC_OC_IPR_INVERT_MD6__B 6
#define FEC_OC_IPR_INVERT_MD6__W 1
#define FEC_OC_IPR_INVERT_MD6__M 0x40
#define FEC_OC_IPR_INVERT_MD6__PRE 0x0
#define FEC_OC_IPR_INVERT_MD7__B 7
#define FEC_OC_IPR_INVERT_MD7__W 1
#define FEC_OC_IPR_INVERT_MD7__M 0x80
#define FEC_OC_IPR_INVERT_MD7__PRE 0x0
#define FEC_OC_IPR_INVERT_MERR__B 8
#define FEC_OC_IPR_INVERT_MERR__W 1
#define FEC_OC_IPR_INVERT_MERR__M 0x100
#define FEC_OC_IPR_INVERT_MERR__PRE 0x0
#define FEC_OC_IPR_INVERT_MSTRT__B 9
#define FEC_OC_IPR_INVERT_MSTRT__W 1
#define FEC_OC_IPR_INVERT_MSTRT__M 0x200
#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0
#define FEC_OC_IPR_INVERT_MVAL__B 10
#define FEC_OC_IPR_INVERT_MVAL__W 1
#define FEC_OC_IPR_INVERT_MVAL__M 0x400
#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0
#define FEC_OC_IPR_INVERT_MCLK__B 11
#define FEC_OC_IPR_INVERT_MCLK__W 1
#define FEC_OC_IPR_INVERT_MCLK__M 0x800
#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0
#define FEC_OC_OCR_MODE__A 0x2440050
#define FEC_OC_OCR_MODE__W 4
#define FEC_OC_OCR_MODE__M 0xF
#define FEC_OC_OCR_MODE__PRE 0x0
#define FEC_OC_OCR_MODE_MB_SELECT__B 0
#define FEC_OC_OCR_MODE_MB_SELECT__W 1
#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1
#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0
#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1
#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1
#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2
#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0
#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2
#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1
#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4
#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0
#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3
#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1
#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8
#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0
#define FEC_OC_OCR_RATE__A 0x2440051
#define FEC_OC_OCR_RATE__W 4
#define FEC_OC_OCR_RATE__M 0xF
#define FEC_OC_OCR_RATE__PRE 0x0
#define FEC_OC_OCR_RATE_RATE__B 0
#define FEC_OC_OCR_RATE_RATE__W 4
#define FEC_OC_OCR_RATE_RATE__M 0xF
#define FEC_OC_OCR_RATE_RATE__PRE 0x0
#define FEC_OC_OCR_INVERT__A 0x2440052
#define FEC_OC_OCR_INVERT__W 12
#define FEC_OC_OCR_INVERT__M 0xFFF
#define FEC_OC_OCR_INVERT__PRE 0x800
#define FEC_OC_OCR_INVERT_INVERT__B 0
#define FEC_OC_OCR_INVERT_INVERT__W 12
#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF
#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800
#define FEC_OC_OCR_GRAB_COUNT__A 0x2440053
#define FEC_OC_OCR_GRAB_COUNT__W 16
#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF
#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0
#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0
#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16
#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF
#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0
#define FEC_OC_OCR_GRAB_SYNC__A 0x2440054
#define FEC_OC_OCR_GRAB_SYNC__W 8
#define FEC_OC_OCR_GRAB_SYNC__M 0xFF
#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0
#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0
#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3
#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7
#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0
#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3
#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4
#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78
#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0
#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7
#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1
#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80
#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0
#define FEC_OC_OCR_GRAB_RD0__A 0x2440055
#define FEC_OC_OCR_GRAB_RD0__W 10
#define FEC_OC_OCR_GRAB_RD0__M 0x3FF
#define FEC_OC_OCR_GRAB_RD0__PRE 0x0
#define FEC_OC_OCR_GRAB_RD0_DATA__B 0
#define FEC_OC_OCR_GRAB_RD0_DATA__W 10
#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF
#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0
#define FEC_OC_OCR_GRAB_RD1__A 0x2440056
#define FEC_OC_OCR_GRAB_RD1__W 10
#define FEC_OC_OCR_GRAB_RD1__M 0x3FF
#define FEC_OC_OCR_GRAB_RD1__PRE 0x0
#define FEC_OC_OCR_GRAB_RD1_DATA__B 0
#define FEC_OC_OCR_GRAB_RD1_DATA__W 10
#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF
#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0
#define FEC_OC_OCR_GRAB_RD2__A 0x2440057
#define FEC_OC_OCR_GRAB_RD2__W 10
#define FEC_OC_OCR_GRAB_RD2__M 0x3FF
#define FEC_OC_OCR_GRAB_RD2__PRE 0x0
#define FEC_OC_OCR_GRAB_RD2_DATA__B 0
#define FEC_OC_OCR_GRAB_RD2_DATA__W 10
#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF
#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0
#define FEC_OC_OCR_GRAB_RD3__A 0x2440058
#define FEC_OC_OCR_GRAB_RD3__W 10
#define FEC_OC_OCR_GRAB_RD3__M 0x3FF
#define FEC_OC_OCR_GRAB_RD3__PRE 0x0
#define FEC_OC_OCR_GRAB_RD3_DATA__B 0
#define FEC_OC_OCR_GRAB_RD3_DATA__W 10
#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF
#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0
#define FEC_OC_OCR_GRAB_RD4__A 0x2440059
#define FEC_OC_OCR_GRAB_RD4__W 10
#define FEC_OC_OCR_GRAB_RD4__M 0x3FF
#define FEC_OC_OCR_GRAB_RD4__PRE 0x0
#define FEC_OC_OCR_GRAB_RD4_DATA__B 0
#define FEC_OC_OCR_GRAB_RD4_DATA__W 10
#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF
#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0
#define FEC_OC_OCR_GRAB_RD5__A 0x244005A
#define FEC_OC_OCR_GRAB_RD5__W 10
#define FEC_OC_OCR_GRAB_RD5__M 0x3FF
#define FEC_OC_OCR_GRAB_RD5__PRE 0x0
#define FEC_OC_OCR_GRAB_RD5_DATA__B 0
#define FEC_OC_OCR_GRAB_RD5_DATA__W 10
#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF
#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0
#define FEC_DI_RAM__A 0x2450000
#define FEC_RS_RAM__A 0x2460000
#define FEC_OC_RAM__A 0x2470000
#define IQM_COMM_EXEC__A 0x1800000
#define IQM_COMM_EXEC__W 2
#define IQM_COMM_EXEC__M 0x3
#define IQM_COMM_EXEC__PRE 0x0
#define IQM_COMM_EXEC_STOP 0x0
#define IQM_COMM_EXEC_ACTIVE 0x1
#define IQM_COMM_EXEC_HOLD 0x2
#define IQM_COMM_MB__A 0x1800002
#define IQM_COMM_MB__W 16
#define IQM_COMM_MB__M 0xFFFF
#define IQM_COMM_MB__PRE 0x0
#define IQM_COMM_INT_REQ__A 0x1800003
#define IQM_COMM_INT_REQ__W 2
#define IQM_COMM_INT_REQ__M 0x3
#define IQM_COMM_INT_REQ__PRE 0x0
#define IQM_COMM_INT_REQ_AF_REQ__B 0
#define IQM_COMM_INT_REQ_AF_REQ__W 1
#define IQM_COMM_INT_REQ_AF_REQ__M 0x1
#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0
#define IQM_COMM_INT_REQ_CF_REQ__B 1
#define IQM_COMM_INT_REQ_CF_REQ__W 1
#define IQM_COMM_INT_REQ_CF_REQ__M 0x2
#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0
#define IQM_COMM_INT_STA__A 0x1800005
#define IQM_COMM_INT_STA__W 16
#define IQM_COMM_INT_STA__M 0xFFFF
#define IQM_COMM_INT_STA__PRE 0x0
#define IQM_COMM_INT_MSK__A 0x1800006
#define IQM_COMM_INT_MSK__W 16
#define IQM_COMM_INT_MSK__M 0xFFFF
#define IQM_COMM_INT_MSK__PRE 0x0
#define IQM_COMM_INT_STM__A 0x1800007
#define IQM_COMM_INT_STM__W 16
#define IQM_COMM_INT_STM__M 0xFFFF
#define IQM_COMM_INT_STM__PRE 0x0
#define IQM_FS_COMM_EXEC__A 0x1820000
#define IQM_FS_COMM_EXEC__W 2
#define IQM_FS_COMM_EXEC__M 0x3
#define IQM_FS_COMM_EXEC__PRE 0x0
#define IQM_FS_COMM_EXEC_STOP 0x0
#define IQM_FS_COMM_EXEC_ACTIVE 0x1
#define IQM_FS_COMM_EXEC_HOLD 0x2
#define IQM_FS_COMM_MB__A 0x1820002
#define IQM_FS_COMM_MB__W 2
#define IQM_FS_COMM_MB__M 0x3
#define IQM_FS_COMM_MB__PRE 0x0
#define IQM_FS_COMM_MB_CTL__B 0
#define IQM_FS_COMM_MB_CTL__W 1
#define IQM_FS_COMM_MB_CTL__M 0x1
#define IQM_FS_COMM_MB_CTL__PRE 0x0
#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0
#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1
#define IQM_FS_COMM_MB_OBS__B 1
#define IQM_FS_COMM_MB_OBS__W 1
#define IQM_FS_COMM_MB_OBS__M 0x2
#define IQM_FS_COMM_MB_OBS__PRE 0x0
#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0
#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2
#define IQM_FS_RATE_OFS_LO__A 0x1820010
#define IQM_FS_RATE_OFS_LO__W 16
#define IQM_FS_RATE_OFS_LO__M 0xFFFF
#define IQM_FS_RATE_OFS_LO__PRE 0x0
#define IQM_FS_RATE_OFS_HI__A 0x1820011
#define IQM_FS_RATE_OFS_HI__W 12
#define IQM_FS_RATE_OFS_HI__M 0xFFF
#define IQM_FS_RATE_OFS_HI__PRE 0x0
#define IQM_FS_RATE_LO__A 0x1820012
#define IQM_FS_RATE_LO__W 16
#define IQM_FS_RATE_LO__M 0xFFFF
#define IQM_FS_RATE_LO__PRE 0x0
#define IQM_FS_RATE_HI__A 0x1820013
#define IQM_FS_RATE_HI__W 12
#define IQM_FS_RATE_HI__M 0xFFF
#define IQM_FS_RATE_HI__PRE 0x0
#define IQM_FS_ADJ_SEL__A 0x1820014
#define IQM_FS_ADJ_SEL__W 2
#define IQM_FS_ADJ_SEL__M 0x3
#define IQM_FS_ADJ_SEL__PRE 0x0
#define IQM_FS_ADJ_SEL_OFF 0x0
#define IQM_FS_ADJ_SEL_QAM 0x1
#define IQM_FS_ADJ_SEL_VSB 0x2
#define IQM_FD_COMM_EXEC__A 0x1830000
#define IQM_FD_COMM_EXEC__W 2
#define IQM_FD_COMM_EXEC__M 0x3
#define IQM_FD_COMM_EXEC__PRE 0x0
#define IQM_FD_COMM_EXEC_STOP 0x0
#define IQM_FD_COMM_EXEC_ACTIVE 0x1
#define IQM_FD_COMM_EXEC_HOLD 0x2
#define IQM_FD_COMM_MB__A 0x1830002
#define IQM_FD_COMM_MB__W 2
#define IQM_FD_COMM_MB__M 0x3
#define IQM_FD_COMM_MB__PRE 0x0
#define IQM_FD_COMM_MB_CTL__B 0
#define IQM_FD_COMM_MB_CTL__W 1
#define IQM_FD_COMM_MB_CTL__M 0x1
#define IQM_FD_COMM_MB_CTL__PRE 0x0
#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0
#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1
#define IQM_FD_COMM_MB_OBS__B 1
#define IQM_FD_COMM_MB_OBS__W 1
#define IQM_FD_COMM_MB_OBS__M 0x2
#define IQM_FD_COMM_MB_OBS__PRE 0x0
#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0
#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2
#define IQM_RC_COMM_EXEC__A 0x1840000
#define IQM_RC_COMM_EXEC__W 2
#define IQM_RC_COMM_EXEC__M 0x3
#define IQM_RC_COMM_EXEC__PRE 0x0
#define IQM_RC_COMM_EXEC_STOP 0x0
#define IQM_RC_COMM_EXEC_ACTIVE 0x1
#define IQM_RC_COMM_EXEC_HOLD 0x2
#define IQM_RC_COMM_MB__A 0x1840002
#define IQM_RC_COMM_MB__W 2
#define IQM_RC_COMM_MB__M 0x3
#define IQM_RC_COMM_MB__PRE 0x0
#define IQM_RC_COMM_MB_CTL__B 0
#define IQM_RC_COMM_MB_CTL__W 1
#define IQM_RC_COMM_MB_CTL__M 0x1
#define IQM_RC_COMM_MB_CTL__PRE 0x0
#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0
#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1
#define IQM_RC_COMM_MB_OBS__B 1
#define IQM_RC_COMM_MB_OBS__W 1
#define IQM_RC_COMM_MB_OBS__M 0x2
#define IQM_RC_COMM_MB_OBS__PRE 0x0
#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0
#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2
#define IQM_RC_RATE_OFS_LO__A 0x1840010
#define IQM_RC_RATE_OFS_LO__W 16
#define IQM_RC_RATE_OFS_LO__M 0xFFFF
#define IQM_RC_RATE_OFS_LO__PRE 0x0
#define IQM_RC_RATE_OFS_HI__A 0x1840011
#define IQM_RC_RATE_OFS_HI__W 8
#define IQM_RC_RATE_OFS_HI__M 0xFF
#define IQM_RC_RATE_OFS_HI__PRE 0x0
#define IQM_RC_RATE_LO__A 0x1840012
#define IQM_RC_RATE_LO__W 16
#define IQM_RC_RATE_LO__M 0xFFFF
#define IQM_RC_RATE_LO__PRE 0x0
#define IQM_RC_RATE_HI__A 0x1840013
#define IQM_RC_RATE_HI__W 8
#define IQM_RC_RATE_HI__M 0xFF
#define IQM_RC_RATE_HI__PRE 0x0
#define IQM_RC_ADJ_SEL__A 0x1840014
#define IQM_RC_ADJ_SEL__W 2
#define IQM_RC_ADJ_SEL__M 0x3
#define IQM_RC_ADJ_SEL__PRE 0x0
#define IQM_RC_ADJ_SEL_OFF 0x0
#define IQM_RC_ADJ_SEL_QAM 0x1
#define IQM_RC_ADJ_SEL_VSB 0x2
#define IQM_RC_CROUT_ENA__A 0x1840015
#define IQM_RC_CROUT_ENA__W 1
#define IQM_RC_CROUT_ENA__M 0x1
#define IQM_RC_CROUT_ENA__PRE 0x0
#define IQM_RC_CROUT_ENA_ENA__B 0
#define IQM_RC_CROUT_ENA_ENA__W 1
#define IQM_RC_CROUT_ENA_ENA__M 0x1
#define IQM_RC_CROUT_ENA_ENA__PRE 0x0
#define IQM_RC_STRETCH__A 0x1840016
#define IQM_RC_STRETCH__W 5
#define IQM_RC_STRETCH__M 0x1F
#define IQM_RC_STRETCH__PRE 0x0
#define IQM_RC_STRETCH_QAM_B_64 0x1E
#define IQM_RC_STRETCH_QAM_B_256 0x1C
#define IQM_RC_STRETCH_ATV 0xF
#define IQM_RT_COMM_EXEC__A 0x1850000
#define IQM_RT_COMM_EXEC__W 2
#define IQM_RT_COMM_EXEC__M 0x3
#define IQM_RT_COMM_EXEC__PRE 0x0
#define IQM_RT_COMM_EXEC_STOP 0x0
#define IQM_RT_COMM_EXEC_ACTIVE 0x1
#define IQM_RT_COMM_EXEC_HOLD 0x2
#define IQM_RT_COMM_MB__A 0x1850002
#define IQM_RT_COMM_MB__W 2
#define IQM_RT_COMM_MB__M 0x3
#define IQM_RT_COMM_MB__PRE 0x0
#define IQM_RT_COMM_MB_CTL__B 0
#define IQM_RT_COMM_MB_CTL__W 1
#define IQM_RT_COMM_MB_CTL__M 0x1
#define IQM_RT_COMM_MB_CTL__PRE 0x0
#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0
#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1
#define IQM_RT_COMM_MB_OBS__B 1
#define IQM_RT_COMM_MB_OBS__W 1
#define IQM_RT_COMM_MB_OBS__M 0x2
#define IQM_RT_COMM_MB_OBS__PRE 0x0
#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0
#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2
#define IQM_RT_ACTIVE__A 0x1850010
#define IQM_RT_ACTIVE__W 2
#define IQM_RT_ACTIVE__M 0x3
#define IQM_RT_ACTIVE__PRE 0x0
#define IQM_RT_ACTIVE_ACTIVE_RT__B 0
#define IQM_RT_ACTIVE_ACTIVE_RT__W 1
#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1
#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0
#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0
#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1
#define IQM_RT_ACTIVE_ACTIVE_CR__B 1
#define IQM_RT_ACTIVE_ACTIVE_CR__W 1
#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2
#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0
#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0
#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2
#define IQM_RT_LO_INCR__A 0x1850011
#define IQM_RT_LO_INCR__W 12
#define IQM_RT_LO_INCR__M 0xFFF
#define IQM_RT_LO_INCR__PRE 0x588
#define IQM_RT_LO_INCR_FM 0x0
#define IQM_RT_LO_INCR_MN 0x588
#define IQM_RT_ROT_BP__A 0x1850012
#define IQM_RT_ROT_BP__W 2
#define IQM_RT_ROT_BP__M 0x3
#define IQM_RT_ROT_BP__PRE 0x0
#define IQM_RT_ROT_BP_ROT_OFF__B 0
#define IQM_RT_ROT_BP_ROT_OFF__W 1
#define IQM_RT_ROT_BP_ROT_OFF__M 0x1
#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0
#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0
#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1
#define IQM_RT_ROT_BP_ROT_BPF__B 1
#define IQM_RT_ROT_BP_ROT_BPF__W 1
#define IQM_RT_ROT_BP_ROT_BPF__M 0x2
#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0
#define IQM_RT_LP_BP__A 0x1850013
#define IQM_RT_LP_BP__W 1
#define IQM_RT_LP_BP__M 0x1
#define IQM_RT_LP_BP__PRE 0x0
#define IQM_RT_DELAY__A 0x1850014
#define IQM_RT_DELAY__W 7
#define IQM_RT_DELAY__M 0x7F
#define IQM_RT_DELAY__PRE 0x45
#define IQM_CF_COMM_EXEC__A 0x1860000
#define IQM_CF_COMM_EXEC__W 2
#define IQM_CF_COMM_EXEC__M 0x3
#define IQM_CF_COMM_EXEC__PRE 0x0
#define IQM_CF_COMM_EXEC_STOP 0x0
#define IQM_CF_COMM_EXEC_ACTIVE 0x1
#define IQM_CF_COMM_EXEC_HOLD 0x2
#define IQM_CF_COMM_MB__A 0x1860002
#define IQM_CF_COMM_MB__W 2
#define IQM_CF_COMM_MB__M 0x3
#define IQM_CF_COMM_MB__PRE 0x0
#define IQM_CF_COMM_MB_CTL__B 0
#define IQM_CF_COMM_MB_CTL__W 1
#define IQM_CF_COMM_MB_CTL__M 0x1
#define IQM_CF_COMM_MB_CTL__PRE 0x0
#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0
#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1
#define IQM_CF_COMM_MB_OBS__B 1
#define IQM_CF_COMM_MB_OBS__W 1
#define IQM_CF_COMM_MB_OBS__M 0x2
#define IQM_CF_COMM_MB_OBS__PRE 0x0
#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0
#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2
#define IQM_CF_COMM_INT_REQ__A 0x1860003
#define IQM_CF_COMM_INT_REQ__W 1
#define IQM_CF_COMM_INT_REQ__M 0x1
#define IQM_CF_COMM_INT_REQ__PRE 0x0
#define IQM_CF_COMM_INT_STA__A 0x1860005
#define IQM_CF_COMM_INT_STA__W 1
#define IQM_CF_COMM_INT_STA__M 0x1
#define IQM_CF_COMM_INT_STA__PRE 0x0
#define IQM_CF_COMM_INT_STA_PM__B 0
#define IQM_CF_COMM_INT_STA_PM__W 1
#define IQM_CF_COMM_INT_STA_PM__M 0x1
#define IQM_CF_COMM_INT_STA_PM__PRE 0x0
#define IQM_CF_COMM_INT_MSK__A 0x1860006
#define IQM_CF_COMM_INT_MSK__W 1
#define IQM_CF_COMM_INT_MSK__M 0x1
#define IQM_CF_COMM_INT_MSK__PRE 0x0
#define IQM_CF_COMM_INT_MSK_PM__B 0
#define IQM_CF_COMM_INT_MSK_PM__W 1
#define IQM_CF_COMM_INT_MSK_PM__M 0x1
#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0
#define IQM_CF_COMM_INT_STM__A 0x1860007
#define IQM_CF_COMM_INT_STM__W 1
#define IQM_CF_COMM_INT_STM__M 0x1
#define IQM_CF_COMM_INT_STM__PRE 0x0
#define IQM_CF_COMM_INT_STM_PM__B 0
#define IQM_CF_COMM_INT_STM_PM__W 1
#define IQM_CF_COMM_INT_STM_PM__M 0x1
#define IQM_CF_COMM_INT_STM_PM__PRE 0x0
#define IQM_CF_SYMMETRIC__A 0x1860010
#define IQM_CF_SYMMETRIC__W 2
#define IQM_CF_SYMMETRIC__M 0x3
#define IQM_CF_SYMMETRIC__PRE 0x0
#define IQM_CF_SYMMETRIC_RE__B 0
#define IQM_CF_SYMMETRIC_RE__W 1
#define IQM_CF_SYMMETRIC_RE__M 0x1
#define IQM_CF_SYMMETRIC_RE__PRE 0x0
#define IQM_CF_SYMMETRIC_IM__B 1
#define IQM_CF_SYMMETRIC_IM__W 1
#define IQM_CF_SYMMETRIC_IM__M 0x2
#define IQM_CF_SYMMETRIC_IM__PRE 0x0
#define IQM_CF_MIDTAP__A 0x1860011
#define IQM_CF_MIDTAP__W 2
#define IQM_CF_MIDTAP__M 0x3
#define IQM_CF_MIDTAP__PRE 0x3
#define IQM_CF_MIDTAP_RE__B 0
#define IQM_CF_MIDTAP_RE__W 1
#define IQM_CF_MIDTAP_RE__M 0x1
#define IQM_CF_MIDTAP_RE__PRE 0x1
#define IQM_CF_MIDTAP_IM__B 1
#define IQM_CF_MIDTAP_IM__W 1
#define IQM_CF_MIDTAP_IM__M 0x2
#define IQM_CF_MIDTAP_IM__PRE 0x2
#define IQM_CF_OUT_ENA__A 0x1860012
#define IQM_CF_OUT_ENA__W 3
#define IQM_CF_OUT_ENA__M 0x7
#define IQM_CF_OUT_ENA__PRE 0x0
#define IQM_CF_OUT_ENA_ATV__B 0
#define IQM_CF_OUT_ENA_ATV__W 1
#define IQM_CF_OUT_ENA_ATV__M 0x1
#define IQM_CF_OUT_ENA_ATV__PRE 0x0
#define IQM_CF_OUT_ENA_QAM__B 1
#define IQM_CF_OUT_ENA_QAM__W 1
#define IQM_CF_OUT_ENA_QAM__M 0x2
#define IQM_CF_OUT_ENA_QAM__PRE 0x0
#define IQM_CF_OUT_ENA_VSB__B 2
#define IQM_CF_OUT_ENA_VSB__W 1
#define IQM_CF_OUT_ENA_VSB__M 0x4
#define IQM_CF_OUT_ENA_VSB__PRE 0x0
#define IQM_CF_ADJ_SEL__A 0x1860013
#define IQM_CF_ADJ_SEL__W 2
#define IQM_CF_ADJ_SEL__M 0x3
#define IQM_CF_ADJ_SEL__PRE 0x0
#define IQM_CF_SCALE__A 0x1860014
#define IQM_CF_SCALE__W 14
#define IQM_CF_SCALE__M 0x3FFF
#define IQM_CF_SCALE__PRE 0x400
#define IQM_CF_SCALE_SH__A 0x1860015
#define IQM_CF_SCALE_SH__W 2
#define IQM_CF_SCALE_SH__M 0x3
#define IQM_CF_SCALE_SH__PRE 0x0
#define IQM_CF_AMP__A 0x1860016
#define IQM_CF_AMP__W 14
#define IQM_CF_AMP__M 0x3FFF
#define IQM_CF_AMP__PRE 0x0
#define IQM_CF_POW_MEAS_LEN__A 0x1860017
#define IQM_CF_POW_MEAS_LEN__W 3
#define IQM_CF_POW_MEAS_LEN__M 0x7
#define IQM_CF_POW_MEAS_LEN__PRE 0x2
#define IQM_CF_POW_MEAS_LEN_QAM_B_64 0x1
#define IQM_CF_POW_MEAS_LEN_QAM_B_256 0x1
#define IQM_CF_POW__A 0x1860018
#define IQM_CF_POW__W 16
#define IQM_CF_POW__M 0xFFFF
#define IQM_CF_POW__PRE 0x2
#define IQM_CF_TAP_RE0__A 0x1860020
#define IQM_CF_TAP_RE0__W 7
#define IQM_CF_TAP_RE0__M 0x7F
#define IQM_CF_TAP_RE0__PRE 0x2
#define IQM_CF_TAP_RE1__A 0x1860021
#define IQM_CF_TAP_RE1__W 7
#define IQM_CF_TAP_RE1__M 0x7F
#define IQM_CF_TAP_RE1__PRE 0x2
#define IQM_CF_TAP_RE2__A 0x1860022
#define IQM_CF_TAP_RE2__W 7
#define IQM_CF_TAP_RE2__M 0x7F
#define IQM_CF_TAP_RE2__PRE 0x2
#define IQM_CF_TAP_RE3__A 0x1860023
#define IQM_CF_TAP_RE3__W 7
#define IQM_CF_TAP_RE3__M 0x7F
#define IQM_CF_TAP_RE3__PRE 0x2
#define IQM_CF_TAP_RE4__A 0x1860024
#define IQM_CF_TAP_RE4__W 7
#define IQM_CF_TAP_RE4__M 0x7F
#define IQM_CF_TAP_RE4__PRE 0x2
#define IQM_CF_TAP_RE5__A 0x1860025
#define IQM_CF_TAP_RE5__W 7
#define IQM_CF_TAP_RE5__M 0x7F
#define IQM_CF_TAP_RE5__PRE 0x2
#define IQM_CF_TAP_RE6__A 0x1860026
#define IQM_CF_TAP_RE6__W 7
#define IQM_CF_TAP_RE6__M 0x7F
#define IQM_CF_TAP_RE6__PRE 0x2
#define IQM_CF_TAP_RE7__A 0x1860027
#define IQM_CF_TAP_RE7__W 9
#define IQM_CF_TAP_RE7__M 0x1FF
#define IQM_CF_TAP_RE7__PRE 0x2
#define IQM_CF_TAP_RE8__A 0x1860028
#define IQM_CF_TAP_RE8__W 9
#define IQM_CF_TAP_RE8__M 0x1FF
#define IQM_CF_TAP_RE8__PRE 0x2
#define IQM_CF_TAP_RE9__A 0x1860029
#define IQM_CF_TAP_RE9__W 9
#define IQM_CF_TAP_RE9__M 0x1FF
#define IQM_CF_TAP_RE9__PRE 0x2
#define IQM_CF_TAP_RE10__A 0x186002A
#define IQM_CF_TAP_RE10__W 9
#define IQM_CF_TAP_RE10__M 0x1FF
#define IQM_CF_TAP_RE10__PRE 0x2
#define IQM_CF_TAP_RE11__A 0x186002B
#define IQM_CF_TAP_RE11__W 9
#define IQM_CF_TAP_RE11__M 0x1FF
#define IQM_CF_TAP_RE11__PRE 0x2
#define IQM_CF_TAP_RE12__A 0x186002C
#define IQM_CF_TAP_RE12__W 9
#define IQM_CF_TAP_RE12__M 0x1FF
#define IQM_CF_TAP_RE12__PRE 0x2
#define IQM_CF_TAP_RE13__A 0x186002D
#define IQM_CF_TAP_RE13__W 9
#define IQM_CF_TAP_RE13__M 0x1FF
#define IQM_CF_TAP_RE13__PRE 0x2
#define IQM_CF_TAP_RE14__A 0x186002E
#define IQM_CF_TAP_RE14__W 9
#define IQM_CF_TAP_RE14__M 0x1FF
#define IQM_CF_TAP_RE14__PRE 0x2
#define IQM_CF_TAP_RE15__A 0x186002F
#define IQM_CF_TAP_RE15__W 9
#define IQM_CF_TAP_RE15__M 0x1FF
#define IQM_CF_TAP_RE15__PRE 0x2
#define IQM_CF_TAP_RE16__A 0x1860030
#define IQM_CF_TAP_RE16__W 9
#define IQM_CF_TAP_RE16__M 0x1FF
#define IQM_CF_TAP_RE16__PRE 0x2
#define IQM_CF_TAP_RE17__A 0x1860031
#define IQM_CF_TAP_RE17__W 9
#define IQM_CF_TAP_RE17__M 0x1FF
#define IQM_CF_TAP_RE17__PRE 0x2
#define IQM_CF_TAP_RE18__A 0x1860032
#define IQM_CF_TAP_RE18__W 9
#define IQM_CF_TAP_RE18__M 0x1FF
#define IQM_CF_TAP_RE18__PRE 0x2
#define IQM_CF_TAP_RE19__A 0x1860033
#define IQM_CF_TAP_RE19__W 9
#define IQM_CF_TAP_RE19__M 0x1FF
#define IQM_CF_TAP_RE19__PRE 0x2
#define IQM_CF_TAP_RE20__A 0x1860034
#define IQM_CF_TAP_RE20__W 9
#define IQM_CF_TAP_RE20__M 0x1FF
#define IQM_CF_TAP_RE20__PRE 0x2
#define IQM_CF_TAP_RE21__A 0x1860035
#define IQM_CF_TAP_RE21__W 11
#define IQM_CF_TAP_RE21__M 0x7FF
#define IQM_CF_TAP_RE21__PRE 0x2
#define IQM_CF_TAP_RE22__A 0x1860036
#define IQM_CF_TAP_RE22__W 11
#define IQM_CF_TAP_RE22__M 0x7FF
#define IQM_CF_TAP_RE22__PRE 0x2
#define IQM_CF_TAP_RE23__A 0x1860037
#define IQM_CF_TAP_RE23__W 11
#define IQM_CF_TAP_RE23__M 0x7FF
#define IQM_CF_TAP_RE23__PRE 0x2
#define IQM_CF_TAP_RE24__A 0x1860038
#define IQM_CF_TAP_RE24__W 11
#define IQM_CF_TAP_RE24__M 0x7FF
#define IQM_CF_TAP_RE24__PRE 0x2
#define IQM_CF_TAP_RE25__A 0x1860039
#define IQM_CF_TAP_RE25__W 11
#define IQM_CF_TAP_RE25__M 0x7FF
#define IQM_CF_TAP_RE25__PRE 0x2
#define IQM_CF_TAP_RE26__A 0x186003A
#define IQM_CF_TAP_RE26__W 11
#define IQM_CF_TAP_RE26__M 0x7FF
#define IQM_CF_TAP_RE26__PRE 0x2
#define IQM_CF_TAP_RE27__A 0x186003B
#define IQM_CF_TAP_RE27__W 11
#define IQM_CF_TAP_RE27__M 0x7FF
#define IQM_CF_TAP_RE27__PRE 0x2
#define IQM_CF_TAP_IM0__A 0x1860040
#define IQM_CF_TAP_IM0__W 7
#define IQM_CF_TAP_IM0__M 0x7F
#define IQM_CF_TAP_IM0__PRE 0x2
#define IQM_CF_TAP_IM1__A 0x1860041
#define IQM_CF_TAP_IM1__W 7
#define IQM_CF_TAP_IM1__M 0x7F
#define IQM_CF_TAP_IM1__PRE 0x2
#define IQM_CF_TAP_IM2__A 0x1860042
#define IQM_CF_TAP_IM2__W 7
#define IQM_CF_TAP_IM2__M 0x7F
#define IQM_CF_TAP_IM2__PRE 0x2
#define IQM_CF_TAP_IM3__A 0x1860043
#define IQM_CF_TAP_IM3__W 7
#define IQM_CF_TAP_IM3__M 0x7F
#define IQM_CF_TAP_IM3__PRE 0x2
#define IQM_CF_TAP_IM4__A 0x1860044
#define IQM_CF_TAP_IM4__W 7
#define IQM_CF_TAP_IM4__M 0x7F
#define IQM_CF_TAP_IM4__PRE 0x2
#define IQM_CF_TAP_IM5__A 0x1860045
#define IQM_CF_TAP_IM5__W 7
#define IQM_CF_TAP_IM5__M 0x7F
#define IQM_CF_TAP_IM5__PRE 0x2
#define IQM_CF_TAP_IM6__A 0x1860046
#define IQM_CF_TAP_IM6__W 7
#define IQM_CF_TAP_IM6__M 0x7F
#define IQM_CF_TAP_IM6__PRE 0x2
#define IQM_CF_TAP_IM7__A 0x1860047
#define IQM_CF_TAP_IM7__W 9
#define IQM_CF_TAP_IM7__M 0x1FF
#define IQM_CF_TAP_IM7__PRE 0x2
#define IQM_CF_TAP_IM8__A 0x1860048
#define IQM_CF_TAP_IM8__W 9
#define IQM_CF_TAP_IM8__M 0x1FF
#define IQM_CF_TAP_IM8__PRE 0x2
#define IQM_CF_TAP_IM9__A 0x1860049
#define IQM_CF_TAP_IM9__W 9
#define IQM_CF_TAP_IM9__M 0x1FF
#define IQM_CF_TAP_IM9__PRE 0x2
#define IQM_CF_TAP_IM10__A 0x186004A
#define IQM_CF_TAP_IM10__W 9
#define IQM_CF_TAP_IM10__M 0x1FF
#define IQM_CF_TAP_IM10__PRE 0x2
#define IQM_CF_TAP_IM11__A 0x186004B
#define IQM_CF_TAP_IM11__W 9
#define IQM_CF_TAP_IM11__M 0x1FF
#define IQM_CF_TAP_IM11__PRE 0x2
#define IQM_CF_TAP_IM12__A 0x186004C
#define IQM_CF_TAP_IM12__W 9
#define IQM_CF_TAP_IM12__M 0x1FF
#define IQM_CF_TAP_IM12__PRE 0x2
#define IQM_CF_TAP_IM13__A 0x186004D
#define IQM_CF_TAP_IM13__W 9
#define IQM_CF_TAP_IM13__M 0x1FF
#define IQM_CF_TAP_IM13__PRE 0x2
#define IQM_CF_TAP_IM14__A 0x186004E
#define IQM_CF_TAP_IM14__W 9
#define IQM_CF_TAP_IM14__M 0x1FF
#define IQM_CF_TAP_IM14__PRE 0x2
#define IQM_CF_TAP_IM15__A 0x186004F
#define IQM_CF_TAP_IM15__W 9
#define IQM_CF_TAP_IM15__M 0x1FF
#define IQM_CF_TAP_IM15__PRE 0x2
#define IQM_CF_TAP_IM16__A 0x1860050
#define IQM_CF_TAP_IM16__W 9
#define IQM_CF_TAP_IM16__M 0x1FF
#define IQM_CF_TAP_IM16__PRE 0x2
#define IQM_CF_TAP_IM17__A 0x1860051
#define IQM_CF_TAP_IM17__W 9
#define IQM_CF_TAP_IM17__M 0x1FF
#define IQM_CF_TAP_IM17__PRE 0x2
#define IQM_CF_TAP_IM18__A 0x1860052
#define IQM_CF_TAP_IM18__W 9
#define IQM_CF_TAP_IM18__M 0x1FF
#define IQM_CF_TAP_IM18__PRE 0x2
#define IQM_CF_TAP_IM19__A 0x1860053
#define IQM_CF_TAP_IM19__W 9
#define IQM_CF_TAP_IM19__M 0x1FF
#define IQM_CF_TAP_IM19__PRE 0x2
#define IQM_CF_TAP_IM20__A 0x1860054
#define IQM_CF_TAP_IM20__W 9
#define IQM_CF_TAP_IM20__M 0x1FF
#define IQM_CF_TAP_IM20__PRE 0x2
#define IQM_CF_TAP_IM21__A 0x1860055
#define IQM_CF_TAP_IM21__W 11
#define IQM_CF_TAP_IM21__M 0x7FF
#define IQM_CF_TAP_IM21__PRE 0x2
#define IQM_CF_TAP_IM22__A 0x1860056
#define IQM_CF_TAP_IM22__W 11
#define IQM_CF_TAP_IM22__M 0x7FF
#define IQM_CF_TAP_IM22__PRE 0x2
#define IQM_CF_TAP_IM23__A 0x1860057
#define IQM_CF_TAP_IM23__W 11
#define IQM_CF_TAP_IM23__M 0x7FF
#define IQM_CF_TAP_IM23__PRE 0x2
#define IQM_CF_TAP_IM24__A 0x1860058
#define IQM_CF_TAP_IM24__W 11
#define IQM_CF_TAP_IM24__M 0x7FF
#define IQM_CF_TAP_IM24__PRE 0x2
#define IQM_CF_TAP_IM25__A 0x1860059
#define IQM_CF_TAP_IM25__W 11
#define IQM_CF_TAP_IM25__M 0x7FF
#define IQM_CF_TAP_IM25__PRE 0x2
#define IQM_CF_TAP_IM26__A 0x186005A
#define IQM_CF_TAP_IM26__W 11
#define IQM_CF_TAP_IM26__M 0x7FF
#define IQM_CF_TAP_IM26__PRE 0x2
#define IQM_CF_TAP_IM27__A 0x186005B
#define IQM_CF_TAP_IM27__W 11
#define IQM_CF_TAP_IM27__M 0x7FF
#define IQM_CF_TAP_IM27__PRE 0x2
#define IQM_AF_COMM_EXEC__A 0x1870000
#define IQM_AF_COMM_EXEC__W 2
#define IQM_AF_COMM_EXEC__M 0x3
#define IQM_AF_COMM_EXEC__PRE 0x0
#define IQM_AF_COMM_EXEC_STOP 0x0
#define IQM_AF_COMM_EXEC_ACTIVE 0x1
#define IQM_AF_COMM_EXEC_HOLD 0x2
#define IQM_AF_COMM_MB__A 0x1870002
#define IQM_AF_COMM_MB__W 8
#define IQM_AF_COMM_MB__M 0xFF
#define IQM_AF_COMM_MB__PRE 0x0
#define IQM_AF_COMM_MB_CTL__B 0
#define IQM_AF_COMM_MB_CTL__W 1
#define IQM_AF_COMM_MB_CTL__M 0x1
#define IQM_AF_COMM_MB_CTL__PRE 0x0
#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0
#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1
#define IQM_AF_COMM_MB_OBS__B 1
#define IQM_AF_COMM_MB_OBS__W 1
#define IQM_AF_COMM_MB_OBS__M 0x2
#define IQM_AF_COMM_MB_OBS__PRE 0x0
#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0
#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2
#define IQM_AF_COMM_MB_MUX_CTRL__B 2
#define IQM_AF_COMM_MB_MUX_CTRL__W 3
#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C
#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0
#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0
#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4
#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8
#define IQM_AF_COMM_MB_MUX_CTRL