drivers/gpu/drm/mediatek/mtk_disp_ovl.c - linux/kernel/git/bpf/bpf - Git at Google

 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2015 MediaTek Inc.
  */

 #include <drm/drm_fourcc.h>

 #include <linux/clk.h>
 #include <linux/component.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/of_irq.h>
 #include <linux/platform_device.h>
 #include <linux/soc/mediatek/mtk-cmdq.h>

 #include "mtk_drm_crtc.h"
 #include "mtk_drm_ddp_comp.h"

 #define DISP_REG_OVL_INTEN			0x0004
 #define OVL_FME_CPL_INT					BIT(1)
 #define DISP_REG_OVL_INTSTA			0x0008
 #define DISP_REG_OVL_EN				0x000c
 #define DISP_REG_OVL_RST			0x0014
 #define DISP_REG_OVL_ROI_SIZE			0x0020
 #define DISP_REG_OVL_DATAPATH_CON		0x0024
 #define OVL_BGCLR_SEL_IN				BIT(2)
 #define DISP_REG_OVL_ROI_BGCLR			0x0028
 #define DISP_REG_OVL_SRC_CON			0x002c
 #define DISP_REG_OVL_CON(n)			(0x0030 + 0x20 * (n))
 #define DISP_REG_OVL_SRC_SIZE(n)		(0x0038 + 0x20 * (n))
 #define DISP_REG_OVL_OFFSET(n)			(0x003c + 0x20 * (n))
 #define DISP_REG_OVL_PITCH(n)			(0x0044 + 0x20 * (n))
 #define DISP_REG_OVL_RDMA_CTRL(n)		(0x00c0 + 0x20 * (n))
 #define DISP_REG_OVL_RDMA_GMC(n)		(0x00c8 + 0x20 * (n))
 #define DISP_REG_OVL_ADDR_MT2701		0x0040
 #define DISP_REG_OVL_ADDR_MT8173		0x0f40
 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))

 #define GMC_THRESHOLD_BITS	16
 #define GMC_THRESHOLD_HIGH	((1 << GMC_THRESHOLD_BITS) / 4)
 #define GMC_THRESHOLD_LOW	((1 << GMC_THRESHOLD_BITS) / 8)

 #define OVL_CON_BYTE_SWAP	BIT(24)
 #define OVL_CON_MTX_YUV_TO_RGB	(6 << 16)
 #define OVL_CON_CLRFMT_RGB	(1 << 12)
 #define OVL_CON_CLRFMT_RGBA8888	(2 << 12)
 #define OVL_CON_CLRFMT_ARGB8888	(3 << 12)
 #define OVL_CON_CLRFMT_UYVY	(4 << 12)
 #define OVL_CON_CLRFMT_YUYV	(5 << 12)
 #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
 					0 : OVL_CON_CLRFMT_RGB)
 #define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
 					OVL_CON_CLRFMT_RGB : 0)
 #define	OVL_CON_AEN		BIT(8)
 #define	OVL_CON_ALPHA		0xff
 #define	OVL_CON_VIRT_FLIP	BIT(9)
 #define	OVL_CON_HORZ_FLIP	BIT(10)

 struct mtk_disp_ovl_data {
 	unsigned int addr;
 	unsigned int gmc_bits;
 	unsigned int layer_nr;
 	bool fmt_rgb565_is_0;
 };

 /**
  * struct mtk_disp_ovl - DISP_OVL driver structure
  * @ddp_comp - structure containing type enum and hardware resources
  * @crtc - associated crtc to report vblank events to
  */
 struct mtk_disp_ovl {
 	struct mtk_ddp_comp		ddp_comp;
 	struct drm_crtc			*crtc;
 	const struct mtk_disp_ovl_data	*data;
 };

 static inline struct mtk_disp_ovl *comp_to_ovl(struct mtk_ddp_comp *comp)
 {
 	return container_of(comp, struct mtk_disp_ovl, ddp_comp);
 }

 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
 {
 	struct mtk_disp_ovl *priv = dev_id;
 	struct mtk_ddp_comp *ovl = &priv->ddp_comp;

 	/* Clear frame completion interrupt */
 	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);

 	if (!priv->crtc)
 		return IRQ_NONE;

 	mtk_crtc_ddp_irq(priv->crtc, ovl);

 	return IRQ_HANDLED;
 }

 static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp,
 				  struct drm_crtc *crtc)
 {
 	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);

 	ovl->crtc = crtc;
 	writel(0x0, comp->regs + DISP_REG_OVL_INTSTA);
 	writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);
 }

 static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
 {
 	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);

 	ovl->crtc = NULL;
 	writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN);
 }

 static void mtk_ovl_start(struct mtk_ddp_comp *comp)
 {
 	writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
 }

 static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
 {
 	writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN);
 }

 static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
 			   unsigned int h, unsigned int vrefresh,
 			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 {
 	if (w != 0 && h != 0)
 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp,
 				      DISP_REG_OVL_ROI_SIZE);
 	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);

 	mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST);
 	mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST);
 }

 static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
 {
 	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);

 	return ovl->data->layer_nr;
 }

 static unsigned int mtk_ovl_supported_rotations(struct mtk_ddp_comp *comp)
 {
 	return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
 	       DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
 }

 static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx,
 			       struct mtk_plane_state *mtk_state)
 {
 	struct drm_plane_state *state = &mtk_state->base;
 	unsigned int rotation = 0;

 	rotation = drm_rotation_simplify(state->rotation,
 					 DRM_MODE_ROTATE_0 |
 					 DRM_MODE_REFLECT_X |
 					 DRM_MODE_REFLECT_Y);
 	rotation &= ~DRM_MODE_ROTATE_0;

 	/* We can only do reflection, not rotation */
 	if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
 		return -EINVAL;

 	/*
 	 * TODO: Rotating/reflecting YUV buffers is not supported at this time.
 	 *	 Only RGB[AX] variants are supported.
 	 */
 	if (state->fb->format->is_yuv && rotation != 0)
 		return -EINVAL;

 	state->rotation = rotation;

 	return 0;
 }

 static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
 			     struct cmdq_pkt *cmdq_pkt)
 {
 	unsigned int gmc_thrshd_l;
 	unsigned int gmc_thrshd_h;
 	unsigned int gmc_value;
 	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);

 	mtk_ddp_write(cmdq_pkt, 0x1, comp,
 		      DISP_REG_OVL_RDMA_CTRL(idx));
 	gmc_thrshd_l = GMC_THRESHOLD_LOW >>
 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
 	gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
 	if (ovl->data->gmc_bits == 10)
 		gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
 	else
 		gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
 			    gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
 	mtk_ddp_write(cmdq_pkt, gmc_value,
 		      comp, DISP_REG_OVL_RDMA_GMC(idx));
 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp,
 			   DISP_REG_OVL_SRC_CON, BIT(idx));
 }

 static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,
 			      struct cmdq_pkt *cmdq_pkt)
 {
 	mtk_ddp_write_mask(cmdq_pkt, 0, comp,
 			   DISP_REG_OVL_SRC_CON, BIT(idx));
 	mtk_ddp_write(cmdq_pkt, 0, comp,
 		      DISP_REG_OVL_RDMA_CTRL(idx));
 }

 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
 {
 	/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
 	 * is defined in mediatek HW data sheet.
 	 * The alphabet order in XXX is no relation to data
 	 * arrangement in memory.
 	 */
 	switch (fmt) {
 	default:
 	case DRM_FORMAT_RGB565:
 		return OVL_CON_CLRFMT_RGB565(ovl);
 	case DRM_FORMAT_BGR565:
 		return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
 	case DRM_FORMAT_RGB888:
 		return OVL_CON_CLRFMT_RGB888(ovl);
 	case DRM_FORMAT_BGR888:
 		return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
 	case DRM_FORMAT_RGBX8888:
 	case DRM_FORMAT_RGBA8888:
 		return OVL_CON_CLRFMT_ARGB8888;
 	case DRM_FORMAT_BGRX8888:
 	case DRM_FORMAT_BGRA8888:
 		return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_ARGB8888:
 		return OVL_CON_CLRFMT_RGBA8888;
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ABGR8888:
 		return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
 	case DRM_FORMAT_UYVY:
 		return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
 	case DRM_FORMAT_YUYV:
 		return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB;
 	}
 }

 static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
 				 struct mtk_plane_state *state,
 				 struct cmdq_pkt *cmdq_pkt)
 {
 	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
 	struct mtk_plane_pending_state *pending = &state->pending;
 	unsigned int addr = pending->addr;
 	unsigned int pitch = pending->pitch & 0xffff;
 	unsigned int fmt = pending->format;
 	unsigned int offset = (pending->y << 16) | pending->x;
 	unsigned int src_size = (pending->height << 16) | pending->width;
 	unsigned int con;

 	if (!pending->enable) {
 		mtk_ovl_layer_off(comp, idx, cmdq_pkt);
 		return;
 	}

 	con = ovl_fmt_convert(ovl, fmt);
 	if (state->base.fb->format->has_alpha)
 		con |= OVL_CON_AEN | OVL_CON_ALPHA;

 	if (pending->rotation & DRM_MODE_REFLECT_Y) {
 		con |= OVL_CON_VIRT_FLIP;
 		addr += (pending->height - 1) * pending->pitch;
 	}

 	if (pending->rotation & DRM_MODE_REFLECT_X) {
 		con |= OVL_CON_HORZ_FLIP;
 		addr += pending->pitch - 1;
 	}

 	mtk_ddp_write_relaxed(cmdq_pkt, con, comp,
 			      DISP_REG_OVL_CON(idx));
 	mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp,
 			      DISP_REG_OVL_PITCH(idx));
 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp,
 			      DISP_REG_OVL_SRC_SIZE(idx));
 	mtk_ddp_write_relaxed(cmdq_pkt, offset, comp,
 			      DISP_REG_OVL_OFFSET(idx));
 	mtk_ddp_write_relaxed(cmdq_pkt, addr, comp,
 			      DISP_REG_OVL_ADDR(ovl, idx));

 	mtk_ovl_layer_on(comp, idx, cmdq_pkt);
 }

 static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
 {
 	unsigned int reg;

 	reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
 	reg = reg | OVL_BGCLR_SEL_IN;
 	writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
 }

 static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
 {
 	unsigned int reg;

 	reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
 	reg = reg & ~OVL_BGCLR_SEL_IN;
 	writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
 }

 static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
 	.config = mtk_ovl_config,
 	.start = mtk_ovl_start,
 	.stop = mtk_ovl_stop,
 	.enable_vblank = mtk_ovl_enable_vblank,
 	.disable_vblank = mtk_ovl_disable_vblank,
 	.supported_rotations = mtk_ovl_supported_rotations,
 	.layer_nr = mtk_ovl_layer_nr,
 	.layer_check = mtk_ovl_layer_check,
 	.layer_config = mtk_ovl_layer_config,
 	.bgclr_in_on = mtk_ovl_bgclr_in_on,
 	.bgclr_in_off = mtk_ovl_bgclr_in_off,
 };

 static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
 			     void *data)
 {
 	struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
 	struct drm_device *drm_dev = data;
 	int ret;

 	ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
 	if (ret < 0) {
 		dev_err(dev, "Failed to register component %pOF: %d\n",
 			dev->of_node, ret);
 		return ret;
 	}

 	return 0;
 }

 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
 				void *data)
 {
 	struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
 	struct drm_device *drm_dev = data;

 	mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
 }

 static const struct component_ops mtk_disp_ovl_component_ops = {
 	.bind	= mtk_disp_ovl_bind,
 	.unbind = mtk_disp_ovl_unbind,
 };

 static int mtk_disp_ovl_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct mtk_disp_ovl *priv;
 	int comp_id;
 	int irq;
 	int ret;

 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;

 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)
 		return irq;

 	priv->data = of_device_get_match_data(dev);

 	comp_id = mtk_ddp_comp_get_id(dev->of_node,
 				      priv->data->layer_nr == 4 ?
 				      MTK_DISP_OVL :
 				      MTK_DISP_OVL_2L);
 	if (comp_id < 0) {
 		dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
 		return comp_id;
 	}

 	ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
 				&mtk_disp_ovl_funcs);
 	if (ret) {
 		dev_err(dev, "Failed to initialize component: %d\n", ret);
 		return ret;
 	}

 	platform_set_drvdata(pdev, priv);

 	ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
 			       IRQF_TRIGGER_NONE, dev_name(dev), priv);
 	if (ret < 0) {
 		dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
 		return ret;
 	}

 	ret = component_add(dev, &mtk_disp_ovl_component_ops);
 	if (ret)
 		dev_err(dev, "Failed to add component: %d\n", ret);

 	return ret;
 }

 static int mtk_disp_ovl_remove(struct platform_device *pdev)
 {
 	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);

 	return 0;
 }

 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
 	.addr = DISP_REG_OVL_ADDR_MT2701,
 	.gmc_bits = 8,
 	.layer_nr = 4,
 	.fmt_rgb565_is_0 = false,
 };

 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
 	.addr = DISP_REG_OVL_ADDR_MT8173,
 	.gmc_bits = 8,
 	.layer_nr = 4,
 	.fmt_rgb565_is_0 = true,
 };

 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-ovl",
 	  .data = &mt2701_ovl_driver_data},
 	{ .compatible = "mediatek,mt8173-disp-ovl",
 	  .data = &mt8173_ovl_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);

 struct platform_driver mtk_disp_ovl_driver = {
 	.probe		= mtk_disp_ovl_probe,
 	.remove		= mtk_disp_ovl_remove,
 	.driver		= {
 		.name	= "mediatek-disp-ovl",
 		.owner	= THIS_MODULE,
 		.of_match_table = mtk_disp_ovl_driver_dt_match,
 	},
 };
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (c) 2015 MediaTek Inc.
	*/

	#include <drm/drm_fourcc.h>

	#include <linux/clk.h>
	#include <linux/component.h>
	#include <linux/module.h>
	#include <linux/of_device.h>
	#include <linux/of_irq.h>
	#include <linux/platform_device.h>
	#include <linux/soc/mediatek/mtk-cmdq.h>

	#include "mtk_drm_crtc.h"
	#include "mtk_drm_ddp_comp.h"

	#define DISP_REG_OVL_INTEN 0x0004
	#define OVL_FME_CPL_INT BIT(1)
	#define DISP_REG_OVL_INTSTA 0x0008
	#define DISP_REG_OVL_EN 0x000c
	#define DISP_REG_OVL_RST 0x0014
	#define DISP_REG_OVL_ROI_SIZE 0x0020
	#define DISP_REG_OVL_DATAPATH_CON 0x0024
	#define OVL_BGCLR_SEL_IN BIT(2)
	#define DISP_REG_OVL_ROI_BGCLR 0x0028
	#define DISP_REG_OVL_SRC_CON 0x002c
	#define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
	#define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n))
	#define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n))
	#define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
	#define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
	#define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
	#define DISP_REG_OVL_ADDR_MT2701 0x0040
	#define DISP_REG_OVL_ADDR_MT8173 0x0f40
	#define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))

	#define GMC_THRESHOLD_BITS 16
	#define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
	#define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8)

	#define OVL_CON_BYTE_SWAP BIT(24)
	#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
	#define OVL_CON_CLRFMT_RGB (1 << 12)
	#define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
	#define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
	#define OVL_CON_CLRFMT_UYVY (4 << 12)
	#define OVL_CON_CLRFMT_YUYV (5 << 12)
	#define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
	0 : OVL_CON_CLRFMT_RGB)
	#define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
	OVL_CON_CLRFMT_RGB : 0)
	#define OVL_CON_AEN BIT(8)
	#define OVL_CON_ALPHA 0xff
	#define OVL_CON_VIRT_FLIP BIT(9)
	#define OVL_CON_HORZ_FLIP BIT(10)

	struct mtk_disp_ovl_data {
	unsigned int addr;
	unsigned int gmc_bits;
	unsigned int layer_nr;
	bool fmt_rgb565_is_0;
	};

	/**
	* struct mtk_disp_ovl - DISP_OVL driver structure
	* @ddp_comp - structure containing type enum and hardware resources
	* @crtc - associated crtc to report vblank events to
	*/
	struct mtk_disp_ovl {
	struct mtk_ddp_comp ddp_comp;
	struct drm_crtc *crtc;
	const struct mtk_disp_ovl_data *data;
	};

	static inline struct mtk_disp_ovl comp_to_ovl(struct mtk_ddp_comp comp)
	{
	return container_of(comp, struct mtk_disp_ovl, ddp_comp);
	}

	static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
	{
	struct mtk_disp_ovl *priv = dev_id;
	struct mtk_ddp_comp *ovl = &priv->ddp_comp;

	/* Clear frame completion interrupt */
	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);

	if (!priv->crtc)
	return IRQ_NONE;

	mtk_crtc_ddp_irq(priv->crtc, ovl);

	return IRQ_HANDLED;
	}

	static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp,
	struct drm_crtc *crtc)
	{
	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);

	ovl->crtc = crtc;
	writel(0x0, comp->regs + DISP_REG_OVL_INTSTA);
	writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);
	}

	static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
	{
	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);

	ovl->crtc = NULL;
	writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN);
	}

	static void mtk_ovl_start(struct mtk_ddp_comp *comp)
	{
	writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
	}

	static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
	{
	writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN);
	}

	static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
	unsigned int h, unsigned int vrefresh,
	unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
	{
	if (w != 0 && h != 0)
	mtk_ddp_write_relaxed(cmdq_pkt, h << 16 \| w, comp,
	DISP_REG_OVL_ROI_SIZE);
	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);

	mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST);
	mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST);
	}

	static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
	{
	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);

	return ovl->data->layer_nr;
	}

	static unsigned int mtk_ovl_supported_rotations(struct mtk_ddp_comp *comp)
	{
	return DRM_MODE_ROTATE_0 \| DRM_MODE_ROTATE_180 \|
	DRM_MODE_REFLECT_X \| DRM_MODE_REFLECT_Y;
	}

	static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx,
	struct mtk_plane_state *mtk_state)
	{
	struct drm_plane_state *state = &mtk_state->base;
	unsigned int rotation = 0;

	rotation = drm_rotation_simplify(state->rotation,
	DRM_MODE_ROTATE_0 \|
	DRM_MODE_REFLECT_X \|
	DRM_MODE_REFLECT_Y);
	rotation &= ~DRM_MODE_ROTATE_0;

	/* We can only do reflection, not rotation */
	if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
	return -EINVAL;

	/*
	* TODO: Rotating/reflecting YUV buffers is not supported at this time.
	* Only RGB[AX] variants are supported.
	*/
	if (state->fb->format->is_yuv && rotation != 0)
	return -EINVAL;

	state->rotation = rotation;

	return 0;
	}

	static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
	struct cmdq_pkt *cmdq_pkt)
	{
	unsigned int gmc_thrshd_l;
	unsigned int gmc_thrshd_h;
	unsigned int gmc_value;
	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);

	mtk_ddp_write(cmdq_pkt, 0x1, comp,
	DISP_REG_OVL_RDMA_CTRL(idx));
	gmc_thrshd_l = GMC_THRESHOLD_LOW >>
	(GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
	gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
	(GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
	if (ovl->data->gmc_bits == 10)
	gmc_value = gmc_thrshd_h \| gmc_thrshd_h << 16;
	else
	gmc_value = gmc_thrshd_l \| gmc_thrshd_l << 8 \|
	gmc_thrshd_h << 16 \| gmc_thrshd_h << 24;
	mtk_ddp_write(cmdq_pkt, gmc_value,
	comp, DISP_REG_OVL_RDMA_GMC(idx));
	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp,
	DISP_REG_OVL_SRC_CON, BIT(idx));
	}

	static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,
	struct cmdq_pkt *cmdq_pkt)
	{
	mtk_ddp_write_mask(cmdq_pkt, 0, comp,
	DISP_REG_OVL_SRC_CON, BIT(idx));
	mtk_ddp_write(cmdq_pkt, 0, comp,
	DISP_REG_OVL_RDMA_CTRL(idx));
	}

	static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
	{
	/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
	* is defined in mediatek HW data sheet.
	* The alphabet order in XXX is no relation to data
	* arrangement in memory.
	*/
	switch (fmt) {
	default:
	case DRM_FORMAT_RGB565:
	return OVL_CON_CLRFMT_RGB565(ovl);
	case DRM_FORMAT_BGR565:
	return OVL_CON_CLRFMT_RGB565(ovl) \| OVL_CON_BYTE_SWAP;
	case DRM_FORMAT_RGB888:
	return OVL_CON_CLRFMT_RGB888(ovl);
	case DRM_FORMAT_BGR888:
	return OVL_CON_CLRFMT_RGB888(ovl) \| OVL_CON_BYTE_SWAP;
	case DRM_FORMAT_RGBX8888:
	case DRM_FORMAT_RGBA8888:
	return OVL_CON_CLRFMT_ARGB8888;
	case DRM_FORMAT_BGRX8888:
	case DRM_FORMAT_BGRA8888:
	return OVL_CON_CLRFMT_ARGB8888 \| OVL_CON_BYTE_SWAP;
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
	return OVL_CON_CLRFMT_RGBA8888;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
	return OVL_CON_CLRFMT_RGBA8888 \| OVL_CON_BYTE_SWAP;
	case DRM_FORMAT_UYVY:
	return OVL_CON_CLRFMT_UYVY \| OVL_CON_MTX_YUV_TO_RGB;
	case DRM_FORMAT_YUYV:
	return OVL_CON_CLRFMT_YUYV \| OVL_CON_MTX_YUV_TO_RGB;
	}
	}

	static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
	struct mtk_plane_state *state,
	struct cmdq_pkt *cmdq_pkt)
	{
	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
	struct mtk_plane_pending_state *pending = &state->pending;
	unsigned int addr = pending->addr;
	unsigned int pitch = pending->pitch & 0xffff;
	unsigned int fmt = pending->format;
	unsigned int offset = (pending->y << 16) \| pending->x;
	unsigned int src_size = (pending->height << 16) \| pending->width;
	unsigned int con;

	if (!pending->enable) {
	mtk_ovl_layer_off(comp, idx, cmdq_pkt);
	return;
	}

	con = ovl_fmt_convert(ovl, fmt);
	if (state->base.fb->format->has_alpha)
	con \|= OVL_CON_AEN \| OVL_CON_ALPHA;

	if (pending->rotation & DRM_MODE_REFLECT_Y) {
	con \|= OVL_CON_VIRT_FLIP;
	addr += (pending->height - 1) * pending->pitch;
	}

	if (pending->rotation & DRM_MODE_REFLECT_X) {
	con \|= OVL_CON_HORZ_FLIP;
	addr += pending->pitch - 1;
	}

	mtk_ddp_write_relaxed(cmdq_pkt, con, comp,
	DISP_REG_OVL_CON(idx));
	mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp,
	DISP_REG_OVL_PITCH(idx));
	mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp,
	DISP_REG_OVL_SRC_SIZE(idx));
	mtk_ddp_write_relaxed(cmdq_pkt, offset, comp,
	DISP_REG_OVL_OFFSET(idx));
	mtk_ddp_write_relaxed(cmdq_pkt, addr, comp,
	DISP_REG_OVL_ADDR(ovl, idx));

	mtk_ovl_layer_on(comp, idx, cmdq_pkt);
	}

	static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
	{
	unsigned int reg;

	reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
	reg = reg \| OVL_BGCLR_SEL_IN;
	writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
	}

	static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
	{
	unsigned int reg;

	reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
	reg = reg & ~OVL_BGCLR_SEL_IN;
	writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
	}

	static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
	.config = mtk_ovl_config,
	.start = mtk_ovl_start,
	.stop = mtk_ovl_stop,
	.enable_vblank = mtk_ovl_enable_vblank,
	.disable_vblank = mtk_ovl_disable_vblank,
	.supported_rotations = mtk_ovl_supported_rotations,
	.layer_nr = mtk_ovl_layer_nr,
	.layer_check = mtk_ovl_layer_check,
	.layer_config = mtk_ovl_layer_config,
	.bgclr_in_on = mtk_ovl_bgclr_in_on,
	.bgclr_in_off = mtk_ovl_bgclr_in_off,
	};

	static int mtk_disp_ovl_bind(struct device dev, struct device master,
	void *data)
	{
	struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
	struct drm_device *drm_dev = data;
	int ret;

	ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
	if (ret < 0) {
	dev_err(dev, "Failed to register component %pOF: %d\n",
	dev->of_node, ret);
	return ret;
	}

	return 0;
	}

	static void mtk_disp_ovl_unbind(struct device dev, struct device master,
	void *data)
	{
	struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
	struct drm_device *drm_dev = data;

	mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
	}

	static const struct component_ops mtk_disp_ovl_component_ops = {
	.bind = mtk_disp_ovl_bind,
	.unbind = mtk_disp_ovl_unbind,
	};

	static int mtk_disp_ovl_probe(struct platform_device *pdev)
	{
	struct device *dev = &pdev->dev;
	struct mtk_disp_ovl *priv;
	int comp_id;
	int irq;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
	return -ENOMEM;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
	return irq;

	priv->data = of_device_get_match_data(dev);

	comp_id = mtk_ddp_comp_get_id(dev->of_node,
	priv->data->layer_nr == 4 ?
	MTK_DISP_OVL :
	MTK_DISP_OVL_2L);
	if (comp_id < 0) {
	dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
	return comp_id;
	}

	ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
	&mtk_disp_ovl_funcs);
	if (ret) {
	dev_err(dev, "Failed to initialize component: %d\n", ret);
	return ret;
	}

	platform_set_drvdata(pdev, priv);

	ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
	IRQF_TRIGGER_NONE, dev_name(dev), priv);
	if (ret < 0) {
	dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
	return ret;
	}

	ret = component_add(dev, &mtk_disp_ovl_component_ops);
	if (ret)
	dev_err(dev, "Failed to add component: %d\n", ret);

	return ret;
	}

	static int mtk_disp_ovl_remove(struct platform_device *pdev)
	{
	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);

	return 0;
	}

	static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
	.addr = DISP_REG_OVL_ADDR_MT2701,
	.gmc_bits = 8,
	.layer_nr = 4,
	.fmt_rgb565_is_0 = false,
	};

	static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
	.addr = DISP_REG_OVL_ADDR_MT8173,
	.gmc_bits = 8,
	.layer_nr = 4,
	.fmt_rgb565_is_0 = true,
	};

	static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
	{ .compatible = "mediatek,mt2701-disp-ovl",
	.data = &mt2701_ovl_driver_data},
	{ .compatible = "mediatek,mt8173-disp-ovl",
	.data = &mt8173_ovl_driver_data},
	{},
	};
	MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);

	struct platform_driver mtk_disp_ovl_driver = {
	.probe = mtk_disp_ovl_probe,
	.remove = mtk_disp_ovl_remove,
	.driver = {
	.name = "mediatek-disp-ovl",
	.owner = THIS_MODULE,
	.of_match_table = mtk_disp_ovl_driver_dt_match,
	},
	};