| Binding for the HSDK Generic PLL clock | 
 |  | 
 | This binding uses the common clock binding[1]. | 
 |  | 
 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | 
 |  | 
 | Required properties: | 
 | - compatible: should be "snps,hsdk-<name>-pll-clock" | 
 |   "snps,hsdk-core-pll-clock" | 
 |   "snps,hsdk-gp-pll-clock" | 
 |   "snps,hsdk-hdmi-pll-clock" | 
 | - reg : should contain base register location and length. | 
 | - clocks: shall be the input parent clock phandle for the PLL. | 
 | - #clock-cells: from common clock binding; Should always be set to 0. | 
 |  | 
 | Example: | 
 | 	input_clk: input-clk { | 
 | 		clock-frequency = <33333333>; | 
 | 		compatible = "fixed-clock"; | 
 | 		#clock-cells = <0>; | 
 | 	}; | 
 |  | 
 | 	cpu_clk: cpu-clk@0 { | 
 | 		compatible = "snps,hsdk-core-pll-clock"; | 
 | 		reg = <0x00 0x10>; | 
 | 		#clock-cells = <0>; | 
 | 		clocks = <&input_clk>; | 
 | 	}; |