| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| /* |
| * AM335x ICE V2 board |
| * http://www.ti.com/tool/tmdsice3359 |
| */ |
| |
| /dts-v1/; |
| |
| #include "am33xx.dtsi" |
| |
| / { |
| model = "TI AM3359 ICE-V2"; |
| compatible = "ti,am3359-icev2", "ti,am33xx"; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0x10000000>; /* 256 MB */ |
| }; |
| |
| chosen { |
| stdout-path = &uart3; |
| }; |
| |
| vbat: fixedregulator0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vbat"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-boot-on; |
| }; |
| |
| vtt_fixed: fixedregulator1 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vtt"; |
| regulator-min-microvolt = <1500000>; |
| regulator-max-microvolt = <1500000>; |
| gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; |
| regulator-always-on; |
| regulator-boot-on; |
| enable-active-high; |
| }; |
| |
| leds-iio { |
| status = "disabled"; |
| compatible = "gpio-leds"; |
| led-out0 { |
| label = "out0"; |
| gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-out1 { |
| label = "out1"; |
| gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-out2 { |
| label = "out2"; |
| gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-out3 { |
| label = "out3"; |
| gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-out4 { |
| label = "out4"; |
| gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-out5 { |
| label = "out5"; |
| gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-out6 { |
| label = "out6"; |
| gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-out7 { |
| label = "out7"; |
| gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| }; |
| |
| /* Tricolor status LEDs */ |
| leds1 { |
| compatible = "gpio-leds"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&user_leds>; |
| |
| led0 { |
| label = "status0:red:cpu0"; |
| gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| linux,default-trigger = "cpu0"; |
| }; |
| |
| led1 { |
| label = "status0:green:usr"; |
| gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led2 { |
| label = "status0:yellow:usr"; |
| gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led3 { |
| label = "status1:red:mmc0"; |
| gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| linux,default-trigger = "mmc0"; |
| }; |
| |
| led4 { |
| label = "status1:green:usr"; |
| gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led5 { |
| label = "status1:yellow:usr"; |
| gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| }; |
| gpio-decoder { |
| compatible = "gpio-decoder"; |
| gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, |
| <&pca9536 2 GPIO_ACTIVE_HIGH>, |
| <&pca9536 1 GPIO_ACTIVE_HIGH>, |
| <&pca9536 0 GPIO_ACTIVE_HIGH>; |
| linux,axis = <0>; /* ABS_X */ |
| decoder-max-value = <9>; |
| }; |
| }; |
| |
| &am33xx_pinmux { |
| user_leds: user_leds { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ |
| AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ |
| AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ |
| AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ |
| AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ |
| AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ |
| >; |
| }; |
| |
| mmc0_pins_default: mmc0_pins_default { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) |
| >; |
| }; |
| |
| i2c0_pins_default: i2c0_pins_default { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) |
| >; |
| }; |
| |
| spi0_pins_default: spi0_pins_default { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ |
| >; |
| }; |
| |
| uart3_pins_default: uart3_pins_default { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ |
| AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ |
| >; |
| }; |
| |
| cpsw_default: cpsw_default { |
| pinctrl-single,pins = < |
| /* Slave 1, RMII mode */ |
| AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ |
| AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ |
| AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ |
| AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ |
| AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ |
| /* Slave 2, RMII mode */ |
| AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ |
| AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_col.rmii2_refclk */ |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ |
| AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a0.rmii2_txen */ |
| >; |
| }; |
| |
| cpsw_sleep: cpsw_sleep { |
| pinctrl-single,pins = < |
| /* Slave 1 reset value */ |
| AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| |
| /* Slave 2 reset value */ |
| AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| >; |
| }; |
| |
| davinci_mdio_default: davinci_mdio_default { |
| pinctrl-single,pins = < |
| /* MDIO */ |
| AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) |
| >; |
| }; |
| |
| davinci_mdio_sleep: davinci_mdio_sleep { |
| pinctrl-single,pins = < |
| /* MDIO reset value */ |
| AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| >; |
| }; |
| }; |
| |
| &i2c0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_pins_default>; |
| |
| status = "okay"; |
| clock-frequency = <400000>; |
| |
| tps: power-controller@2d { |
| reg = <0x2d>; |
| }; |
| |
| tpic2810: gpio@60 { |
| compatible = "ti,tpic2810"; |
| reg = <0x60>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| pca9536: gpio@41 { |
| compatible = "ti,pca9536"; |
| reg = <0x41>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| /* osd9616p0899-10 */ |
| display@3c { |
| compatible = "solomon,ssd1306fb-i2c"; |
| reg = <0x3c>; |
| solomon,height = <16>; |
| solomon,width = <96>; |
| solomon,com-seq; |
| solomon,com-invdir; |
| solomon,page-offset = <0>; |
| solomon,prechargep1 = <2>; |
| solomon,prechargep2 = <13>; |
| }; |
| }; |
| |
| &spi0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi0_pins_default>; |
| |
| sn65hvs882@1 { |
| compatible = "pisosr-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; |
| |
| reg = <1>; |
| spi-max-frequency = <1000000>; |
| spi-cpol; |
| }; |
| |
| spi_nor: flash@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "winbond,w25q64", "jedec,spi-nor"; |
| spi-max-frequency = <80000000>; |
| m25p,fast-read; |
| reg = <0>; |
| |
| partition@0 { |
| label = "u-boot-spl"; |
| reg = <0x0 0x80000>; |
| read-only; |
| }; |
| |
| partition@1 { |
| label = "u-boot"; |
| reg = <0x80000 0x100000>; |
| read-only; |
| }; |
| |
| partition@2 { |
| label = "u-boot-env"; |
| reg = <0x180000 0x20000>; |
| read-only; |
| }; |
| |
| partition@3 { |
| label = "misc"; |
| reg = <0x1A0000 0x660000>; |
| }; |
| }; |
| |
| }; |
| |
| &tscadc { |
| status = "okay"; |
| adc { |
| ti,adc-channels = <1 2 3 4 5 6 7>; |
| }; |
| }; |
| |
| #include "tps65910.dtsi" |
| |
| &tps { |
| vcc1-supply = <&vbat>; |
| vcc2-supply = <&vbat>; |
| vcc3-supply = <&vbat>; |
| vcc4-supply = <&vbat>; |
| vcc5-supply = <&vbat>; |
| vcc6-supply = <&vbat>; |
| vcc7-supply = <&vbat>; |
| vccio-supply = <&vbat>; |
| |
| regulators { |
| vrtc_reg: regulator@0 { |
| regulator-always-on; |
| }; |
| |
| vio_reg: regulator@1 { |
| regulator-always-on; |
| }; |
| |
| vdd1_reg: regulator@2 { |
| regulator-name = "vdd_mpu"; |
| regulator-min-microvolt = <912500>; |
| regulator-max-microvolt = <1326000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vdd2_reg: regulator@3 { |
| regulator-name = "vdd_core"; |
| regulator-min-microvolt = <912500>; |
| regulator-max-microvolt = <1144000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vdd3_reg: regulator@4 { |
| regulator-always-on; |
| }; |
| |
| vdig1_reg: regulator@5 { |
| regulator-always-on; |
| }; |
| |
| vdig2_reg: regulator@6 { |
| regulator-always-on; |
| }; |
| |
| vpll_reg: regulator@7 { |
| regulator-always-on; |
| }; |
| |
| vdac_reg: regulator@8 { |
| regulator-always-on; |
| }; |
| |
| vaux1_reg: regulator@9 { |
| regulator-always-on; |
| }; |
| |
| vaux2_reg: regulator@10 { |
| regulator-always-on; |
| }; |
| |
| vaux33_reg: regulator@11 { |
| regulator-always-on; |
| }; |
| |
| vmmc_reg: regulator@12 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| &mmc1 { |
| status = "okay"; |
| vmmc-supply = <&vmmc_reg>; |
| bus-width = <4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc0_pins_default>; |
| }; |
| |
| &gpio0_target { |
| /* Do not idle the GPIO used for holding the VTT regulator */ |
| ti,no-reset-on-init; |
| ti,no-idle-on-init; |
| }; |
| |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart3_pins_default>; |
| status = "okay"; |
| }; |
| |
| &gpio3 { |
| pr1-mii-ctl-hog { |
| gpio-hog; |
| gpios = <4 GPIO_ACTIVE_HIGH>; |
| output-high; |
| line-name = "PR1_MII_CTRL"; |
| }; |
| |
| mux-mii-hog { |
| gpio-hog; |
| gpios = <10 GPIO_ACTIVE_HIGH>; |
| /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ |
| output-high; |
| line-name = "MUX_MII_CTL1"; |
| }; |
| }; |
| |
| &cpsw_port1 { |
| phy-handle = <ðphy0>; |
| phy-mode = "rmii"; |
| ti,dual-emac-pvid = <1>; |
| }; |
| |
| &cpsw_port2 { |
| phy-handle = <ðphy1>; |
| phy-mode = "rmii"; |
| ti,dual-emac-pvid = <2>; |
| }; |
| |
| &mac_sw { |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&cpsw_default>; |
| pinctrl-1 = <&cpsw_sleep>; |
| status = "okay"; |
| }; |
| |
| &davinci_mdio_sw { |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&davinci_mdio_default>; |
| pinctrl-1 = <&davinci_mdio_sleep>; |
| reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; |
| reset-delay-us = <2>; /* PHY datasheet states 1uS min */ |
| |
| ethphy0: ethernet-phy@1 { |
| reg = <1>; |
| }; |
| |
| ethphy1: ethernet-phy@3 { |
| reg = <3>; |
| }; |
| }; |
