| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ | |
| /* | |
| * Copyright (c) 2018-2023, The Linux Foundation. All rights reserved. | |
| */ | |
| #ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H | |
| #define _DT_BINDINGS_RESET_IPQ_GCC_9574_H | |
| #define GCC_ADSS_BCR 0 | |
| #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 1 | |
| #define GCC_BLSP1_BCR 2 | |
| #define GCC_BLSP1_QUP1_BCR 3 | |
| #define GCC_BLSP1_QUP2_BCR 4 | |
| #define GCC_BLSP1_QUP3_BCR 5 | |
| #define GCC_BLSP1_QUP4_BCR 6 | |
| #define GCC_BLSP1_QUP5_BCR 7 | |
| #define GCC_BLSP1_QUP6_BCR 8 | |
| #define GCC_BLSP1_UART1_BCR 9 | |
| #define GCC_BLSP1_UART2_BCR 10 | |
| #define GCC_BLSP1_UART3_BCR 11 | |
| #define GCC_BLSP1_UART4_BCR 12 | |
| #define GCC_BLSP1_UART5_BCR 13 | |
| #define GCC_BLSP1_UART6_BCR 14 | |
| #define GCC_BOOT_ROM_BCR 15 | |
| #define GCC_MDIO_BCR 16 | |
| #define GCC_NSS_BCR 17 | |
| #define GCC_NSS_TBU_BCR 18 | |
| #define GCC_PCIE0_BCR 19 | |
| #define GCC_PCIE0_LINK_DOWN_BCR 20 | |
| #define GCC_PCIE0_PHY_BCR 21 | |
| #define GCC_PCIE0PHY_PHY_BCR 22 | |
| #define GCC_PCIE1_BCR 23 | |
| #define GCC_PCIE1_LINK_DOWN_BCR 24 | |
| #define GCC_PCIE1_PHY_BCR 25 | |
| #define GCC_PCIE1PHY_PHY_BCR 26 | |
| #define GCC_PCIE2_BCR 27 | |
| #define GCC_PCIE2_LINK_DOWN_BCR 28 | |
| #define GCC_PCIE2_PHY_BCR 29 | |
| #define GCC_PCIE2PHY_PHY_BCR 30 | |
| #define GCC_PCIE3_BCR 31 | |
| #define GCC_PCIE3_LINK_DOWN_BCR 32 | |
| #define GCC_PCIE3_PHY_BCR 33 | |
| #define GCC_PCIE3PHY_PHY_BCR 34 | |
| #define GCC_PRNG_BCR 35 | |
| #define GCC_QUSB2_0_PHY_BCR 36 | |
| #define GCC_SDCC_BCR 37 | |
| #define GCC_TLMM_BCR 38 | |
| #define GCC_UNIPHY0_BCR 39 | |
| #define GCC_UNIPHY1_BCR 40 | |
| #define GCC_UNIPHY2_BCR 41 | |
| #define GCC_USB0_PHY_BCR 42 | |
| #define GCC_USB3PHY_0_PHY_BCR 43 | |
| #define GCC_USB_BCR 44 | |
| #define GCC_ANOC0_TBU_BCR 45 | |
| #define GCC_ANOC1_TBU_BCR 46 | |
| #define GCC_ANOC_BCR 47 | |
| #define GCC_APSS_TCU_BCR 48 | |
| #define GCC_CMN_BLK_BCR 49 | |
| #define GCC_CMN_BLK_AHB_ARES 50 | |
| #define GCC_CMN_BLK_SYS_ARES 51 | |
| #define GCC_CMN_BLK_APU_ARES 52 | |
| #define GCC_DCC_BCR 53 | |
| #define GCC_DDRSS_BCR 54 | |
| #define GCC_IMEM_BCR 55 | |
| #define GCC_LPASS_BCR 56 | |
| #define GCC_MPM_BCR 57 | |
| #define GCC_MSG_RAM_BCR 58 | |
| #define GCC_NSSNOC_MEMNOC_1_ARES 59 | |
| #define GCC_NSSNOC_PCNOC_1_ARES 60 | |
| #define GCC_NSSNOC_SNOC_1_ARES 61 | |
| #define GCC_NSSNOC_XO_DCD_ARES 62 | |
| #define GCC_NSSNOC_TS_ARES 63 | |
| #define GCC_NSSCC_ARES 64 | |
| #define GCC_NSSNOC_NSSCC_ARES 65 | |
| #define GCC_NSSNOC_ATB_ARES 66 | |
| #define GCC_NSSNOC_MEMNOC_ARES 67 | |
| #define GCC_NSSNOC_QOSGEN_REF_ARES 68 | |
| #define GCC_NSSNOC_SNOC_ARES 69 | |
| #define GCC_NSSNOC_TIMEOUT_REF_ARES 70 | |
| #define GCC_NSS_CFG_ARES 71 | |
| #define GCC_UBI0_DBG_ARES 72 | |
| #define GCC_PCIE0_AHB_ARES 73 | |
| #define GCC_PCIE0_AUX_ARES 74 | |
| #define GCC_PCIE0_AXI_M_ARES 75 | |
| #define GCC_PCIE0_AXI_M_STICKY_ARES 76 | |
| #define GCC_PCIE0_AXI_S_ARES 77 | |
| #define GCC_PCIE0_AXI_S_STICKY_ARES 78 | |
| #define GCC_PCIE0_CORE_STICKY_ARES 79 | |
| #define GCC_PCIE0_PIPE_ARES 80 | |
| #define GCC_PCIE1_AHB_ARES 81 | |
| #define GCC_PCIE1_AUX_ARES 82 | |
| #define GCC_PCIE1_AXI_M_ARES 83 | |
| #define GCC_PCIE1_AXI_M_STICKY_ARES 84 | |
| #define GCC_PCIE1_AXI_S_ARES 85 | |
| #define GCC_PCIE1_AXI_S_STICKY_ARES 86 | |
| #define GCC_PCIE1_CORE_STICKY_ARES 87 | |
| #define GCC_PCIE1_PIPE_ARES 88 | |
| #define GCC_PCIE2_AHB_ARES 89 | |
| #define GCC_PCIE2_AUX_ARES 90 | |
| #define GCC_PCIE2_AXI_M_ARES 91 | |
| #define GCC_PCIE2_AXI_M_STICKY_ARES 92 | |
| #define GCC_PCIE2_AXI_S_ARES 93 | |
| #define GCC_PCIE2_AXI_S_STICKY_ARES 94 | |
| #define GCC_PCIE2_CORE_STICKY_ARES 95 | |
| #define GCC_PCIE2_PIPE_ARES 96 | |
| #define GCC_PCIE3_AHB_ARES 97 | |
| #define GCC_PCIE3_AUX_ARES 98 | |
| #define GCC_PCIE3_AXI_M_ARES 99 | |
| #define GCC_PCIE3_AXI_M_STICKY_ARES 100 | |
| #define GCC_PCIE3_AXI_S_ARES 101 | |
| #define GCC_PCIE3_AXI_S_STICKY_ARES 102 | |
| #define GCC_PCIE3_CORE_STICKY_ARES 103 | |
| #define GCC_PCIE3_PIPE_ARES 104 | |
| #define GCC_PCNOC_BCR 105 | |
| #define GCC_PCNOC_BUS_TIMEOUT0_BCR 106 | |
| #define GCC_PCNOC_BUS_TIMEOUT1_BCR 107 | |
| #define GCC_PCNOC_BUS_TIMEOUT2_BCR 108 | |
| #define GCC_PCNOC_BUS_TIMEOUT3_BCR 109 | |
| #define GCC_PCNOC_BUS_TIMEOUT4_BCR 110 | |
| #define GCC_PCNOC_BUS_TIMEOUT5_BCR 111 | |
| #define GCC_PCNOC_BUS_TIMEOUT6_BCR 112 | |
| #define GCC_PCNOC_BUS_TIMEOUT7_BCR 113 | |
| #define GCC_PCNOC_BUS_TIMEOUT8_BCR 114 | |
| #define GCC_PCNOC_BUS_TIMEOUT9_BCR 115 | |
| #define GCC_PCNOC_TBU_BCR 116 | |
| #define GCC_Q6SS_DBG_ARES 117 | |
| #define GCC_Q6_AHB_ARES 118 | |
| #define GCC_Q6_AHB_S_ARES 119 | |
| #define GCC_Q6_AXIM2_ARES 120 | |
| #define GCC_Q6_AXIM_ARES 121 | |
| #define GCC_QDSS_BCR 122 | |
| #define GCC_QPIC_BCR 123 | |
| #define GCC_QPIC_AHB_ARES 124 | |
| #define GCC_QPIC_ARES 125 | |
| #define GCC_RBCPR_BCR 126 | |
| #define GCC_RBCPR_MX_BCR 127 | |
| #define GCC_SEC_CTRL_BCR 128 | |
| #define GCC_SMMU_CFG_BCR 129 | |
| #define GCC_SNOC_BCR 130 | |
| #define GCC_SPDM_BCR 131 | |
| #define GCC_TME_BCR 132 | |
| #define GCC_UNIPHY0_SYS_RESET 133 | |
| #define GCC_UNIPHY0_AHB_RESET 134 | |
| #define GCC_UNIPHY0_XPCS_RESET 135 | |
| #define GCC_UNIPHY1_SYS_RESET 136 | |
| #define GCC_UNIPHY1_AHB_RESET 137 | |
| #define GCC_UNIPHY1_XPCS_RESET 138 | |
| #define GCC_UNIPHY2_SYS_RESET 139 | |
| #define GCC_UNIPHY2_AHB_RESET 140 | |
| #define GCC_UNIPHY2_XPCS_RESET 141 | |
| #define GCC_USB_MISC_RESET 142 | |
| #define GCC_WCSSAON_RESET 143 | |
| #define GCC_WCSS_ACMT_ARES 144 | |
| #define GCC_WCSS_AHB_S_ARES 145 | |
| #define GCC_WCSS_AXI_M_ARES 146 | |
| #define GCC_WCSS_BCR 147 | |
| #define GCC_WCSS_DBG_ARES 148 | |
| #define GCC_WCSS_DBG_BDG_ARES 149 | |
| #define GCC_WCSS_ECAHB_ARES 150 | |
| #define GCC_WCSS_Q6_BCR 151 | |
| #define GCC_WCSS_Q6_TBU_BCR 152 | |
| #define GCC_TCSR_BCR 153 | |
| #define GCC_CRYPTO_BCR 154 | |
| #endif |