include/dt-bindings/clock/qcom,sa8775p-dispcc.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
#define _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H

/* DISP_CC_0/1 clocks */
#define MDSS_DISP_CC_MDSS_AHB1_CLK				0
#define MDSS_DISP_CC_MDSS_AHB_CLK				1
#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC				2
#define MDSS_DISP_CC_MDSS_BYTE0_CLK				3
#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC				4
#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC			5
#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK			6
#define MDSS_DISP_CC_MDSS_BYTE1_CLK				7
#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC				8
#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC			9
#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK			10
#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK				11
#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC			12
#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK			13
#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC			14
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK			15
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC			16
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC		17
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK			18
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK			19
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC			20
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK			21
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC			22
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK			23
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC			24
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK			25
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC			26
#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK	27
#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK				28
#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC			29
#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK			30
#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC			31
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK			32
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC			33
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC		34
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK			35
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK			36
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC			37
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK			38
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC			39
#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK	40
#define MDSS_DISP_CC_MDSS_ESC0_CLK				41
#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC				42
#define MDSS_DISP_CC_MDSS_ESC1_CLK				43
#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC				44
#define MDSS_DISP_CC_MDSS_MDP1_CLK				45
#define MDSS_DISP_CC_MDSS_MDP_CLK				46
#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC				47
#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK				48
#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK				49
#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK			50
#define MDSS_DISP_CC_MDSS_PCLK0_CLK				51
#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC				52
#define MDSS_DISP_CC_MDSS_PCLK1_CLK				53
#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC				54
#define MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK			55
#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK				56
#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK			57
#define MDSS_DISP_CC_MDSS_VSYNC1_CLK				58
#define MDSS_DISP_CC_MDSS_VSYNC_CLK				59
#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC				60
#define MDSS_DISP_CC_PLL0					61
#define MDSS_DISP_CC_PLL1					62
#define MDSS_DISP_CC_SLEEP_CLK					63
#define MDSS_DISP_CC_SLEEP_CLK_SRC				64
#define MDSS_DISP_CC_SM_OBS_CLK					65
#define MDSS_DISP_CC_XO_CLK					66
#define MDSS_DISP_CC_XO_CLK_SRC					67

/* DISP_CC_0/1 power domains */
#define MDSS_DISP_CC_MDSS_CORE_GDSC				0
#define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC			1

/* DISP_CC_0/1 resets */
#define MDSS_DISP_CC_MDSS_CORE_BCR				0
#define MDSS_DISP_CC_MDSS_RSCC_BCR				1

#endif