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Thomas Gleixnerd94d71c2019-05-29 07:12:40 -07001// SPDX-License-Identifier: GPL-2.0-only
Alexander Grafc215c6e2009-10-30 05:47:14 +00002/*
Alexander Grafc215c6e2009-10-30 05:47:14 +00003 *
4 * Copyright SUSE Linux Products GmbH 2009
5 *
6 * Authors: Alexander Graf <agraf@suse.de>
7 */
8
9#include <asm/kvm_ppc.h>
10#include <asm/disassemble.h>
11#include <asm/kvm_book3s.h>
12#include <asm/reg.h>
Benjamin Herrenschmidt95327d02012-04-01 17:35:53 +000013#include <asm/switch_to.h>
Paul Mackerrasb0a94d42012-11-04 18:15:43 +000014#include <asm/time.h>
Simon Guo57063402018-05-23 15:02:01 +080015#include <asm/tm.h>
Thomas Huth5358a962015-05-22 09:25:02 +020016#include "book3s.h"
Simon Guo533082a2018-05-23 15:02:00 +080017#include <asm/asm-prototypes.h>
Alexander Grafc215c6e2009-10-30 05:47:14 +000018
19#define OP_19_XOP_RFID 18
20#define OP_19_XOP_RFI 50
21
22#define OP_31_XOP_MFMSR 83
23#define OP_31_XOP_MTMSR 146
24#define OP_31_XOP_MTMSRD 178
Alexander Graf71db4082010-02-19 11:00:37 +010025#define OP_31_XOP_MTSR 210
Alexander Grafc215c6e2009-10-30 05:47:14 +000026#define OP_31_XOP_MTSRIN 242
27#define OP_31_XOP_TLBIEL 274
Alexander Graf50c7bb82012-12-14 23:42:05 +010028/* Opcode is officially reserved, reuse it as sc 1 when sc 1 doesn't trap */
29#define OP_31_XOP_FAKE_SC1 308
Alexander Grafc215c6e2009-10-30 05:47:14 +000030#define OP_31_XOP_SLBMTE 402
31#define OP_31_XOP_SLBIE 434
32#define OP_31_XOP_SLBIA 498
Alexander Grafc6648762010-03-24 21:48:24 +010033#define OP_31_XOP_MFSR 595
Alexander Grafc215c6e2009-10-30 05:47:14 +000034#define OP_31_XOP_MFSRIN 659
Alexander Grafbd7cdbb2010-03-24 21:48:33 +010035#define OP_31_XOP_DCBA 758
Alexander Grafc215c6e2009-10-30 05:47:14 +000036#define OP_31_XOP_SLBMFEV 851
37#define OP_31_XOP_EIOIO 854
38#define OP_31_XOP_SLBMFEE 915
Paul Mackerras41a86452019-02-04 19:06:18 +110039#define OP_31_XOP_SLBFEE 979
Alexander Grafc215c6e2009-10-30 05:47:14 +000040
Simon Guo57063402018-05-23 15:02:01 +080041#define OP_31_XOP_TBEGIN 654
Simon Guo26798f82018-05-23 15:02:05 +080042#define OP_31_XOP_TABORT 910
Simon Guo57063402018-05-23 15:02:01 +080043
Simon Guo03c81682018-05-23 15:02:03 +080044#define OP_31_XOP_TRECLAIM 942
Simon Guoe32c53d2018-05-23 15:02:04 +080045#define OP_31_XOP_TRCHKPT 1006
Simon Guo03c81682018-05-23 15:02:03 +080046
Alexander Grafc215c6e2009-10-30 05:47:14 +000047/* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */
48#define OP_31_XOP_DCBZ 1010
49
Alexander Grafca7f4202010-03-24 21:48:28 +010050#define OP_LFS 48
51#define OP_LFD 50
52#define OP_STFS 52
53#define OP_STFD 54
54
Alexander Grafd6d549b2010-02-19 11:00:33 +010055#define SPRN_GQR0 912
56#define SPRN_GQR1 913
57#define SPRN_GQR2 914
58#define SPRN_GQR3 915
59#define SPRN_GQR4 916
60#define SPRN_GQR5 917
61#define SPRN_GQR6 918
62#define SPRN_GQR7 919
63
Alexander Graf317a8fa2011-08-08 16:07:16 +020064enum priv_level {
65 PRIV_PROBLEM = 0,
66 PRIV_SUPER = 1,
67 PRIV_HYPER = 2,
68};
69
70static bool spr_allowed(struct kvm_vcpu *vcpu, enum priv_level level)
71{
72 /* PAPR VMs only access supervisor SPRs */
73 if (vcpu->arch.papr_enabled && (level > PRIV_SUPER))
74 return false;
75
76 /* Limit user space to its own small SPR set */
Alexander Graf5deb8e72014-04-24 13:46:24 +020077 if ((kvmppc_get_msr(vcpu) & MSR_PR) && level > PRIV_PROBLEM)
Alexander Graf317a8fa2011-08-08 16:07:16 +020078 return false;
79
80 return true;
81}
82
Simon Guode7ad932018-05-23 15:01:56 +080083#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
84static inline void kvmppc_copyto_vcpu_tm(struct kvm_vcpu *vcpu)
85{
86 memcpy(&vcpu->arch.gpr_tm[0], &vcpu->arch.regs.gpr[0],
87 sizeof(vcpu->arch.gpr_tm));
88 memcpy(&vcpu->arch.fp_tm, &vcpu->arch.fp,
89 sizeof(struct thread_fp_state));
90 memcpy(&vcpu->arch.vr_tm, &vcpu->arch.vr,
91 sizeof(struct thread_vr_state));
92 vcpu->arch.ppr_tm = vcpu->arch.ppr;
93 vcpu->arch.dscr_tm = vcpu->arch.dscr;
94 vcpu->arch.amr_tm = vcpu->arch.amr;
95 vcpu->arch.ctr_tm = vcpu->arch.regs.ctr;
96 vcpu->arch.tar_tm = vcpu->arch.tar;
97 vcpu->arch.lr_tm = vcpu->arch.regs.link;
Paul Mackerrasfd0944b2018-10-08 16:30:58 +110098 vcpu->arch.cr_tm = vcpu->arch.regs.ccr;
Simon Guode7ad932018-05-23 15:01:56 +080099 vcpu->arch.xer_tm = vcpu->arch.regs.xer;
100 vcpu->arch.vrsave_tm = vcpu->arch.vrsave;
101}
102
103static inline void kvmppc_copyfrom_vcpu_tm(struct kvm_vcpu *vcpu)
104{
105 memcpy(&vcpu->arch.regs.gpr[0], &vcpu->arch.gpr_tm[0],
106 sizeof(vcpu->arch.regs.gpr));
107 memcpy(&vcpu->arch.fp, &vcpu->arch.fp_tm,
108 sizeof(struct thread_fp_state));
109 memcpy(&vcpu->arch.vr, &vcpu->arch.vr_tm,
110 sizeof(struct thread_vr_state));
111 vcpu->arch.ppr = vcpu->arch.ppr_tm;
112 vcpu->arch.dscr = vcpu->arch.dscr_tm;
113 vcpu->arch.amr = vcpu->arch.amr_tm;
114 vcpu->arch.regs.ctr = vcpu->arch.ctr_tm;
115 vcpu->arch.tar = vcpu->arch.tar_tm;
116 vcpu->arch.regs.link = vcpu->arch.lr_tm;
Paul Mackerrasfd0944b2018-10-08 16:30:58 +1100117 vcpu->arch.regs.ccr = vcpu->arch.cr_tm;
Simon Guode7ad932018-05-23 15:01:56 +0800118 vcpu->arch.regs.xer = vcpu->arch.xer_tm;
119 vcpu->arch.vrsave = vcpu->arch.vrsave_tm;
120}
121
Simon Guo03c81682018-05-23 15:02:03 +0800122static void kvmppc_emulate_treclaim(struct kvm_vcpu *vcpu, int ra_val)
123{
124 unsigned long guest_msr = kvmppc_get_msr(vcpu);
125 int fc_val = ra_val ? ra_val : 1;
Paul Mackerrasa50623f2018-06-07 18:06:21 +1000126 uint64_t texasr;
Simon Guo03c81682018-05-23 15:02:03 +0800127
128 /* CR0 = 0 | MSR[TS] | 0 */
Paul Mackerrasfd0944b2018-10-08 16:30:58 +1100129 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)) |
Simon Guo03c81682018-05-23 15:02:03 +0800130 (((guest_msr & MSR_TS_MASK) >> (MSR_TS_S_LG - 1))
131 << CR0_SHIFT);
132
133 preempt_disable();
Paul Mackerrasa50623f2018-06-07 18:06:21 +1000134 tm_enable();
135 texasr = mfspr(SPRN_TEXASR);
Simon Guo03c81682018-05-23 15:02:03 +0800136 kvmppc_save_tm_pr(vcpu);
137 kvmppc_copyfrom_vcpu_tm(vcpu);
138
Simon Guo03c81682018-05-23 15:02:03 +0800139 /* failure recording depends on Failure Summary bit */
Paul Mackerrasa50623f2018-06-07 18:06:21 +1000140 if (!(texasr & TEXASR_FS)) {
141 texasr &= ~TEXASR_FC;
142 texasr |= ((u64)fc_val << TEXASR_FC_LG) | TEXASR_FS;
Simon Guo03c81682018-05-23 15:02:03 +0800143
Paul Mackerrasa50623f2018-06-07 18:06:21 +1000144 texasr &= ~(TEXASR_PR | TEXASR_HV);
Simon Guo03c81682018-05-23 15:02:03 +0800145 if (kvmppc_get_msr(vcpu) & MSR_PR)
Paul Mackerrasa50623f2018-06-07 18:06:21 +1000146 texasr |= TEXASR_PR;
Simon Guo03c81682018-05-23 15:02:03 +0800147
148 if (kvmppc_get_msr(vcpu) & MSR_HV)
Paul Mackerrasa50623f2018-06-07 18:06:21 +1000149 texasr |= TEXASR_HV;
Simon Guo03c81682018-05-23 15:02:03 +0800150
Paul Mackerrasa50623f2018-06-07 18:06:21 +1000151 vcpu->arch.texasr = texasr;
Simon Guo03c81682018-05-23 15:02:03 +0800152 vcpu->arch.tfiar = kvmppc_get_pc(vcpu);
Paul Mackerrasa50623f2018-06-07 18:06:21 +1000153 mtspr(SPRN_TEXASR, texasr);
Simon Guo03c81682018-05-23 15:02:03 +0800154 mtspr(SPRN_TFIAR, vcpu->arch.tfiar);
155 }
156 tm_disable();
157 /*
158 * treclaim need quit to non-transactional state.
159 */
160 guest_msr &= ~(MSR_TS_MASK);
161 kvmppc_set_msr(vcpu, guest_msr);
162 preempt_enable();
Simon Guo7284ca82018-05-23 15:02:07 +0800163
164 if (vcpu->arch.shadow_fscr & FSCR_TAR)
165 mtspr(SPRN_TAR, vcpu->arch.tar);
Simon Guo03c81682018-05-23 15:02:03 +0800166}
Simon Guoe32c53d2018-05-23 15:02:04 +0800167
168static void kvmppc_emulate_trchkpt(struct kvm_vcpu *vcpu)
169{
170 unsigned long guest_msr = kvmppc_get_msr(vcpu);
171
172 preempt_disable();
173 /*
174 * need flush FP/VEC/VSX to vcpu save area before
175 * copy.
176 */
177 kvmppc_giveup_ext(vcpu, MSR_VSX);
Simon Guo7284ca82018-05-23 15:02:07 +0800178 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
Simon Guoe32c53d2018-05-23 15:02:04 +0800179 kvmppc_copyto_vcpu_tm(vcpu);
180 kvmppc_save_tm_sprs(vcpu);
181
182 /*
183 * as a result of trecheckpoint. set TS to suspended.
184 */
185 guest_msr &= ~(MSR_TS_MASK);
186 guest_msr |= MSR_TS_S;
187 kvmppc_set_msr(vcpu, guest_msr);
188 kvmppc_restore_tm_pr(vcpu);
189 preempt_enable();
190}
Simon Guo26798f82018-05-23 15:02:05 +0800191
192/* emulate tabort. at guest privilege state */
Simon Guo68ab07b2018-05-23 15:02:06 +0800193void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val)
Simon Guo26798f82018-05-23 15:02:05 +0800194{
195 /* currently we only emulate tabort. but no emulation of other
196 * tabort variants since there is no kernel usage of them at
197 * present.
198 */
199 unsigned long guest_msr = kvmppc_get_msr(vcpu);
Simon Guof61e0d32018-06-08 01:40:03 -0400200 uint64_t org_texasr;
Simon Guo26798f82018-05-23 15:02:05 +0800201
202 preempt_disable();
203 tm_enable();
Simon Guof61e0d32018-06-08 01:40:03 -0400204 org_texasr = mfspr(SPRN_TEXASR);
Simon Guo26798f82018-05-23 15:02:05 +0800205 tm_abort(ra_val);
206
207 /* CR0 = 0 | MSR[TS] | 0 */
Paul Mackerrasfd0944b2018-10-08 16:30:58 +1100208 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)) |
Simon Guo26798f82018-05-23 15:02:05 +0800209 (((guest_msr & MSR_TS_MASK) >> (MSR_TS_S_LG - 1))
210 << CR0_SHIFT);
211
212 vcpu->arch.texasr = mfspr(SPRN_TEXASR);
213 /* failure recording depends on Failure Summary bit,
214 * and tabort will be treated as nops in non-transactional
215 * state.
216 */
Simon Guof61e0d32018-06-08 01:40:03 -0400217 if (!(org_texasr & TEXASR_FS) &&
Simon Guo26798f82018-05-23 15:02:05 +0800218 MSR_TM_ACTIVE(guest_msr)) {
219 vcpu->arch.texasr &= ~(TEXASR_PR | TEXASR_HV);
220 if (guest_msr & MSR_PR)
221 vcpu->arch.texasr |= TEXASR_PR;
222
223 if (guest_msr & MSR_HV)
224 vcpu->arch.texasr |= TEXASR_HV;
225
226 vcpu->arch.tfiar = kvmppc_get_pc(vcpu);
Simon Guo26798f82018-05-23 15:02:05 +0800227 }
228 tm_disable();
229 preempt_enable();
230}
231
Simon Guode7ad932018-05-23 15:01:56 +0800232#endif
233
Tianjia Zhang8c99d342020-04-27 12:35:11 +0800234int kvmppc_core_emulate_op_pr(struct kvm_vcpu *vcpu,
Aneesh Kumar K.V3a167bea2013-10-07 22:17:53 +0530235 unsigned int inst, int *advance)
Alexander Grafc215c6e2009-10-30 05:47:14 +0000236{
237 int emulated = EMULATE_DONE;
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200238 int rt = get_rt(inst);
239 int rs = get_rs(inst);
240 int ra = get_ra(inst);
241 int rb = get_rb(inst);
Alexander Graf42188362014-05-13 17:05:51 +0200242 u32 inst_sc = 0x44000002;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000243
244 switch (get_op(inst)) {
Alexander Graf42188362014-05-13 17:05:51 +0200245 case 0:
246 emulated = EMULATE_FAIL;
247 if ((kvmppc_get_msr(vcpu) & MSR_LE) &&
248 (inst == swab32(inst_sc))) {
249 /*
250 * This is the byte reversed syscall instruction of our
251 * hypercall handler. Early versions of LE Linux didn't
252 * swap the instructions correctly and ended up in
253 * illegal instructions.
254 * Just always fail hypercalls on these broken systems.
255 */
256 kvmppc_set_gpr(vcpu, 3, EV_UNIMPLEMENTED);
257 kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
258 emulated = EMULATE_DONE;
259 }
260 break;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000261 case 19:
262 switch (get_xop(inst)) {
263 case OP_19_XOP_RFID:
Simon Guo401a89e2018-05-23 15:01:54 +0800264 case OP_19_XOP_RFI: {
265 unsigned long srr1 = kvmppc_get_srr1(vcpu);
266#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
267 unsigned long cur_msr = kvmppc_get_msr(vcpu);
268
269 /*
270 * add rules to fit in ISA specification regarding TM
Julia Lawall1fd02f62022-04-30 20:56:54 +0200271 * state transition in TM disable/Suspended state,
Simon Guo401a89e2018-05-23 15:01:54 +0800272 * and target TM state is TM inactive(00) state. (the
273 * change should be suppressed).
274 */
275 if (((cur_msr & MSR_TM) == 0) &&
276 ((srr1 & MSR_TM) == 0) &&
277 MSR_TM_SUSPENDED(cur_msr) &&
278 !MSR_TM_ACTIVE(srr1))
279 srr1 |= MSR_TS_S;
280#endif
Alexander Graf5deb8e72014-04-24 13:46:24 +0200281 kvmppc_set_pc(vcpu, kvmppc_get_srr0(vcpu));
Simon Guo401a89e2018-05-23 15:01:54 +0800282 kvmppc_set_msr(vcpu, srr1);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000283 *advance = 0;
284 break;
Simon Guo401a89e2018-05-23 15:01:54 +0800285 }
Alexander Grafc215c6e2009-10-30 05:47:14 +0000286
287 default:
288 emulated = EMULATE_FAIL;
289 break;
290 }
291 break;
292 case 31:
293 switch (get_xop(inst)) {
294 case OP_31_XOP_MFMSR:
Alexander Graf5deb8e72014-04-24 13:46:24 +0200295 kvmppc_set_gpr(vcpu, rt, kvmppc_get_msr(vcpu));
Alexander Grafc215c6e2009-10-30 05:47:14 +0000296 break;
297 case OP_31_XOP_MTMSRD:
298 {
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200299 ulong rs_val = kvmppc_get_gpr(vcpu, rs);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000300 if (inst & 0x10000) {
Alexander Graf5deb8e72014-04-24 13:46:24 +0200301 ulong new_msr = kvmppc_get_msr(vcpu);
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200302 new_msr &= ~(MSR_RI | MSR_EE);
303 new_msr |= rs_val & (MSR_RI | MSR_EE);
Alexander Graf5deb8e72014-04-24 13:46:24 +0200304 kvmppc_set_msr_fast(vcpu, new_msr);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000305 } else
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200306 kvmppc_set_msr(vcpu, rs_val);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000307 break;
308 }
309 case OP_31_XOP_MTMSR:
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200310 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
Alexander Grafc215c6e2009-10-30 05:47:14 +0000311 break;
Alexander Grafc6648762010-03-24 21:48:24 +0100312 case OP_31_XOP_MFSR:
313 {
314 int srnum;
315
316 srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32);
317 if (vcpu->arch.mmu.mfsrin) {
318 u32 sr;
319 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200320 kvmppc_set_gpr(vcpu, rt, sr);
Alexander Grafc6648762010-03-24 21:48:24 +0100321 }
322 break;
323 }
Alexander Grafc215c6e2009-10-30 05:47:14 +0000324 case OP_31_XOP_MFSRIN:
325 {
326 int srnum;
327
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200328 srnum = (kvmppc_get_gpr(vcpu, rb) >> 28) & 0xf;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000329 if (vcpu->arch.mmu.mfsrin) {
330 u32 sr;
331 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200332 kvmppc_set_gpr(vcpu, rt, sr);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000333 }
334 break;
335 }
Alexander Graf71db4082010-02-19 11:00:37 +0100336 case OP_31_XOP_MTSR:
337 vcpu->arch.mmu.mtsrin(vcpu,
338 (inst >> 16) & 0xf,
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200339 kvmppc_get_gpr(vcpu, rs));
Alexander Graf71db4082010-02-19 11:00:37 +0100340 break;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000341 case OP_31_XOP_MTSRIN:
342 vcpu->arch.mmu.mtsrin(vcpu,
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200343 (kvmppc_get_gpr(vcpu, rb) >> 28) & 0xf,
344 kvmppc_get_gpr(vcpu, rs));
Alexander Grafc215c6e2009-10-30 05:47:14 +0000345 break;
346 case OP_31_XOP_TLBIE:
347 case OP_31_XOP_TLBIEL:
348 {
349 bool large = (inst & 0x00200000) ? true : false;
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200350 ulong addr = kvmppc_get_gpr(vcpu, rb);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000351 vcpu->arch.mmu.tlbie(vcpu, addr, large);
352 break;
353 }
Aneesh Kumar K.V2ba9f0d2013-10-07 22:17:59 +0530354#ifdef CONFIG_PPC_BOOK3S_64
Alexander Graf50c7bb82012-12-14 23:42:05 +0100355 case OP_31_XOP_FAKE_SC1:
356 {
357 /* SC 1 papr hypercalls */
358 ulong cmd = kvmppc_get_gpr(vcpu, 3);
359 int i;
360
Alexander Graf5deb8e72014-04-24 13:46:24 +0200361 if ((kvmppc_get_msr(vcpu) & MSR_PR) ||
Alexander Graf50c7bb82012-12-14 23:42:05 +0100362 !vcpu->arch.papr_enabled) {
363 emulated = EMULATE_FAIL;
364 break;
365 }
366
367 if (kvmppc_h_pr(vcpu, cmd) == EMULATE_DONE)
368 break;
369
Tianjia Zhang8c99d342020-04-27 12:35:11 +0800370 vcpu->run->papr_hcall.nr = cmd;
Alexander Graf50c7bb82012-12-14 23:42:05 +0100371 for (i = 0; i < 9; ++i) {
372 ulong gpr = kvmppc_get_gpr(vcpu, 4 + i);
Tianjia Zhang8c99d342020-04-27 12:35:11 +0800373 vcpu->run->papr_hcall.args[i] = gpr;
Alexander Graf50c7bb82012-12-14 23:42:05 +0100374 }
375
Tianjia Zhang8c99d342020-04-27 12:35:11 +0800376 vcpu->run->exit_reason = KVM_EXIT_PAPR_HCALL;
Bharat Bhushan0f47f9b2013-04-08 00:32:14 +0000377 vcpu->arch.hcall_needed = 1;
Bharat Bhushanc402a3f2013-04-08 00:32:13 +0000378 emulated = EMULATE_EXIT_USER;
Alexander Graf50c7bb82012-12-14 23:42:05 +0100379 break;
380 }
381#endif
Alexander Grafc215c6e2009-10-30 05:47:14 +0000382 case OP_31_XOP_EIOIO:
383 break;
384 case OP_31_XOP_SLBMTE:
385 if (!vcpu->arch.mmu.slbmte)
386 return EMULATE_FAIL;
387
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100388 vcpu->arch.mmu.slbmte(vcpu,
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200389 kvmppc_get_gpr(vcpu, rs),
390 kvmppc_get_gpr(vcpu, rb));
Alexander Grafc215c6e2009-10-30 05:47:14 +0000391 break;
392 case OP_31_XOP_SLBIE:
393 if (!vcpu->arch.mmu.slbie)
394 return EMULATE_FAIL;
395
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100396 vcpu->arch.mmu.slbie(vcpu,
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200397 kvmppc_get_gpr(vcpu, rb));
Alexander Grafc215c6e2009-10-30 05:47:14 +0000398 break;
399 case OP_31_XOP_SLBIA:
400 if (!vcpu->arch.mmu.slbia)
401 return EMULATE_FAIL;
402
403 vcpu->arch.mmu.slbia(vcpu);
404 break;
Paul Mackerras41a86452019-02-04 19:06:18 +1100405 case OP_31_XOP_SLBFEE:
406 if (!(inst & 1) || !vcpu->arch.mmu.slbfee) {
407 return EMULATE_FAIL;
408 } else {
409 ulong b, t;
410 ulong cr = kvmppc_get_cr(vcpu) & ~CR0_MASK;
411
412 b = kvmppc_get_gpr(vcpu, rb);
413 if (!vcpu->arch.mmu.slbfee(vcpu, b, &t))
414 cr |= 2 << CR0_SHIFT;
415 kvmppc_set_gpr(vcpu, rt, t);
416 /* copy XER[SO] bit to CR0[SO] */
417 cr |= (vcpu->arch.regs.xer & 0x80000000) >>
418 (31 - CR0_SHIFT);
419 kvmppc_set_cr(vcpu, cr);
420 }
421 break;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000422 case OP_31_XOP_SLBMFEE:
423 if (!vcpu->arch.mmu.slbmfee) {
424 emulated = EMULATE_FAIL;
425 } else {
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200426 ulong t, rb_val;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000427
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200428 rb_val = kvmppc_get_gpr(vcpu, rb);
429 t = vcpu->arch.mmu.slbmfee(vcpu, rb_val);
430 kvmppc_set_gpr(vcpu, rt, t);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000431 }
432 break;
433 case OP_31_XOP_SLBMFEV:
434 if (!vcpu->arch.mmu.slbmfev) {
435 emulated = EMULATE_FAIL;
436 } else {
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200437 ulong t, rb_val;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000438
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200439 rb_val = kvmppc_get_gpr(vcpu, rb);
440 t = vcpu->arch.mmu.slbmfev(vcpu, rb_val);
441 kvmppc_set_gpr(vcpu, rt, t);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000442 }
443 break;
Alexander Grafbd7cdbb2010-03-24 21:48:33 +0100444 case OP_31_XOP_DCBA:
445 /* Gets treated as NOP */
446 break;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000447 case OP_31_XOP_DCBZ:
448 {
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200449 ulong rb_val = kvmppc_get_gpr(vcpu, rb);
450 ulong ra_val = 0;
Alexander Graf5467a972010-02-19 11:00:38 +0100451 ulong addr, vaddr;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000452 u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
Alexander Graf9fb244a2010-03-24 21:48:32 +0100453 u32 dsisr;
454 int r;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000455
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200456 if (ra)
457 ra_val = kvmppc_get_gpr(vcpu, ra);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000458
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200459 addr = (ra_val + rb_val) & ~31ULL;
Alexander Graf5deb8e72014-04-24 13:46:24 +0200460 if (!(kvmppc_get_msr(vcpu) & MSR_SF))
Alexander Grafc215c6e2009-10-30 05:47:14 +0000461 addr &= 0xffffffff;
Alexander Graf5467a972010-02-19 11:00:38 +0100462 vaddr = addr;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000463
Alexander Graf9fb244a2010-03-24 21:48:32 +0100464 r = kvmppc_st(vcpu, &addr, 32, zeros, true);
465 if ((r == -ENOENT) || (r == -EPERM)) {
466 *advance = 0;
Alexander Graf5deb8e72014-04-24 13:46:24 +0200467 kvmppc_set_dar(vcpu, vaddr);
Paul Mackerrasa2d56022013-09-20 14:52:43 +1000468 vcpu->arch.fault_dar = vaddr;
Alexander Graf9fb244a2010-03-24 21:48:32 +0100469
470 dsisr = DSISR_ISSTORE;
471 if (r == -ENOENT)
472 dsisr |= DSISR_NOHPTE;
473 else if (r == -EPERM)
474 dsisr |= DSISR_PROTFAULT;
475
Alexander Graf5deb8e72014-04-24 13:46:24 +0200476 kvmppc_set_dsisr(vcpu, dsisr);
Paul Mackerrasa2d56022013-09-20 14:52:43 +1000477 vcpu->arch.fault_dsisr = dsisr;
Alexander Graf9fb244a2010-03-24 21:48:32 +0100478
Alexander Grafc215c6e2009-10-30 05:47:14 +0000479 kvmppc_book3s_queue_irqprio(vcpu,
480 BOOK3S_INTERRUPT_DATA_STORAGE);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000481 }
482
483 break;
484 }
Simon Guo57063402018-05-23 15:02:01 +0800485#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
486 case OP_31_XOP_TBEGIN:
487 {
488 if (!cpu_has_feature(CPU_FTR_TM))
489 break;
490
491 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
492 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
493 emulated = EMULATE_AGAIN;
494 break;
495 }
496
497 if (!(kvmppc_get_msr(vcpu) & MSR_PR)) {
498 preempt_disable();
Paul Mackerrasfd0944b2018-10-08 16:30:58 +1100499 vcpu->arch.regs.ccr = (CR0_TBEGIN_FAILURE |
500 (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)));
Simon Guo57063402018-05-23 15:02:01 +0800501
502 vcpu->arch.texasr = (TEXASR_FS | TEXASR_EXACT |
503 (((u64)(TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
504 << TEXASR_FC_LG));
505
506 if ((inst >> 21) & 0x1)
507 vcpu->arch.texasr |= TEXASR_ROT;
508
509 if (kvmppc_get_msr(vcpu) & MSR_HV)
510 vcpu->arch.texasr |= TEXASR_HV;
511
512 vcpu->arch.tfhar = kvmppc_get_pc(vcpu) + 4;
513 vcpu->arch.tfiar = kvmppc_get_pc(vcpu);
514
515 kvmppc_restore_tm_sprs(vcpu);
516 preempt_enable();
517 } else
518 emulated = EMULATE_FAIL;
519 break;
520 }
Simon Guo26798f82018-05-23 15:02:05 +0800521 case OP_31_XOP_TABORT:
522 {
523 ulong guest_msr = kvmppc_get_msr(vcpu);
524 unsigned long ra_val = 0;
525
526 if (!cpu_has_feature(CPU_FTR_TM))
527 break;
528
529 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
530 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
531 emulated = EMULATE_AGAIN;
532 break;
533 }
534
535 /* only emulate for privilege guest, since problem state
536 * guest can run with TM enabled and we don't expect to
537 * trap at here for that case.
538 */
539 WARN_ON(guest_msr & MSR_PR);
540
541 if (ra)
542 ra_val = kvmppc_get_gpr(vcpu, ra);
543
544 kvmppc_emulate_tabort(vcpu, ra_val);
545 break;
546 }
Simon Guo03c81682018-05-23 15:02:03 +0800547 case OP_31_XOP_TRECLAIM:
548 {
549 ulong guest_msr = kvmppc_get_msr(vcpu);
550 unsigned long ra_val = 0;
551
552 if (!cpu_has_feature(CPU_FTR_TM))
553 break;
554
555 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
556 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
557 emulated = EMULATE_AGAIN;
558 break;
559 }
560
561 /* generate interrupts based on priorities */
562 if (guest_msr & MSR_PR) {
563 /* Privileged Instruction type Program Interrupt */
564 kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV);
565 emulated = EMULATE_AGAIN;
566 break;
567 }
568
569 if (!MSR_TM_ACTIVE(guest_msr)) {
570 /* TM bad thing interrupt */
571 kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
572 emulated = EMULATE_AGAIN;
573 break;
574 }
575
576 if (ra)
577 ra_val = kvmppc_get_gpr(vcpu, ra);
578 kvmppc_emulate_treclaim(vcpu, ra_val);
579 break;
580 }
Simon Guoe32c53d2018-05-23 15:02:04 +0800581 case OP_31_XOP_TRCHKPT:
582 {
583 ulong guest_msr = kvmppc_get_msr(vcpu);
584 unsigned long texasr;
585
586 if (!cpu_has_feature(CPU_FTR_TM))
587 break;
588
589 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
590 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
591 emulated = EMULATE_AGAIN;
592 break;
593 }
594
595 /* generate interrupt based on priorities */
596 if (guest_msr & MSR_PR) {
597 /* Privileged Instruction type Program Intr */
598 kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV);
599 emulated = EMULATE_AGAIN;
600 break;
601 }
602
603 tm_enable();
604 texasr = mfspr(SPRN_TEXASR);
605 tm_disable();
606
607 if (MSR_TM_ACTIVE(guest_msr) ||
608 !(texasr & (TEXASR_FS))) {
609 /* TM bad thing interrupt */
610 kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
611 emulated = EMULATE_AGAIN;
612 break;
613 }
614
615 kvmppc_emulate_trchkpt(vcpu);
616 break;
617 }
Simon Guo57063402018-05-23 15:02:01 +0800618#endif
Alexander Grafc215c6e2009-10-30 05:47:14 +0000619 default:
620 emulated = EMULATE_FAIL;
621 }
622 break;
623 default:
624 emulated = EMULATE_FAIL;
625 }
626
Alexander Graf831317b2010-02-19 11:00:44 +0100627 if (emulated == EMULATE_FAIL)
Tianjia Zhang8c99d342020-04-27 12:35:11 +0800628 emulated = kvmppc_emulate_paired_single(vcpu);
Alexander Graf831317b2010-02-19 11:00:44 +0100629
Alexander Grafc215c6e2009-10-30 05:47:14 +0000630 return emulated;
631}
632
Alexander Grafe15a1132009-11-30 03:02:02 +0000633void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper,
634 u32 val)
635{
636 if (upper) {
637 /* Upper BAT */
638 u32 bl = (val >> 2) & 0x7ff;
639 bat->bepi_mask = (~bl << 17);
640 bat->bepi = val & 0xfffe0000;
641 bat->vs = (val & 2) ? 1 : 0;
642 bat->vp = (val & 1) ? 1 : 0;
643 bat->raw = (bat->raw & 0xffffffff00000000ULL) | val;
644 } else {
645 /* Lower BAT */
646 bat->brpn = val & 0xfffe0000;
647 bat->wimg = (val >> 3) & 0xf;
648 bat->pp = val & 3;
649 bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32);
650 }
651}
652
Alexander Grafc1c88e22010-08-02 23:23:04 +0200653static struct kvmppc_bat *kvmppc_find_bat(struct kvm_vcpu *vcpu, int sprn)
Alexander Grafc04a6952010-03-24 21:48:25 +0100654{
655 struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
656 struct kvmppc_bat *bat;
657
658 switch (sprn) {
659 case SPRN_IBAT0U ... SPRN_IBAT3L:
660 bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2];
661 break;
662 case SPRN_IBAT4U ... SPRN_IBAT7L:
663 bat = &vcpu_book3s->ibat[4 + ((sprn - SPRN_IBAT4U) / 2)];
664 break;
665 case SPRN_DBAT0U ... SPRN_DBAT3L:
666 bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2];
667 break;
668 case SPRN_DBAT4U ... SPRN_DBAT7L:
669 bat = &vcpu_book3s->dbat[4 + ((sprn - SPRN_DBAT4U) / 2)];
670 break;
671 default:
672 BUG();
673 }
674
Alexander Grafc1c88e22010-08-02 23:23:04 +0200675 return bat;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000676}
677
Aneesh Kumar K.V3a167bea2013-10-07 22:17:53 +0530678int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
Alexander Grafc215c6e2009-10-30 05:47:14 +0000679{
680 int emulated = EMULATE_DONE;
681
682 switch (sprn) {
683 case SPRN_SDR1:
Alexander Graf317a8fa2011-08-08 16:07:16 +0200684 if (!spr_allowed(vcpu, PRIV_HYPER))
685 goto unprivileged;
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100686 to_book3s(vcpu)->sdr1 = spr_val;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000687 break;
688 case SPRN_DSISR:
Alexander Graf5deb8e72014-04-24 13:46:24 +0200689 kvmppc_set_dsisr(vcpu, spr_val);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000690 break;
691 case SPRN_DAR:
Alexander Graf5deb8e72014-04-24 13:46:24 +0200692 kvmppc_set_dar(vcpu, spr_val);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000693 break;
694 case SPRN_HIOR:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100695 to_book3s(vcpu)->hior = spr_val;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000696 break;
697 case SPRN_IBAT0U ... SPRN_IBAT3L:
698 case SPRN_IBAT4U ... SPRN_IBAT7L:
699 case SPRN_DBAT0U ... SPRN_DBAT3L:
700 case SPRN_DBAT4U ... SPRN_DBAT7L:
Alexander Grafc1c88e22010-08-02 23:23:04 +0200701 {
702 struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);
703
704 kvmppc_set_bat(vcpu, bat, !(sprn % 2), (u32)spr_val);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000705 /* BAT writes happen so rarely that we're ok to flush
706 * everything here */
707 kvmppc_mmu_pte_flush(vcpu, 0, 0);
Alexander Grafc04a6952010-03-24 21:48:25 +0100708 kvmppc_mmu_flush_segments(vcpu);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000709 break;
Alexander Grafc1c88e22010-08-02 23:23:04 +0200710 }
Alexander Grafc215c6e2009-10-30 05:47:14 +0000711 case SPRN_HID0:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100712 to_book3s(vcpu)->hid[0] = spr_val;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000713 break;
714 case SPRN_HID1:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100715 to_book3s(vcpu)->hid[1] = spr_val;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000716 break;
717 case SPRN_HID2:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100718 to_book3s(vcpu)->hid[2] = spr_val;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000719 break;
Alexander Grafd6d549b2010-02-19 11:00:33 +0100720 case SPRN_HID2_GEKKO:
721 to_book3s(vcpu)->hid[2] = spr_val;
722 /* HID2.PSE controls paired single on gekko */
723 switch (vcpu->arch.pvr) {
724 case 0x00080200: /* lonestar 2.0 */
725 case 0x00088202: /* lonestar 2.2 */
726 case 0x70000100: /* gekko 1.0 */
727 case 0x00080100: /* gekko 2.0 */
728 case 0x00083203: /* gekko 2.3a */
729 case 0x00083213: /* gekko 2.3b */
730 case 0x00083204: /* gekko 2.4 */
731 case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */
Alexander Grafb83d4a92010-04-20 02:49:54 +0200732 case 0x00087200: /* broadway */
733 if (vcpu->arch.hflags & BOOK3S_HFLAG_NATIVE_PS) {
734 /* Native paired singles */
735 } else if (spr_val & (1 << 29)) { /* HID2.PSE */
Alexander Grafd6d549b2010-02-19 11:00:33 +0100736 vcpu->arch.hflags |= BOOK3S_HFLAG_PAIRED_SINGLE;
737 kvmppc_giveup_ext(vcpu, MSR_FP);
738 } else {
739 vcpu->arch.hflags &= ~BOOK3S_HFLAG_PAIRED_SINGLE;
740 }
741 break;
742 }
743 break;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000744 case SPRN_HID4:
Alexander Grafd6d549b2010-02-19 11:00:33 +0100745 case SPRN_HID4_GEKKO:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100746 to_book3s(vcpu)->hid[4] = spr_val;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000747 break;
748 case SPRN_HID5:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100749 to_book3s(vcpu)->hid[5] = spr_val;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000750 /* guest HID5 set can change is_dcbz32 */
751 if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
752 (mfmsr() & MSR_HV))
753 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
754 break;
Alexander Grafd6d549b2010-02-19 11:00:33 +0100755 case SPRN_GQR0:
756 case SPRN_GQR1:
757 case SPRN_GQR2:
758 case SPRN_GQR3:
759 case SPRN_GQR4:
760 case SPRN_GQR5:
761 case SPRN_GQR6:
762 case SPRN_GQR7:
763 to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val;
764 break;
Alexander Graf2e23f542014-04-29 13:36:21 +0200765#ifdef CONFIG_PPC_BOOK3S_64
Alexander Graf8e6afa32014-07-31 10:21:59 +0200766 case SPRN_FSCR:
767 kvmppc_set_fscr(vcpu, spr_val);
768 break;
Alexander Graf2e23f542014-04-29 13:36:21 +0200769 case SPRN_BESCR:
770 vcpu->arch.bescr = spr_val;
771 break;
772 case SPRN_EBBHR:
773 vcpu->arch.ebbhr = spr_val;
774 break;
775 case SPRN_EBBRR:
776 vcpu->arch.ebbrr = spr_val;
777 break;
Alexander Graf9916d572014-04-29 17:54:40 +0200778#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
779 case SPRN_TFHAR:
Alexander Graf9916d572014-04-29 17:54:40 +0200780 case SPRN_TEXASR:
Alexander Graf9916d572014-04-29 17:54:40 +0200781 case SPRN_TFIAR:
Simon Guo533082a2018-05-23 15:02:00 +0800782 if (!cpu_has_feature(CPU_FTR_TM))
783 break;
784
785 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
786 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
787 emulated = EMULATE_AGAIN;
788 break;
789 }
790
791 if (MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)) &&
792 !((MSR_TM_SUSPENDED(kvmppc_get_msr(vcpu))) &&
793 (sprn == SPRN_TFHAR))) {
794 /* it is illegal to mtspr() TM regs in
795 * other than non-transactional state, with
796 * the exception of TFHAR in suspend state.
797 */
798 kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
799 emulated = EMULATE_AGAIN;
800 break;
801 }
802
803 tm_enable();
804 if (sprn == SPRN_TFHAR)
805 mtspr(SPRN_TFHAR, spr_val);
806 else if (sprn == SPRN_TEXASR)
807 mtspr(SPRN_TEXASR, spr_val);
808 else
809 mtspr(SPRN_TFIAR, spr_val);
810 tm_disable();
811
Alexander Graf9916d572014-04-29 17:54:40 +0200812 break;
813#endif
Alexander Graf2e23f542014-04-29 13:36:21 +0200814#endif
Alexander Grafc215c6e2009-10-30 05:47:14 +0000815 case SPRN_ICTC:
816 case SPRN_THRM1:
817 case SPRN_THRM2:
818 case SPRN_THRM3:
819 case SPRN_CTRLF:
820 case SPRN_CTRLT:
Alexander Grafd6d549b2010-02-19 11:00:33 +0100821 case SPRN_L2CR:
Paul Mackerrasb0a94d42012-11-04 18:15:43 +0000822 case SPRN_DSCR:
Alexander Grafd6d549b2010-02-19 11:00:33 +0100823 case SPRN_MMCR0_GEKKO:
824 case SPRN_MMCR1_GEKKO:
825 case SPRN_PMC1_GEKKO:
826 case SPRN_PMC2_GEKKO:
827 case SPRN_PMC3_GEKKO:
828 case SPRN_PMC4_GEKKO:
829 case SPRN_WPAR_GEKKO:
Mihai Caramanf2be6552012-12-20 04:52:39 +0000830 case SPRN_MSSSR0:
Alexander Graff3532022013-07-02 16:15:10 +0200831 case SPRN_DABR:
Alexander Graff8f6eb02014-04-22 12:41:06 +0200832#ifdef CONFIG_PPC_BOOK3S_64
833 case SPRN_MMCRS:
834 case SPRN_MMCRA:
835 case SPRN_MMCR0:
836 case SPRN_MMCR1:
837 case SPRN_MMCR2:
Thomas Huthfa73c3b2016-09-21 15:06:45 +0200838 case SPRN_UMMCR2:
Aneesh Kumar K.V9f378b92020-11-27 10:14:04 +0530839 case SPRN_UAMOR:
840 case SPRN_IAMR:
841 case SPRN_AMR:
Alexander Graff8f6eb02014-04-22 12:41:06 +0200842#endif
Alexander Grafc215c6e2009-10-30 05:47:14 +0000843 break;
Alexander Graf317a8fa2011-08-08 16:07:16 +0200844unprivileged:
Alexander Grafc215c6e2009-10-30 05:47:14 +0000845 default:
Thomas Huthfeafd132017-04-05 15:58:51 +0200846 pr_info_ratelimited("KVM: invalid SPR write: %d\n", sprn);
847 if (sprn & 0x10) {
848 if (kvmppc_get_msr(vcpu) & MSR_PR) {
849 kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV);
850 emulated = EMULATE_AGAIN;
851 }
852 } else {
853 if ((kvmppc_get_msr(vcpu) & MSR_PR) || sprn == 0) {
854 kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
855 emulated = EMULATE_AGAIN;
856 }
857 }
Alexander Grafc215c6e2009-10-30 05:47:14 +0000858 break;
859 }
860
861 return emulated;
862}
863
Aneesh Kumar K.V3a167bea2013-10-07 22:17:53 +0530864int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
Alexander Grafc215c6e2009-10-30 05:47:14 +0000865{
866 int emulated = EMULATE_DONE;
867
868 switch (sprn) {
Alexander Grafc04a6952010-03-24 21:48:25 +0100869 case SPRN_IBAT0U ... SPRN_IBAT3L:
870 case SPRN_IBAT4U ... SPRN_IBAT7L:
871 case SPRN_DBAT0U ... SPRN_DBAT3L:
872 case SPRN_DBAT4U ... SPRN_DBAT7L:
Alexander Grafc1c88e22010-08-02 23:23:04 +0200873 {
874 struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);
875
876 if (sprn % 2)
Alexander Graf54771e62012-05-04 14:55:12 +0200877 *spr_val = bat->raw >> 32;
Alexander Grafc1c88e22010-08-02 23:23:04 +0200878 else
Alexander Graf54771e62012-05-04 14:55:12 +0200879 *spr_val = bat->raw;
Alexander Grafc1c88e22010-08-02 23:23:04 +0200880
Alexander Grafc04a6952010-03-24 21:48:25 +0100881 break;
Alexander Grafc1c88e22010-08-02 23:23:04 +0200882 }
Alexander Grafc215c6e2009-10-30 05:47:14 +0000883 case SPRN_SDR1:
Alexander Graf317a8fa2011-08-08 16:07:16 +0200884 if (!spr_allowed(vcpu, PRIV_HYPER))
885 goto unprivileged;
Alexander Graf54771e62012-05-04 14:55:12 +0200886 *spr_val = to_book3s(vcpu)->sdr1;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000887 break;
888 case SPRN_DSISR:
Alexander Graf5deb8e72014-04-24 13:46:24 +0200889 *spr_val = kvmppc_get_dsisr(vcpu);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000890 break;
891 case SPRN_DAR:
Alexander Graf5deb8e72014-04-24 13:46:24 +0200892 *spr_val = kvmppc_get_dar(vcpu);
Alexander Grafc215c6e2009-10-30 05:47:14 +0000893 break;
894 case SPRN_HIOR:
Alexander Graf54771e62012-05-04 14:55:12 +0200895 *spr_val = to_book3s(vcpu)->hior;
Alexander Grafc215c6e2009-10-30 05:47:14 +0000896 break;
897 case SPRN_HID0:
Alexander Graf54771e62012-05-04 14:55:12 +0200898 *spr_val = to_book3s(vcpu)->hid[0];
Alexander Grafc215c6e2009-10-30 05:47:14 +0000899 break;
900 case SPRN_HID1:
Alexander Graf54771e62012-05-04 14:55:12 +0200901 *spr_val = to_book3s(vcpu)->hid[1];
Alexander Grafc215c6e2009-10-30 05:47:14 +0000902 break;
903 case SPRN_HID2:
Alexander Grafd6d549b2010-02-19 11:00:33 +0100904 case SPRN_HID2_GEKKO:
Alexander Graf54771e62012-05-04 14:55:12 +0200905 *spr_val = to_book3s(vcpu)->hid[2];
Alexander Grafc215c6e2009-10-30 05:47:14 +0000906 break;
907 case SPRN_HID4:
Alexander Grafd6d549b2010-02-19 11:00:33 +0100908 case SPRN_HID4_GEKKO:
Alexander Graf54771e62012-05-04 14:55:12 +0200909 *spr_val = to_book3s(vcpu)->hid[4];
Alexander Grafc215c6e2009-10-30 05:47:14 +0000910 break;
911 case SPRN_HID5:
Alexander Graf54771e62012-05-04 14:55:12 +0200912 *spr_val = to_book3s(vcpu)->hid[5];
Alexander Grafc215c6e2009-10-30 05:47:14 +0000913 break;
Alexander Grafaacf9aa2011-08-08 17:22:59 +0200914 case SPRN_CFAR:
Paul Mackerrasb0a94d42012-11-04 18:15:43 +0000915 case SPRN_DSCR:
Alexander Graf54771e62012-05-04 14:55:12 +0200916 *spr_val = 0;
Alexander Grafaacf9aa2011-08-08 17:22:59 +0200917 break;
Paul Mackerrasb0a94d42012-11-04 18:15:43 +0000918 case SPRN_PURR:
Aneesh Kumar K.V3cd60e32014-06-04 16:47:55 +0530919 /*
920 * On exit we would have updated purr
921 */
922 *spr_val = vcpu->arch.purr;
Paul Mackerrasb0a94d42012-11-04 18:15:43 +0000923 break;
924 case SPRN_SPURR:
Aneesh Kumar K.V3cd60e32014-06-04 16:47:55 +0530925 /*
926 * On exit we would have updated spurr
927 */
928 *spr_val = vcpu->arch.spurr;
Paul Mackerrasb0a94d42012-11-04 18:15:43 +0000929 break;
Aneesh Kumar K.V8f42ab22014-06-05 17:38:02 +0530930 case SPRN_VTB:
Paul Mackerras88b02cf92016-09-15 13:42:52 +1000931 *spr_val = to_book3s(vcpu)->vtb;
Aneesh Kumar K.V8f42ab22014-06-05 17:38:02 +0530932 break;
Aneesh Kumar K.V06da28e2014-06-05 17:38:05 +0530933 case SPRN_IC:
934 *spr_val = vcpu->arch.ic;
935 break;
Alexander Grafd6d549b2010-02-19 11:00:33 +0100936 case SPRN_GQR0:
937 case SPRN_GQR1:
938 case SPRN_GQR2:
939 case SPRN_GQR3:
940 case SPRN_GQR4:
941 case SPRN_GQR5:
942 case SPRN_GQR6:
943 case SPRN_GQR7:
Alexander Graf54771e62012-05-04 14:55:12 +0200944 *spr_val = to_book3s(vcpu)->gqr[sprn - SPRN_GQR0];
Alexander Grafd6d549b2010-02-19 11:00:33 +0100945 break;
Alexander Graf8e6afa32014-07-31 10:21:59 +0200946#ifdef CONFIG_PPC_BOOK3S_64
Alexander Graf616dff82014-04-29 16:48:44 +0200947 case SPRN_FSCR:
948 *spr_val = vcpu->arch.fscr;
949 break;
Alexander Graf2e23f542014-04-29 13:36:21 +0200950 case SPRN_BESCR:
951 *spr_val = vcpu->arch.bescr;
952 break;
953 case SPRN_EBBHR:
954 *spr_val = vcpu->arch.ebbhr;
955 break;
956 case SPRN_EBBRR:
957 *spr_val = vcpu->arch.ebbrr;
958 break;
Alexander Graf9916d572014-04-29 17:54:40 +0200959#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
960 case SPRN_TFHAR:
Alexander Graf9916d572014-04-29 17:54:40 +0200961 case SPRN_TEXASR:
Alexander Graf9916d572014-04-29 17:54:40 +0200962 case SPRN_TFIAR:
Simon Guo533082a2018-05-23 15:02:00 +0800963 if (!cpu_has_feature(CPU_FTR_TM))
964 break;
965
966 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
967 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
968 emulated = EMULATE_AGAIN;
969 break;
970 }
971
972 tm_enable();
973 if (sprn == SPRN_TFHAR)
974 *spr_val = mfspr(SPRN_TFHAR);
975 else if (sprn == SPRN_TEXASR)
976 *spr_val = mfspr(SPRN_TEXASR);
977 else if (sprn == SPRN_TFIAR)
978 *spr_val = mfspr(SPRN_TFIAR);
979 tm_disable();
Alexander Graf9916d572014-04-29 17:54:40 +0200980 break;
981#endif
Alexander Graf2e23f542014-04-29 13:36:21 +0200982#endif
Alexander Grafc215c6e2009-10-30 05:47:14 +0000983 case SPRN_THRM1:
984 case SPRN_THRM2:
985 case SPRN_THRM3:
986 case SPRN_CTRLF:
987 case SPRN_CTRLT:
Alexander Grafd6d549b2010-02-19 11:00:33 +0100988 case SPRN_L2CR:
989 case SPRN_MMCR0_GEKKO:
990 case SPRN_MMCR1_GEKKO:
991 case SPRN_PMC1_GEKKO:
992 case SPRN_PMC2_GEKKO:
993 case SPRN_PMC3_GEKKO:
994 case SPRN_PMC4_GEKKO:
995 case SPRN_WPAR_GEKKO:
Mihai Caramanf2be6552012-12-20 04:52:39 +0000996 case SPRN_MSSSR0:
Alexander Graff3532022013-07-02 16:15:10 +0200997 case SPRN_DABR:
Alexander Graff8f6eb02014-04-22 12:41:06 +0200998#ifdef CONFIG_PPC_BOOK3S_64
999 case SPRN_MMCRS:
1000 case SPRN_MMCRA:
1001 case SPRN_MMCR0:
1002 case SPRN_MMCR1:
1003 case SPRN_MMCR2:
Thomas Huthfa73c3b2016-09-21 15:06:45 +02001004 case SPRN_UMMCR2:
Alexander Grafa5948fa2014-04-25 16:07:21 +02001005 case SPRN_TIR:
Aneesh Kumar K.V9f378b92020-11-27 10:14:04 +05301006 case SPRN_UAMOR:
1007 case SPRN_IAMR:
1008 case SPRN_AMR:
Alexander Graff8f6eb02014-04-22 12:41:06 +02001009#endif
Alexander Graf54771e62012-05-04 14:55:12 +02001010 *spr_val = 0;
Alexander Grafc215c6e2009-10-30 05:47:14 +00001011 break;
1012 default:
Alexander Graf317a8fa2011-08-08 16:07:16 +02001013unprivileged:
Thomas Huthfeafd132017-04-05 15:58:51 +02001014 pr_info_ratelimited("KVM: invalid SPR read: %d\n", sprn);
1015 if (sprn & 0x10) {
1016 if (kvmppc_get_msr(vcpu) & MSR_PR) {
1017 kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV);
1018 emulated = EMULATE_AGAIN;
1019 }
1020 } else {
1021 if ((kvmppc_get_msr(vcpu) & MSR_PR) || sprn == 0 ||
1022 sprn == 4 || sprn == 5 || sprn == 6) {
1023 kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
1024 emulated = EMULATE_AGAIN;
1025 }
1026 }
1027
Alexander Grafc215c6e2009-10-30 05:47:14 +00001028 break;
1029 }
1030
1031 return emulated;
1032}
1033
Alexander Grafca7f4202010-03-24 21:48:28 +01001034u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst)
1035{
Aneesh Kumar K.Vddca1562014-05-12 17:04:06 +05301036 return make_dsisr(inst);
Alexander Grafca7f4202010-03-24 21:48:28 +01001037}
1038
1039ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst)
1040{
Aneesh Kumar K.V7310f3a2014-05-12 17:04:05 +05301041#ifdef CONFIG_PPC_BOOK3S_64
1042 /*
1043 * Linux's fix_alignment() assumes that DAR is valid, so can we
1044 */
1045 return vcpu->arch.fault_dar;
1046#else
Alexander Grafca7f4202010-03-24 21:48:28 +01001047 ulong dar = 0;
Alexander Grafc46dc9a2012-05-04 14:01:33 +02001048 ulong ra = get_ra(inst);
1049 ulong rb = get_rb(inst);
Alexander Grafca7f4202010-03-24 21:48:28 +01001050
1051 switch (get_op(inst)) {
1052 case OP_LFS:
1053 case OP_LFD:
1054 case OP_STFD:
1055 case OP_STFS:
Alexander Grafca7f4202010-03-24 21:48:28 +01001056 if (ra)
1057 dar = kvmppc_get_gpr(vcpu, ra);
1058 dar += (s32)((s16)inst);
1059 break;
1060 case 31:
Alexander Grafca7f4202010-03-24 21:48:28 +01001061 if (ra)
1062 dar = kvmppc_get_gpr(vcpu, ra);
Alexander Grafc46dc9a2012-05-04 14:01:33 +02001063 dar += kvmppc_get_gpr(vcpu, rb);
Alexander Grafca7f4202010-03-24 21:48:28 +01001064 break;
1065 default:
1066 printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);
1067 break;
1068 }
1069
1070 return dar;
Aneesh Kumar K.V7310f3a2014-05-12 17:04:05 +05301071#endif
Alexander Grafca7f4202010-03-24 21:48:28 +01001072}