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NXP i.MX Messaging Unit (MU)
The Messaging Unit module enables two processors within the SoC to
communicate and coordinate by passing messages (e.g. data, status
and control) through the MU interface. The MU also provides the ability
for one processor to signal the other processor using interrupts.
Because the MU manages the messaging between processors, the MU uses
different clocks (from each side of the different peripheral buses).
Therefore, the MU must synchronize the accesses from one side to the
other. The MU accomplishes synchronization using two sets of matching
registers (Processor A-facing, Processor B-facing).
Messaging Unit Device Node:
Required properties:
- compatible : should be "fsl,<chip>-mu", the supported chips include
imx6sx, imx7s, imx8qxp, imx8qm.
The "fsl,imx6sx-mu" compatible is seen as generic and should
be included together with SoC specific compatible.
There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu"
compatible to support it.
- reg : Should contain the registers location and length
- interrupts : Interrupt number. The interrupt specifier format depends
on the interrupt controller parent.
- #mbox-cells: Must be 2.
<&phandle type channel>
phandle : Label name of controller
type : Channel type
channel : Channel number
This MU support 4 type of unidirectional channels, each type
has 4 channels. A total of 16 channels. Following types are
0 - TX channel with 32bit transmit register and IRQ transmit
acknowledgment support.
1 - RX channel with 32bit receive register and IRQ support
2 - TX doorbell channel. Without own register and no ACK support.
3 - RX doorbell channel.
Optional properties:
- clocks : phandle to the input clock.
- fsl,mu-side-b : Should be set for side B MU.
lsio_mu0: mailbox@5d1b0000 {
compatible = "fsl,imx8qxp-mu";
reg = <0x0 0x5d1b0000 0x0 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;