| # SPDX-License-Identifier: GPL-2.0 |
| |
| menuconfig CACHEMAINT_FOR_DMA |
| bool "Cache management for noncoherent DMA" |
| depends on RISCV |
| default y |
| help |
| These drivers implement support for noncoherent DMA master devices |
| on platforms that lack the standard CPU interfaces for this. |
| |
| if CACHEMAINT_FOR_DMA |
| |
| config AX45MP_L2_CACHE |
| bool "Andes Technology AX45MP L2 Cache controller" |
| select RISCV_NONSTANDARD_CACHE_OPS |
| help |
| Support for the L2 cache controller on Andes Technology AX45MP platforms. |
| |
| config SIFIVE_CCACHE |
| bool "Sifive Composable Cache controller" |
| depends on ARCH_SIFIVE || ARCH_STARFIVE |
| help |
| Support for the composable cache controller on SiFive platforms. |
| |
| config STARFIVE_STARLINK_CACHE |
| bool "StarFive StarLink Cache controller" |
| depends on ARCH_STARFIVE |
| depends on 64BIT |
| select RISCV_DMA_NONCOHERENT |
| select RISCV_NONSTANDARD_CACHE_OPS |
| help |
| Support for the StarLink cache controller IP from StarFive. |
| |
| endif #CACHEMAINT_FOR_DMA |
| |
| menuconfig CACHEMAINT_FOR_HOTPLUG |
| bool "Cache management for memory hot plug like operations" |
| depends on GENERIC_CPU_CACHE_MAINTENANCE |
| help |
| These drivers implement cache management for flows where it is necessary |
| to flush data from all host caches. |
| |
| if CACHEMAINT_FOR_HOTPLUG |
| |
| config HISI_SOC_HHA |
| tristate "HiSilicon Hydra Home Agent (HHA) device driver" |
| depends on (ARM64 && ACPI) || COMPILE_TEST |
| help |
| The Hydra Home Agent (HHA) is responsible for cache coherency |
| on the SoC. This drivers enables the cache maintenance functions of |
| the HHA. |
| |
| This driver can be built as a module. If so, the module will be |
| called hisi_soc_hha. |
| |
| endif #CACHEMAINT_FOR_HOTPLUG |
