| /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ |
| /* |
| * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved |
| */ |
| |
| #ifndef __T7_SCMI_CLKC_H |
| #define __T7_SCMI_CLKC_H |
| |
| #define CLKID_DDR_PLL_OSC 0 |
| #define CLKID_AUD_PLL_OSC 1 |
| #define CLKID_TOP_PLL_OSC 2 |
| #define CLKID_TCON_PLL_OSC 3 |
| #define CLKID_USB_PLL0_OSC 4 |
| #define CLKID_USB_PLL1_OSC 5 |
| #define CLKID_MCLK_PLL_OSC 6 |
| #define CLKID_PCIE_OSC 7 |
| #define CLKID_ETH_PLL_OSC 8 |
| #define CLKID_PCIE_REFCLK_PLL_OSC 9 |
| #define CLKID_EARC_OSC 10 |
| #define CLKID_SYS1_PLL_OSC 11 |
| #define CLKID_HDMI_PLL_OSC 12 |
| #define CLKID_SYS_CLK 13 |
| #define CLKID_AXI_CLK 14 |
| #define CLKID_FIXED_PLL_DCO 15 |
| #define CLKID_FIXED_PLL 16 |
| #define CLKID_FCLK_DIV2_DIV 17 |
| #define CLKID_FCLK_DIV2 18 |
| #define CLKID_FCLK_DIV2P5_DIV 19 |
| #define CLKID_FCLK_DIV2P5 20 |
| #define CLKID_FCLK_DIV3_DIV 21 |
| #define CLKID_FCLK_DIV3 22 |
| #define CLKID_FCLK_DIV4_DIV 23 |
| #define CLKID_FCLK_DIV4 24 |
| #define CLKID_FCLK_DIV5_DIV 25 |
| #define CLKID_FCLK_DIV5 26 |
| #define CLKID_FCLK_DIV7_DIV 27 |
| #define CLKID_FCLK_DIV7 28 |
| #define CLKID_FCLK_50M_DIV 29 |
| #define CLKID_FCLK_50M 30 |
| #define CLKID_CPU_CLK 31 |
| #define CLKID_A73_CLK 32 |
| #define CLKID_CPU_CLK_DIV16_DIV 33 |
| #define CLKID_CPU_CLK_DIV16 34 |
| #define CLKID_A73_CLK_DIV16_DIV 35 |
| #define CLKID_A73_CLK_DIV16 36 |
| |
| #endif /* __T7_SCMI_CLKC_H */ |
