| // SPDX-License-Identifier: GPL-2.0-only | |
| /* | |
| * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> | |
| */ | |
| #include <linux/platform_device.h> | |
| #include <linux/regmap.h> | |
| #include "pinctrl-mtk-mt6735.h" | |
| #include "pinctrl-paris.h" | |
| /* Common registers */ | |
| #define GPIO_DIR 0x000 | |
| #define GPIO_DOUT 0x100 | |
| #define GPIO_DIN 0x200 | |
| #define GPIO_MODE1 0x300 | |
| #define GPIO_MODE2 0x310 | |
| #define GPIO_MODE3 0x320 | |
| #define GPIO_MODE4 0x330 | |
| #define GPIO_MODE5 0x340 | |
| #define GPIO_MODE6 0x350 | |
| #define GPIO_MODE7 0x360 | |
| #define GPIO_MODE8 0x370 | |
| #define GPIO_MODE9 0x380 | |
| #define GPIO_MODE10 0x390 | |
| #define GPIO_MODE11 0x3a0 | |
| #define GPIO_MODE12 0x3b0 | |
| #define GPIO_MODE13 0x3c0 | |
| #define GPIO_MODE14 0x3d0 | |
| #define GPIO_MODE15 0x3e0 | |
| #define GPIO_MODE16 0x3f0 | |
| #define GPIO_MODE17 0x400 | |
| #define GPIO_MODE18 0x410 | |
| #define GPIO_MODE19 0x420 | |
| #define GPIO_MODE20 0x430 | |
| #define GPIO_MODE21 0x440 | |
| /* Pin group registers */ | |
| #define GPIO_IES 0x000 /* 16-bit */ | |
| #define GPIO_SMT 0x010 /* 16-bit */ | |
| #define GPIO_TDSEL 0x020 /* 32-bit */ | |
| #define GPIO_RDSEL 0x028 /* 32-bit */ | |
| #define GPIO_PULLEN 0x030 /* 32-bit */ | |
| #define GPIO_PULLSEL 0x050 /* 32-bit */ | |
| #define GPIO_DRV 0x070 /* 32-bit */ | |
| #define GPIO_PUPD 0x080 /* 32-bit */ | |
| /* Every pin has its own bit(s) */ | |
| #define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _s_width, _x_addrs, _s_bit, _x_bits) \ | |
| PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ | |
| _x_bits, _s_width, 0) | |
| /* All pins in the range share the same bit(s) */ | |
| #define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _s_width, _x_addrs, _s_bit, _x_bits) \ | |
| PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ | |
| _x_bits, _s_width, 1) | |
| static const struct mtk_pin_field_calc mt6735_pin_dir_range[] = { | |
| PIN_FIELD(0, 203, GPIO_DIR, 0x10, 0, 1) | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_di_range[] = { | |
| PIN_FIELD(0, 203, GPIO_DIN, 0x10, 0, 1) | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_do_range[] = { | |
| PIN_FIELD(0, 203, GPIO_DOUT, 0x10, 0, 1) | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_mode_range[] = { | |
| PIN_FIELD(0, 4, GPIO_MODE1, 0, 0, 3), | |
| PIN_FIELD(5, 9, GPIO_MODE1, 0, 16, 3), | |
| PIN_FIELD(10, 14, GPIO_MODE2, 0, 0, 3), | |
| PIN_FIELD(15, 19, GPIO_MODE2, 0, 16, 3), | |
| PIN_FIELD(20, 24, GPIO_MODE3, 0, 0, 3), | |
| PIN_FIELD(25, 29, GPIO_MODE3, 0, 16, 3), | |
| PIN_FIELD(30, 34, GPIO_MODE4, 0, 0, 3), | |
| PIN_FIELD(35, 39, GPIO_MODE4, 0, 16, 3), | |
| PIN_FIELD(40, 44, GPIO_MODE5, 0, 0, 3), | |
| PIN_FIELD(45, 49, GPIO_MODE5, 0, 16, 3), | |
| PIN_FIELD(50, 54, GPIO_MODE6, 0, 0, 3), | |
| PIN_FIELD(55, 59, GPIO_MODE6, 0, 16, 3), | |
| PIN_FIELD(60, 64, GPIO_MODE7, 0, 0, 3), | |
| PIN_FIELD(65, 69, GPIO_MODE7, 0, 16, 3), | |
| PIN_FIELD(70, 74, GPIO_MODE8, 0, 0, 3), | |
| PIN_FIELD(75, 79, GPIO_MODE8, 0, 16, 3), | |
| PIN_FIELD(80, 84, GPIO_MODE9, 0, 0, 3), | |
| PIN_FIELD(85, 89, GPIO_MODE9, 0, 16, 3), | |
| PIN_FIELD(90, 94, GPIO_MODE10, 0, 0, 3), | |
| PIN_FIELD(95, 99, GPIO_MODE10, 0, 16, 3), | |
| PIN_FIELD(100, 104, GPIO_MODE11, 0, 0, 3), | |
| PIN_FIELD(105, 109, GPIO_MODE11, 0, 16, 3), | |
| PIN_FIELD(110, 114, GPIO_MODE12, 0, 0, 3), | |
| PIN_FIELD(115, 119, GPIO_MODE12, 0, 16, 3), | |
| PIN_FIELD(120, 124, GPIO_MODE13, 0, 0, 3), | |
| PIN_FIELD(125, 129, GPIO_MODE13, 0, 16, 3), | |
| PIN_FIELD(130, 134, GPIO_MODE14, 0, 0, 3), | |
| PIN_FIELD(135, 139, GPIO_MODE14, 0, 16, 3), | |
| PIN_FIELD(140, 144, GPIO_MODE15, 0, 0, 3), | |
| PIN_FIELD(145, 149, GPIO_MODE15, 0, 16, 3), | |
| PIN_FIELD(150, 154, GPIO_MODE16, 0, 0, 3), | |
| PIN_FIELD(155, 159, GPIO_MODE16, 0, 16, 3), | |
| PIN_FIELD(160, 164, GPIO_MODE17, 0, 0, 3), | |
| PIN_FIELD(165, 169, GPIO_MODE17, 0, 16, 3), | |
| PIN_FIELD(170, 174, GPIO_MODE18, 0, 0, 3), | |
| PIN_FIELD(175, 179, GPIO_MODE18, 0, 16, 3), | |
| PIN_FIELD(180, 184, GPIO_MODE19, 0, 0, 3), | |
| PIN_FIELD(185, 189, GPIO_MODE19, 0, 16, 3), | |
| PIN_FIELD(190, 194, GPIO_MODE20, 0, 0, 3), | |
| PIN_FIELD(195, 199, GPIO_MODE20, 0, 16, 3), | |
| PIN_FIELD(200, 203, GPIO_MODE21, 0, 0, 3), | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_smt_range[] = { | |
| PINS_FIELD_BASE(0, 4, 2, GPIO_SMT, 16, 0, 10, 1), /* EINT0~4 */ | |
| PINS_FIELD_BASE(5, 8, 3, GPIO_SMT, 16, 0, 3, 1), /* EINT5~8 */ | |
| PINS_FIELD_BASE(9, 12, 3, GPIO_SMT, 16, 0, 6, 1), /* EINT9~12 */ | |
| PINS_FIELD_BASE(13, 18, 1, GPIO_SMT, 16, 0, 0, 1), /* WB_CTRL */ | |
| PINS_FIELD_BASE(19, 21, 1, GPIO_SMT, 16, 0, 1, 1), /* ANTSEL */ | |
| PINS_FIELD_BASE(45, 46, 2, GPIO_SMT, 16, 0, 1, 1), /* CMMCLK */ | |
| PINS_FIELD_BASE(47, 48, 2, GPIO_SMT, 16, 0, 2, 1), /* I2C0 */ | |
| PINS_FIELD_BASE(49, 50, 2, GPIO_SMT, 16, 0, 3, 1), /* I2C1 */ | |
| PINS_FIELD_BASE(51, 52, 2, GPIO_SMT, 16, 0, 4, 1), /* I2C2 */ | |
| PINS_FIELD_BASE(53, 54, 2, GPIO_SMT, 16, 0, 5, 1), /* I2C3 */ | |
| PINS_FIELD_BASE(55, 55, 2, GPIO_SMT, 16, 0, 6, 1), /* SRCLKENAI */ | |
| PINS_FIELD_BASE(56, 56, 2, GPIO_SMT, 16, 0, 7, 1), /* SRCLKENA1 */ | |
| PINS_FIELD_BASE(57, 60, 2, GPIO_SMT, 16, 0, 8, 1), /* UART2/3 */ | |
| PINS_FIELD_BASE(61, 64, 2, GPIO_SMT, 16, 0, 9, 1), /* PCM */ | |
| PINS_FIELD_BASE(65, 68, 3, GPIO_SMT, 16, 0, 0, 1), /* SPI */ | |
| PINS_FIELD_BASE(69, 69, 3, GPIO_SMT, 16, 0, 1, 1), /* DISP_PWM */ | |
| PINS_FIELD_BASE(70, 73, 3, GPIO_SMT, 16, 0, 2, 1), /* JTAG */ | |
| PINS_FIELD_BASE(74, 77, 3, GPIO_SMT, 16, 0, 4, 1), /* UART0/1 */ | |
| PINS_FIELD_BASE(78, 80, 3, GPIO_SMT, 16, 0, 5, 1), /* I2S */ | |
| PINS_FIELD_BASE(81, 86, 3, GPIO_SMT, 16, 0, 7, 1), /* KEYPAD */ | |
| PINS_FIELD_BASE(87, 103, 3, GPIO_SMT, 16, 0, 8, 1), /* BPI5~20, C2K_TKBPI */ | |
| PINS_FIELD_BASE(104, 114, 3, GPIO_SMT, 16, 0, 9, 1), /* RFIC0/1 */ | |
| PINS_FIELD_BASE(118, 136, 4, GPIO_SMT, 16, 0, 0, 1), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */ | |
| PINS_FIELD_BASE(137, 137, 4, GPIO_SMT, 16, 0, 1, 1), /* RTC32K */ | |
| PINS_FIELD_BASE(138, 142, 4, GPIO_SMT, 16, 0, 2, 1), /* PWRAP */ | |
| PINS_FIELD_BASE(143, 145, 4, GPIO_SMT, 16, 0, 3, 1), /* AUD */ | |
| PINS_FIELD_BASE(146, 147, 4, GPIO_SMT, 16, 0, 4, 1), /* LCM_RST, DSI_TE */ | |
| PINS_FIELD_BASE(148, 148, 4, GPIO_SMT, 16, 0, 5, 1), /* SRCLKENA0 */ | |
| PINS_FIELD_BASE(149, 149, 4, GPIO_SMT, 16, 0, 1, 1), /* WATCHDOG */ | |
| PINS_FIELD_BASE(160, 162, 5, GPIO_SMT, 16, 0, 0, 1), /* SIM2 */ | |
| PINS_FIELD_BASE(163, 165, 4, GPIO_SMT, 16, 0, 1, 1), /* SIM1 */ | |
| PINS_FIELD_BASE(166, 166, 5, GPIO_SMT, 16, 0, 2, 1), /* MSDC1_CMD */ | |
| PINS_FIELD_BASE(167, 167, 5, GPIO_SMT, 16, 0, 3, 1), /* MSDC1_CLK */ | |
| PINS_FIELD_BASE(168, 171, 5, GPIO_SMT, 16, 0, 4, 1), /* MSDC1_DAT */ | |
| PINS_FIELD_BASE(172, 172, 6, GPIO_SMT, 16, 0, 0, 1), /* MSDC0_CMD */ | |
| PINS_FIELD_BASE(173, 173, 6, GPIO_SMT, 16, 0, 1, 1), /* MSDC0_DSL */ | |
| PINS_FIELD_BASE(174, 174, 6, GPIO_SMT, 16, 0, 2, 1), /* MSDC0_CLK */ | |
| PINS_FIELD_BASE(175, 182, 6, GPIO_SMT, 16, 0, 3, 1), /* MSDC0_DAT */ | |
| PINS_FIELD_BASE(183, 183, 6, GPIO_SMT, 16, 0, 4, 1), /* MSDC0_RSTB */ | |
| PINS_FIELD_BASE(184, 185, 6, GPIO_SMT, 16, 0, 5, 1), /* FM */ | |
| PINS_FIELD_BASE(186, 189, 6, GPIO_SMT, 16, 0, 6, 1), /* WB SPI */ | |
| PINS_FIELD_BASE(198, 198, 1, GPIO_SMT, 16, 0, 2, 1), /* MSDC2_CMD */ | |
| PINS_FIELD_BASE(199, 199, 1, GPIO_SMT, 16, 0, 3, 1), /* MSDC2_CLK */ | |
| PINS_FIELD_BASE(200, 203, 1, GPIO_SMT, 16, 0, 4, 1), /* MSDC2_DAT */ | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_ies_range[] = { | |
| PINS_FIELD_BASE(0, 4, 2, GPIO_IES, 16, 0, 10, 1), /* EINT0~4 */ | |
| PINS_FIELD_BASE(5, 8, 3, GPIO_IES, 16, 0, 3, 1), /* EINT5~8 */ | |
| PINS_FIELD_BASE(9, 12, 3, GPIO_IES, 16, 0, 6, 1), /* EINT9~12 */ | |
| PINS_FIELD_BASE(13, 18, 1, GPIO_IES, 16, 0, 0, 1), /* WB_CTRL */ | |
| PINS_FIELD_BASE(19, 21, 1, GPIO_IES, 16, 0, 1, 1), /* ANTSEL */ | |
| PINS_FIELD_BASE(45, 46, 2, GPIO_IES, 16, 0, 1, 1), /* CMMCLK */ | |
| PINS_FIELD_BASE(47, 48, 2, GPIO_IES, 16, 0, 2, 1), /* I2C0 */ | |
| PINS_FIELD_BASE(49, 50, 2, GPIO_IES, 16, 0, 3, 1), /* I2C1 */ | |
| PINS_FIELD_BASE(51, 52, 2, GPIO_IES, 16, 0, 4, 1), /* I2C2 */ | |
| PINS_FIELD_BASE(53, 54, 2, GPIO_IES, 16, 0, 5, 1), /* I2C3 */ | |
| PINS_FIELD_BASE(55, 55, 2, GPIO_IES, 16, 0, 6, 1), /* SRCLKENAI */ | |
| PINS_FIELD_BASE(56, 56, 2, GPIO_IES, 16, 0, 7, 1), /* SRCLKENA1 */ | |
| PINS_FIELD_BASE(57, 60, 2, GPIO_IES, 16, 0, 8, 1), /* UART2/3 */ | |
| PINS_FIELD_BASE(61, 64, 2, GPIO_IES, 16, 0, 9, 1), /* PCM */ | |
| PINS_FIELD_BASE(65, 68, 3, GPIO_IES, 16, 0, 0, 1), /* SPI */ | |
| PINS_FIELD_BASE(69, 69, 3, GPIO_IES, 16, 0, 1, 1), /* DISP_PWM */ | |
| PINS_FIELD_BASE(70, 73, 3, GPIO_IES, 16, 0, 2, 1), /* JTAG */ | |
| PINS_FIELD_BASE(74, 77, 3, GPIO_IES, 16, 0, 4, 1), /* UART0/1 */ | |
| PINS_FIELD_BASE(78, 80, 3, GPIO_IES, 16, 0, 5, 1), /* I2S */ | |
| PINS_FIELD_BASE(81, 86, 3, GPIO_IES, 16, 0, 7, 1), /* KEYPAD */ | |
| PINS_FIELD_BASE(87, 103, 3, GPIO_IES, 16, 0, 8, 1), /* BPI5~20, C2K_TKBPI */ | |
| PINS_FIELD_BASE(104, 114, 3, GPIO_IES, 16, 0, 9, 1), /* RFIC0/1 */ | |
| PINS_FIELD_BASE(118, 136, 4, GPIO_IES, 16, 0, 0, 1), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */ | |
| PINS_FIELD_BASE(137, 137, 4, GPIO_IES, 16, 0, 1, 1), /* RTC32K */ | |
| PINS_FIELD_BASE(138, 142, 4, GPIO_IES, 16, 0, 2, 1), /* PWRAP */ | |
| PINS_FIELD_BASE(143, 145, 4, GPIO_IES, 16, 0, 3, 1), /* AUD */ | |
| PINS_FIELD_BASE(146, 147, 4, GPIO_IES, 16, 0, 4, 1), /* LCM_RST, DSI_TE */ | |
| PINS_FIELD_BASE(148, 148, 4, GPIO_IES, 16, 0, 5, 1), /* SRCLKENA0 */ | |
| PINS_FIELD_BASE(149, 149, 4, GPIO_IES, 16, 0, 1, 1), /* WATCHDOG */ | |
| PINS_FIELD_BASE(160, 162, 5, GPIO_IES, 16, 0, 0, 1), /* SIM2 */ | |
| PINS_FIELD_BASE(163, 165, 4, GPIO_IES, 16, 0, 1, 1), /* SIM1 */ | |
| PINS_FIELD_BASE(166, 166, 5, GPIO_IES, 16, 0, 2, 1), /* MSDC1_CMD */ | |
| PINS_FIELD_BASE(167, 167, 5, GPIO_IES, 16, 0, 3, 1), /* MSDC1_CLK */ | |
| PINS_FIELD_BASE(168, 171, 5, GPIO_IES, 16, 0, 4, 1), /* MSDC1_DAT */ | |
| PINS_FIELD_BASE(172, 172, 6, GPIO_IES, 16, 0, 0, 1), /* MSDC0_CMD */ | |
| PINS_FIELD_BASE(173, 173, 6, GPIO_IES, 16, 0, 1, 1), /* MSDC0_DSL */ | |
| PINS_FIELD_BASE(174, 174, 6, GPIO_IES, 16, 0, 2, 1), /* MSDC0_CLK */ | |
| PINS_FIELD_BASE(175, 182, 6, GPIO_IES, 16, 0, 3, 1), /* MSDC0_DAT */ | |
| PINS_FIELD_BASE(183, 183, 6, GPIO_IES, 16, 0, 4, 1), /* MSDC0_RSTB */ | |
| PINS_FIELD_BASE(184, 185, 6, GPIO_IES, 16, 0, 5, 1), /* FM */ | |
| PINS_FIELD_BASE(186, 189, 6, GPIO_IES, 16, 0, 6, 1), /* WB SPI */ | |
| PINS_FIELD_BASE(198, 198, 1, GPIO_IES, 16, 0, 2, 1), /* MSDC2_CMD */ | |
| PINS_FIELD_BASE(199, 199, 1, GPIO_IES, 16, 0, 3, 1), /* MSDC2_CLK */ | |
| PINS_FIELD_BASE(200, 203, 1, GPIO_IES, 16, 0, 4, 1) /* MSDC2_DAT */ | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_tdsel_range[] = { | |
| PINS_FIELD_BASE(0, 4, 2, GPIO_TDSEL, 32, 0x04, 40, 4), /* EINT0~4 */ | |
| PINS_FIELD_BASE(5, 8, 3, GPIO_TDSEL, 32, 0x04, 12, 4), /* EINT5~8 */ | |
| PINS_FIELD_BASE(9, 12, 3, GPIO_TDSEL, 32, 0x04, 24, 4), /* EINT9~12 */ | |
| PINS_FIELD_BASE(13, 18, 1, GPIO_TDSEL, 32, 0, 0, 4), /* WB_CTRL */ | |
| PINS_FIELD_BASE(19, 21, 1, GPIO_TDSEL, 32, 0, 4, 4), /* ANTSEL */ | |
| PINS_FIELD_BASE(45, 46, 2, GPIO_TDSEL, 32, 0x04, 4, 4), /* CMMCLK */ | |
| PINS_FIELD_BASE(47, 48, 2, GPIO_TDSEL, 32, 0x04, 8, 4), /* I2C0 */ | |
| PINS_FIELD_BASE(49, 50, 2, GPIO_TDSEL, 32, 0x04, 12, 4), /* I2C1 */ | |
| PINS_FIELD_BASE(51, 52, 2, GPIO_TDSEL, 32, 0x04, 16, 4), /* I2C2 */ | |
| PINS_FIELD_BASE(53, 54, 2, GPIO_TDSEL, 32, 0x04, 20, 4), /* I2C3 */ | |
| PINS_FIELD_BASE(55, 55, 2, GPIO_TDSEL, 32, 0x04, 24, 4), /* SRCLKENAI */ | |
| PINS_FIELD_BASE(56, 56, 2, GPIO_TDSEL, 32, 0x04, 28, 4), /* SRCLKENA1 */ | |
| PINS_FIELD_BASE(57, 60, 2, GPIO_TDSEL, 32, 0x04, 32, 4), /* UART2/3 */ | |
| PINS_FIELD_BASE(61, 64, 2, GPIO_TDSEL, 32, 0x04, 36, 4), /* PCM */ | |
| PINS_FIELD_BASE(65, 68, 3, GPIO_TDSEL, 32, 0x04, 0, 4), /* SPI */ | |
| PINS_FIELD_BASE(69, 69, 3, GPIO_TDSEL, 32, 0x04, 4, 4), /* DISP_PWM */ | |
| PINS_FIELD_BASE(70, 73, 3, GPIO_TDSEL, 32, 0x04, 8, 4), /* JTAG */ | |
| PINS_FIELD_BASE(74, 77, 3, GPIO_TDSEL, 32, 0x04, 16, 4), /* UART0/1 */ | |
| PINS_FIELD_BASE(78, 80, 3, GPIO_TDSEL, 32, 0x04, 20, 4), /* I2S */ | |
| PINS_FIELD_BASE(81, 86, 3, GPIO_TDSEL, 32, 0x04, 28, 4), /* KEYPAD */ | |
| PINS_FIELD_BASE(87, 103, 3, GPIO_TDSEL, 32, 0x04, 32, 4), /* BPI5~20, C2K_TKBPI */ | |
| PINS_FIELD_BASE(104, 114, 3, GPIO_TDSEL, 32, 0x04, 36, 4), /* RFIC0/1 */ | |
| PINS_FIELD_BASE(118, 136, 4, GPIO_TDSEL, 32, 0, 0, 4), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */ | |
| PINS_FIELD_BASE(137, 137, 4, GPIO_TDSEL, 32, 0, 4, 4), /* RTC32K */ | |
| PINS_FIELD_BASE(138, 142, 4, GPIO_TDSEL, 32, 0, 8, 4), /* PWRAP */ | |
| PINS_FIELD_BASE(143, 145, 4, GPIO_TDSEL, 32, 0, 12, 4), /* AUD */ | |
| PINS_FIELD_BASE(146, 147, 4, GPIO_TDSEL, 32, 0, 16, 4), /* LCM_RST, DSI_TE */ | |
| PINS_FIELD_BASE(148, 148, 4, GPIO_TDSEL, 32, 0, 20, 4), /* SRCLKENA0 */ | |
| PINS_FIELD_BASE(149, 149, 4, GPIO_TDSEL, 32, 0, 4, 4), /* WATCHDOG */ | |
| PINS_FIELD_BASE(160, 162, 5, GPIO_TDSEL, 32, 0, 0, 4), /* SIM2 */ | |
| PINS_FIELD_BASE(163, 165, 5, GPIO_TDSEL, 32, 0, 4, 4), /* SIM1 */ | |
| PINS_FIELD_BASE(166, 166, 5, GPIO_TDSEL, 32, 0, 8, 4), /* MSDC1_CMD */ | |
| PINS_FIELD_BASE(167, 167, 5, GPIO_TDSEL, 32, 0, 12, 4), /* MSDC1_CLK */ | |
| PINS_FIELD_BASE(168, 171, 5, GPIO_TDSEL, 32, 0, 16, 4), /* MSDC1_DAT */ | |
| PINS_FIELD_BASE(172, 172, 6, GPIO_TDSEL, 32, 0, 0, 4), /* MSDC0_CMD */ | |
| PINS_FIELD_BASE(173, 173, 6, GPIO_TDSEL, 32, 0, 4, 4), /* MSDC0_DSL */ | |
| PINS_FIELD_BASE(174, 174, 6, GPIO_TDSEL, 32, 0, 8, 4), /* MSDC0_CLK */ | |
| PINS_FIELD_BASE(175, 182, 6, GPIO_TDSEL, 32, 0, 12, 4), /* MSDC0_DAT */ | |
| PINS_FIELD_BASE(183, 183, 6, GPIO_TDSEL, 32, 0, 16, 4), /* MSDC0_RSTB */ | |
| PINS_FIELD_BASE(184, 185, 6, GPIO_TDSEL, 32, 0, 20, 4), /* FM */ | |
| PINS_FIELD_BASE(186, 189, 6, GPIO_TDSEL, 32, 0, 24, 4), /* WB SPI */ | |
| PINS_FIELD_BASE(198, 198, 1, GPIO_TDSEL, 32, 0, 8, 4), /* MSDC2_CMD */ | |
| PINS_FIELD_BASE(199, 199, 1, GPIO_TDSEL, 32, 0, 12, 4), /* MSDC2_CLK */ | |
| PINS_FIELD_BASE(200, 203, 1, GPIO_TDSEL, 32, 0, 16, 4) /* MSDC2_DAT */ | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_rdsel_range[] = { | |
| PINS_FIELD_BASE(0, 4, 2, GPIO_RDSEL, 32, 0x04, 24, 2), /* EINT0~4 */ | |
| PINS_FIELD_BASE(5, 8, 3, GPIO_RDSEL, 32, 0, 6, 2), /* EINT5~8 */ | |
| PINS_FIELD_BASE(9, 12, 3, GPIO_RDSEL, 32, 0, 12, 2), /* EINT9~12 */ | |
| PINS_FIELD_BASE(13, 18, 1, GPIO_RDSEL, 32, 0, 0, 2), /* WB_CTRL */ | |
| PINS_FIELD_BASE(19, 21, 1, GPIO_RDSEL, 32, 0, 2, 2), /* ANTSEL */ | |
| PINS_FIELD_BASE(45, 46, 2, GPIO_RDSEL, 32, 0x04, 2, 6), /* CMMCLK */ | |
| PINS_FIELD_BASE(47, 48, 2, GPIO_RDSEL, 32, 0x04, 8, 2), /* I2C0 */ | |
| PINS_FIELD_BASE(49, 50, 2, GPIO_RDSEL, 32, 0x04, 10, 2), /* I2C1 */ | |
| PINS_FIELD_BASE(51, 52, 2, GPIO_RDSEL, 32, 0x04, 12, 2), /* I2C2 */ | |
| PINS_FIELD_BASE(53, 54, 2, GPIO_RDSEL, 32, 0x04, 14, 2), /* I2C3 */ | |
| PINS_FIELD_BASE(55, 55, 2, GPIO_RDSEL, 32, 0x04, 16, 2), /* SRCLKENAI */ | |
| PINS_FIELD_BASE(56, 56, 2, GPIO_RDSEL, 32, 0x04, 18, 2), /* SRCLKENA1 */ | |
| PINS_FIELD_BASE(57, 60, 2, GPIO_RDSEL, 32, 0x04, 20, 2), /* UART2/3 */ | |
| PINS_FIELD_BASE(61, 64, 2, GPIO_RDSEL, 32, 0x04, 22, 2), /* PCM */ | |
| PINS_FIELD_BASE(65, 68, 3, GPIO_RDSEL, 32, 0, 0, 2), /* SPI */ | |
| PINS_FIELD_BASE(69, 69, 3, GPIO_RDSEL, 32, 0, 2, 2), /* DISP_PWM */ | |
| PINS_FIELD_BASE(70, 73, 3, GPIO_RDSEL, 32, 0, 4, 2), /* JTAG */ | |
| PINS_FIELD_BASE(74, 77, 3, GPIO_RDSEL, 32, 0, 8, 2), /* UART0/1 */ | |
| PINS_FIELD_BASE(78, 80, 3, GPIO_RDSEL, 32, 0, 10, 2), /* I2S */ | |
| PINS_FIELD_BASE(81, 86, 3, GPIO_RDSEL, 32, 0, 14, 2), /* KEYPAD */ | |
| PINS_FIELD_BASE(87, 103, 3, GPIO_RDSEL, 32, 0, 16, 2), /* BPI5~20, C2K_TKBPI */ | |
| PINS_FIELD_BASE(104, 114, 3, GPIO_RDSEL, 32, 0, 18, 2), /* RFIC0/1 */ | |
| PINS_FIELD_BASE(118, 136, 4, GPIO_RDSEL, 32, 0, 0, 2), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */ | |
| PINS_FIELD_BASE(137, 137, 4, GPIO_RDSEL, 32, 0, 4, 2), /* RTC32K */ | |
| PINS_FIELD_BASE(138, 142, 4, GPIO_RDSEL, 32, 0, 6, 2), /* PWRAP */ | |
| PINS_FIELD_BASE(143, 145, 4, GPIO_RDSEL, 32, 0, 8, 2), /* AUD */ | |
| PINS_FIELD_BASE(146, 147, 4, GPIO_RDSEL, 32, 0, 10, 2), /* LCM_RST, DSI_TE */ | |
| PINS_FIELD_BASE(148, 148, 4, GPIO_RDSEL, 32, 0, 12, 2), /* SRCLKENA0 */ | |
| PINS_FIELD_BASE(149, 149, 4, GPIO_RDSEL, 32, 0, 4, 2), /* WATCHDOG */ | |
| PINS_FIELD_BASE(160, 162, 5, GPIO_RDSEL, 32, 0, 0, 6), /* SIM2 */ | |
| PINS_FIELD_BASE(163, 165, 5, GPIO_RDSEL, 32, 0, 6, 6), /* SIM1 */ | |
| PINS_FIELD_BASE(166, 166, 5, GPIO_RDSEL, 32, 0, 12, 6), /* MSDC1_CMD */ | |
| PINS_FIELD_BASE(167, 167, 5, GPIO_RDSEL, 32, 0, 18, 6), /* MSDC1_CLK */ | |
| PINS_FIELD_BASE(168, 171, 5, GPIO_RDSEL, 32, 0, 24, 6), /* MSDC1_DAT */ | |
| PINS_FIELD_BASE(172, 172, 6, GPIO_RDSEL, 32, 4, 0, 6), /* MSDC0_CMD */ | |
| PINS_FIELD_BASE(173, 173, 6, GPIO_RDSEL, 32, 4, 6, 6), /* MSDC0_DSL */ | |
| PINS_FIELD_BASE(174, 174, 6, GPIO_RDSEL, 32, 4, 12, 6), /* MSDC0_CLK */ | |
| PINS_FIELD_BASE(175, 182, 6, GPIO_RDSEL, 32, 4, 18, 6), /* MSDC0_DAT */ | |
| PINS_FIELD_BASE(183, 183, 6, GPIO_RDSEL, 32, 4, 24, 6), /* MSDC0_RSTB */ | |
| PINS_FIELD_BASE(184, 185, 6, GPIO_RDSEL, 32, 4, 30, 2), /* FM */ | |
| PINS_FIELD_BASE(186, 189, 6, GPIO_RDSEL, 32, 4, 32, 2), /* WB SPI */ | |
| PINS_FIELD_BASE(198, 198, 1, GPIO_RDSEL, 32, 0, 4, 6), /* MSDC2_CMD */ | |
| PINS_FIELD_BASE(199, 199, 1, GPIO_RDSEL, 32, 0, 10, 6), /* MSDC2_CLK */ | |
| PINS_FIELD_BASE(200, 203, 1, GPIO_RDSEL, 32, 0, 16, 6) /* MSDC2_DAT */ | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_drv_range[] = { | |
| PINS_FIELD_BASE(0, 4, 2, GPIO_DRV, 32, 0x04, 41, 2), /* EINT0~4 */ | |
| PINS_FIELD_BASE(5, 8, 3, GPIO_DRV, 32, 0x04, 13, 2), /* EINT5~8 */ | |
| PINS_FIELD_BASE(9, 12, 3, GPIO_DRV, 32, 0x04, 25, 2), /* EINT9~12 */ | |
| PINS_FIELD_BASE(13, 18, 1, GPIO_DRV, 32, 0, 1, 2), /* WB_CTRL */ | |
| PINS_FIELD_BASE(19, 21, 1, GPIO_DRV, 32, 0, 5, 2), /* ANTSEL */ | |
| PINS_FIELD_BASE(45, 46, 2, GPIO_DRV, 32, 0x04, 4, 3), /* CMMCLK */ | |
| PINS_FIELD_BASE(55, 55, 2, GPIO_DRV, 32, 0x04, 25, 2), /* SRCLKENAI */ | |
| PINS_FIELD_BASE(56, 56, 2, GPIO_DRV, 32, 0x04, 29, 2), /* SRCLKENA1 */ | |
| PINS_FIELD_BASE(57, 60, 2, GPIO_DRV, 32, 0x04, 33, 2), /* UART2/3 */ | |
| PINS_FIELD_BASE(61, 64, 2, GPIO_DRV, 32, 0x04, 37, 2), /* PCM */ | |
| PINS_FIELD_BASE(65, 68, 3, GPIO_DRV, 32, 0x04, 1, 2), /* SPI */ | |
| PINS_FIELD_BASE(69, 69, 3, GPIO_DRV, 32, 0x04, 5, 2), /* DISP_PWM */ | |
| PINS_FIELD_BASE(70, 73, 3, GPIO_DRV, 32, 0x04, 9, 2), /* JTAG */ | |
| PINS_FIELD_BASE(74, 77, 3, GPIO_DRV, 32, 0x04, 17, 2), /* UART0/1 */ | |
| PINS_FIELD_BASE(78, 80, 3, GPIO_DRV, 32, 0x04, 21, 2), /* I2S */ | |
| PINS_FIELD_BASE(81, 86, 3, GPIO_DRV, 32, 0x04, 29, 2), /* KEYPAD */ | |
| PINS_FIELD_BASE(87, 103, 3, GPIO_DRV, 32, 0x04, 33, 2), /* BPI5~20, C2K_TKBPI */ | |
| PINS_FIELD_BASE(104, 114, 3, GPIO_DRV, 32, 0x04, 37, 2), /* RFIC0/1 */ | |
| PINS_FIELD_BASE(118, 136, 4, GPIO_DRV, 32, 0, 1, 2), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */ | |
| PINS_FIELD_BASE(137, 137, 4, GPIO_DRV, 32, 0, 5, 2), /* RTC32K */ | |
| PINS_FIELD_BASE(138, 142, 4, GPIO_DRV, 32, 0, 9, 2), /* PWRAP */ | |
| PINS_FIELD_BASE(143, 145, 4, GPIO_DRV, 32, 0, 13, 2), /* AUD */ | |
| PINS_FIELD_BASE(146, 147, 4, GPIO_DRV, 32, 0, 17, 2), /* LCM_RST, DSI_TE */ | |
| PINS_FIELD_BASE(148, 148, 4, GPIO_DRV, 32, 0, 21, 2), /* SRCLKENA0 */ | |
| PINS_FIELD_BASE(149, 149, 4, GPIO_DRV, 32, 0, 5, 2), /* WATCHDOG */ | |
| PINS_FIELD_BASE(160, 162, 5, GPIO_DRV, 32, 0, 1, 2), /* SIM2 */ | |
| PINS_FIELD_BASE(163, 165, 5, GPIO_DRV, 32, 0, 5, 2), /* SIM1 */ | |
| PINS_FIELD_BASE(166, 166, 5, GPIO_DRV, 32, 0, 9, 3), /* MSDC1_CMD */ | |
| PINS_FIELD_BASE(167, 167, 5, GPIO_DRV, 32, 0, 12, 3), /* MSDC1_CLK */ | |
| PINS_FIELD_BASE(168, 171, 5, GPIO_DRV, 32, 0, 16, 3), /* MSDC1_DAT */ | |
| PINS_FIELD_BASE(172, 172, 6, GPIO_DRV, 32, 0, 0, 3), /* MSDC0_CMD */ | |
| PINS_FIELD_BASE(173, 173, 6, GPIO_DRV, 32, 0, 4, 3), /* MSDC0_DSL */ | |
| PINS_FIELD_BASE(174, 174, 6, GPIO_DRV, 32, 0, 8, 3), /* MSDC0_CLK */ | |
| PINS_FIELD_BASE(175, 182, 6, GPIO_DRV, 32, 0, 12, 3), /* MSDC0_DAT */ | |
| PINS_FIELD_BASE(183, 183, 6, GPIO_DRV, 32, 0, 16, 3), /* MSDC0_RSTB */ | |
| PINS_FIELD_BASE(184, 185, 6, GPIO_DRV, 32, 0, 21, 2), /* FM */ | |
| PINS_FIELD_BASE(186, 189, 6, GPIO_DRV, 32, 0, 25, 2), /* WB SPI */ | |
| PINS_FIELD_BASE(198, 198, 1, GPIO_DRV, 32, 0, 8, 3), /* MSDC2_CMD */ | |
| PINS_FIELD_BASE(199, 199, 1, GPIO_DRV, 32, 0, 12, 3), /* MSDC2_CLK */ | |
| PINS_FIELD_BASE(200, 203, 1, GPIO_DRV, 32, 0, 16, 3) /* MSDC2_DAT */ | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_r0_range[] = { | |
| PINS_FIELD_BASE(45, 45, 2, GPIO_PUPD, 32, 0, 0, 1), /* CMMCLK0 */ | |
| PINS_FIELD_BASE(46, 46, 2, GPIO_PUPD, 32, 0, 4, 1), /* CMMCLK1 */ | |
| PINS_FIELD_BASE(81, 81, 3, GPIO_PUPD, 32, 0, 0, 1), /* KPROW0 */ | |
| PINS_FIELD_BASE(82, 82, 3, GPIO_PUPD, 32, 0, 4, 1), /* KPROW1 */ | |
| PINS_FIELD_BASE(83, 83, 3, GPIO_PUPD, 32, 0, 8, 1), /* KPROW2 */ | |
| PINS_FIELD_BASE(84, 84, 3, GPIO_PUPD, 32, 0, 16, 1), /* KPCOL0 */ | |
| PINS_FIELD_BASE(85, 85, 3, GPIO_PUPD, 32, 0, 20, 1), /* KPCOL1 */ | |
| PINS_FIELD_BASE(86, 86, 3, GPIO_PUPD, 32, 0, 24, 1), /* KPCOL2 */ | |
| PINS_FIELD_BASE(160, 160, 5, GPIO_PUPD, 32, 0x10, 32, 1), /* SIM2_SCLK */ | |
| PINS_FIELD_BASE(161, 161, 5, GPIO_PUPD, 32, 0x10, 36, 1), /* SIM2_SRST */ | |
| PINS_FIELD_BASE(162, 162, 5, GPIO_PUPD, 32, 0x10, 44, 1), /* SIM2_SDAT */ | |
| PINS_FIELD_BASE(163, 163, 5, GPIO_PUPD, 32, 0x10, 48, 1), /* SIM1_SCLK */ | |
| PINS_FIELD_BASE(164, 164, 5, GPIO_PUPD, 32, 0x10, 52, 1), /* SIM1_SRST */ | |
| PINS_FIELD_BASE(165, 165, 5, GPIO_PUPD, 32, 0x10, 56, 1), /* SIM1_SDAT */ | |
| PINS_FIELD_BASE(166, 166, 5, GPIO_PUPD, 32, 0x10, 0, 1), /* MSDC1_CMD */ | |
| PINS_FIELD_BASE(167, 167, 5, GPIO_PUPD, 32, 0x10, 4, 1), /* MSDC1_CLK */ | |
| PINS_FIELD_BASE(168, 168, 5, GPIO_PUPD, 32, 0x10, 8, 1), /* MSDC1_DAT0 */ | |
| PINS_FIELD_BASE(169, 169, 5, GPIO_PUPD, 32, 0x10, 12, 1), /* MSDC1_DAT1 */ | |
| PINS_FIELD_BASE(170, 170, 5, GPIO_PUPD, 32, 0x10, 16, 1), /* MSDC1_DAT2 */ | |
| PINS_FIELD_BASE(171, 171, 5, GPIO_PUPD, 32, 0x10, 20, 1), /* MSDC1_DAT3 */ | |
| PINS_FIELD_BASE(172, 172, 6, GPIO_PUPD, 32, 0x10, 0, 1), /* MSDC0_CMD */ | |
| PINS_FIELD_BASE(173, 173, 6, GPIO_PUPD, 32, 0x10, 8, 1), /* MSDC0_DSL */ | |
| PINS_FIELD_BASE(174, 174, 6, GPIO_PUPD, 32, 0x10, 4, 1), /* MSDC0_CLK */ | |
| PINS_FIELD_BASE(175, 175, 6, GPIO_PUPD, 32, 0x10, 12, 1), /* MSDC0_DAT0 */ | |
| PINS_FIELD_BASE(176, 176, 6, GPIO_PUPD, 32, 0x10, 16, 1), /* MSDC0_DAT1 */ | |
| PINS_FIELD_BASE(177, 177, 6, GPIO_PUPD, 32, 0x10, 20, 1), /* MSDC0_DAT2 */ | |
| PINS_FIELD_BASE(178, 178, 6, GPIO_PUPD, 32, 0x10, 24, 1), /* MSDC0_DAT3 */ | |
| PINS_FIELD_BASE(179, 179, 6, GPIO_PUPD, 32, 0x10, 28, 1), /* MSDC0_DAT4 */ | |
| PINS_FIELD_BASE(180, 180, 6, GPIO_PUPD, 32, 0x10, 32, 1), /* MSDC0_DAT5 */ | |
| PINS_FIELD_BASE(181, 181, 6, GPIO_PUPD, 32, 0x10, 36, 1), /* MSDC0_DAT6 */ | |
| PINS_FIELD_BASE(182, 182, 6, GPIO_PUPD, 32, 0x10, 40, 1), /* MSDC0_DAT7 */ | |
| PINS_FIELD_BASE(183, 183, 6, GPIO_PUPD, 32, 0x10, 44, 1), /* MSDC0_RSTB */ | |
| PINS_FIELD_BASE(198, 198, 1, GPIO_PUPD, 32, 0, 0, 1), /* MSDC2_CMD */ | |
| PINS_FIELD_BASE(199, 199, 1, GPIO_PUPD, 32, 0, 4, 1), /* MSDC2_CLK */ | |
| PINS_FIELD_BASE(200, 200, 1, GPIO_PUPD, 32, 0, 8, 1), /* MSDC2_DAT0 */ | |
| PINS_FIELD_BASE(201, 201, 1, GPIO_PUPD, 32, 0, 12, 1), /* MSDC2_DAT1 */ | |
| PINS_FIELD_BASE(202, 202, 1, GPIO_PUPD, 32, 0, 16, 1), /* MSDC2_DAT2 */ | |
| PINS_FIELD_BASE(203, 203, 1, GPIO_PUPD, 32, 0, 20, 1) /* MSDC2_DAT3 */ | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_r1_range[] = { | |
| PINS_FIELD_BASE(45, 45, 2, GPIO_PUPD, 32, 0, 1, 1), /* CMMCLK0 */ | |
| PINS_FIELD_BASE(46, 46, 2, GPIO_PUPD, 32, 0, 5, 1), /* CMMCLK1 */ | |
| PINS_FIELD_BASE(81, 81, 3, GPIO_PUPD, 32, 0, 1, 1), /* KPROW0 */ | |
| PINS_FIELD_BASE(82, 82, 3, GPIO_PUPD, 32, 0, 5, 1), /* KPROW1 */ | |
| PINS_FIELD_BASE(83, 83, 3, GPIO_PUPD, 32, 0, 9, 1), /* KPROW2 */ | |
| PINS_FIELD_BASE(84, 84, 3, GPIO_PUPD, 32, 0, 17, 1), /* KPCOL0 */ | |
| PINS_FIELD_BASE(85, 85, 3, GPIO_PUPD, 32, 0, 21, 1), /* KPCOL1 */ | |
| PINS_FIELD_BASE(86, 86, 3, GPIO_PUPD, 32, 0, 25, 1), /* KPCOL2 */ | |
| PINS_FIELD_BASE(160, 160, 5, GPIO_PUPD, 32, 0x10, 33, 1), /* SIM2_SCLK */ | |
| PINS_FIELD_BASE(161, 161, 5, GPIO_PUPD, 32, 0x10, 37, 1), /* SIM2_SRST */ | |
| PINS_FIELD_BASE(162, 162, 5, GPIO_PUPD, 32, 0x10, 45, 1), /* SIM2_SDAT */ | |
| PINS_FIELD_BASE(163, 163, 5, GPIO_PUPD, 32, 0x10, 49, 1), /* SIM1_SCLK */ | |
| PINS_FIELD_BASE(164, 164, 5, GPIO_PUPD, 32, 0x10, 53, 1), /* SIM1_SRST */ | |
| PINS_FIELD_BASE(165, 165, 5, GPIO_PUPD, 32, 0x10, 57, 1), /* SIM1_SDAT */ | |
| PINS_FIELD_BASE(166, 166, 5, GPIO_PUPD, 32, 0x10, 1, 1), /* MSDC1_CMD */ | |
| PINS_FIELD_BASE(167, 167, 5, GPIO_PUPD, 32, 0x10, 5, 1), /* MSDC1_CLK */ | |
| PINS_FIELD_BASE(168, 168, 5, GPIO_PUPD, 32, 0x10, 9, 1), /* MSDC1_DAT0 */ | |
| PINS_FIELD_BASE(169, 169, 5, GPIO_PUPD, 32, 0x10, 13, 1), /* MSDC1_DAT1 */ | |
| PINS_FIELD_BASE(170, 170, 5, GPIO_PUPD, 32, 0x10, 17, 1), /* MSDC1_DAT2 */ | |
| PINS_FIELD_BASE(171, 171, 5, GPIO_PUPD, 32, 0x10, 21, 1), /* MSDC1_DAT3 */ | |
| PINS_FIELD_BASE(172, 172, 6, GPIO_PUPD, 32, 0x10, 1, 1), /* MSDC0_CMD */ | |
| PINS_FIELD_BASE(173, 173, 6, GPIO_PUPD, 32, 0x10, 9, 1), /* MSDC0_DSL */ | |
| PINS_FIELD_BASE(174, 174, 6, GPIO_PUPD, 32, 0x10, 5, 1), /* MSDC0_CLK */ | |
| PINS_FIELD_BASE(175, 175, 6, GPIO_PUPD, 32, 0x10, 13, 1), /* MSDC0_DAT0 */ | |
| PINS_FIELD_BASE(176, 176, 6, GPIO_PUPD, 32, 0x10, 17, 1), /* MSDC0_DAT1 */ | |
| PINS_FIELD_BASE(177, 177, 6, GPIO_PUPD, 32, 0x10, 21, 1), /* MSDC0_DAT2 */ | |
| PINS_FIELD_BASE(178, 178, 6, GPIO_PUPD, 32, 0x10, 25, 1), /* MSDC0_DAT3 */ | |
| PINS_FIELD_BASE(179, 179, 6, GPIO_PUPD, 32, 0x10, 29, 1), /* MSDC0_DAT4 */ | |
| PINS_FIELD_BASE(180, 180, 6, GPIO_PUPD, 32, 0x10, 33, 1), /* MSDC0_DAT5 */ | |
| PINS_FIELD_BASE(181, 181, 6, GPIO_PUPD, 32, 0x10, 37, 1), /* MSDC0_DAT6 */ | |
| PINS_FIELD_BASE(182, 182, 6, GPIO_PUPD, 32, 0x10, 41, 1), /* MSDC0_DAT7 */ | |
| PINS_FIELD_BASE(183, 183, 6, GPIO_PUPD, 32, 0x10, 45, 1), /* MSDC0_RSTB */ | |
| PINS_FIELD_BASE(198, 198, 1, GPIO_PUPD, 32, 0, 1, 1), /* MSDC2_CMD */ | |
| PINS_FIELD_BASE(199, 199, 1, GPIO_PUPD, 32, 0, 5, 1), /* MSDC2_CLK */ | |
| PINS_FIELD_BASE(200, 200, 1, GPIO_PUPD, 32, 0, 9, 1), /* MSDC2_DAT0 */ | |
| PINS_FIELD_BASE(201, 201, 1, GPIO_PUPD, 32, 0, 13, 1), /* MSDC2_DAT1 */ | |
| PINS_FIELD_BASE(202, 202, 1, GPIO_PUPD, 32, 0, 17, 1), /* MSDC2_DAT2 */ | |
| PINS_FIELD_BASE(203, 203, 1, GPIO_PUPD, 32, 0, 21, 1) /* MSDC2_DAT3 */ | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_pupd_range[] = { | |
| PINS_FIELD_BASE(45, 45, 2, GPIO_PUPD, 32, 0, 2, 1), /* CMMCLK0 */ | |
| PINS_FIELD_BASE(46, 46, 2, GPIO_PUPD, 32, 0, 6, 1), /* CMMCLK1 */ | |
| PINS_FIELD_BASE(81, 81, 3, GPIO_PUPD, 32, 0, 2, 1), /* KPROW0 */ | |
| PINS_FIELD_BASE(82, 82, 3, GPIO_PUPD, 32, 0, 6, 1), /* KPROW1 */ | |
| PINS_FIELD_BASE(83, 83, 3, GPIO_PUPD, 32, 0, 10, 1), /* KPROW2 */ | |
| PINS_FIELD_BASE(84, 84, 3, GPIO_PUPD, 32, 0, 18, 1), /* KPCOL0 */ | |
| PINS_FIELD_BASE(85, 85, 3, GPIO_PUPD, 32, 0, 22, 1), /* KPCOL1 */ | |
| PINS_FIELD_BASE(86, 86, 3, GPIO_PUPD, 32, 0, 26, 1), /* KPCOL2 */ | |
| PINS_FIELD_BASE(160, 160, 5, GPIO_PUPD, 32, 0x10, 34, 1), /* SIM2_SCLK */ | |
| PINS_FIELD_BASE(161, 161, 5, GPIO_PUPD, 32, 0x10, 38, 1), /* SIM2_SRST */ | |
| PINS_FIELD_BASE(162, 162, 5, GPIO_PUPD, 32, 0x10, 46, 1), /* SIM2_SDAT */ | |
| PINS_FIELD_BASE(163, 163, 5, GPIO_PUPD, 32, 0x10, 50, 1), /* SIM1_SCLK */ | |
| PINS_FIELD_BASE(164, 164, 5, GPIO_PUPD, 32, 0x10, 54, 1), /* SIM1_SRST */ | |
| PINS_FIELD_BASE(165, 165, 5, GPIO_PUPD, 32, 0x10, 58, 1), /* SIM1_SDAT */ | |
| PINS_FIELD_BASE(166, 166, 5, GPIO_PUPD, 32, 0x10, 2, 1), /* MSDC1_CMD */ | |
| PINS_FIELD_BASE(167, 167, 5, GPIO_PUPD, 32, 0x10, 6, 1), /* MSDC1_CLK */ | |
| PINS_FIELD_BASE(168, 168, 5, GPIO_PUPD, 32, 0x10, 10, 1), /* MSDC1_DAT0 */ | |
| PINS_FIELD_BASE(169, 169, 5, GPIO_PUPD, 32, 0x10, 14, 1), /* MSDC1_DAT1 */ | |
| PINS_FIELD_BASE(170, 170, 5, GPIO_PUPD, 32, 0x10, 18, 1), /* MSDC1_DAT2 */ | |
| PINS_FIELD_BASE(171, 171, 5, GPIO_PUPD, 32, 0x10, 22, 1), /* MSDC1_DAT3 */ | |
| PINS_FIELD_BASE(172, 172, 6, GPIO_PUPD, 32, 0x10, 2, 1), /* MSDC0_CMD */ | |
| PINS_FIELD_BASE(173, 173, 6, GPIO_PUPD, 32, 0x10, 10, 1), /* MSDC0_DSL */ | |
| PINS_FIELD_BASE(174, 174, 6, GPIO_PUPD, 32, 0x10, 6, 1), /* MSDC0_CLK */ | |
| PINS_FIELD_BASE(175, 175, 6, GPIO_PUPD, 32, 0x10, 14, 1), /* MSDC0_DAT0 */ | |
| PINS_FIELD_BASE(176, 176, 6, GPIO_PUPD, 32, 0x10, 18, 1), /* MSDC0_DAT1 */ | |
| PINS_FIELD_BASE(177, 177, 6, GPIO_PUPD, 32, 0x10, 22, 1), /* MSDC0_DAT2 */ | |
| PINS_FIELD_BASE(178, 178, 6, GPIO_PUPD, 32, 0x10, 26, 1), /* MSDC0_DAT3 */ | |
| PINS_FIELD_BASE(179, 179, 6, GPIO_PUPD, 32, 0x10, 30, 1), /* MSDC0_DAT4 */ | |
| PINS_FIELD_BASE(180, 180, 6, GPIO_PUPD, 32, 0x10, 34, 1), /* MSDC0_DAT5 */ | |
| PINS_FIELD_BASE(181, 181, 6, GPIO_PUPD, 32, 0x10, 38, 1), /* MSDC0_DAT6 */ | |
| PINS_FIELD_BASE(182, 182, 6, GPIO_PUPD, 32, 0x10, 42, 1), /* MSDC0_DAT7 */ | |
| PINS_FIELD_BASE(183, 183, 6, GPIO_PUPD, 32, 0x10, 46, 1), /* MSDC0_RSTB */ | |
| PINS_FIELD_BASE(198, 198, 1, GPIO_PUPD, 32, 0, 2, 1), /* MSDC2_CMD */ | |
| PINS_FIELD_BASE(199, 199, 1, GPIO_PUPD, 32, 0, 6, 1), /* MSDC2_CLK */ | |
| PINS_FIELD_BASE(200, 200, 1, GPIO_PUPD, 32, 0, 10, 1), /* MSDC2_DAT0 */ | |
| PINS_FIELD_BASE(201, 201, 1, GPIO_PUPD, 32, 0, 14, 1), /* MSDC2_DAT1 */ | |
| PINS_FIELD_BASE(202, 202, 1, GPIO_PUPD, 32, 0, 18, 1), /* MSDC2_DAT2 */ | |
| PINS_FIELD_BASE(203, 203, 1, GPIO_PUPD, 32, 0, 22, 1) /* MSDC2_DAT3 */ | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_pullen_range[] = { | |
| PIN_FIELD_BASE(0, 4, 2, GPIO_PULLEN, 32, 0, 23, 1), | |
| PIN_FIELD_BASE(5, 8, 3, GPIO_PULLEN, 32, 0x10, 9, 1), | |
| PIN_FIELD_BASE(9, 12, 3, GPIO_PULLEN, 32, 0x10, 20, 1), | |
| PIN_FIELD_BASE(13, 21, 1, GPIO_PULLEN, 32, 0, 0, 1), | |
| PIN_FIELD_BASE(42, 44, 2, GPIO_PULLEN, 32, 0, 0, 1), | |
| PIN_FIELD_BASE(47, 64, 2, GPIO_PULLEN, 32, 0, 5, 1), | |
| PIN_FIELD_BASE(65, 73, 3, GPIO_PULLEN, 32, 0x10, 0, 1), | |
| PIN_FIELD_BASE(74, 80, 3, GPIO_PULLEN, 32, 0x10, 13, 1), | |
| PIN_FIELD_BASE(87, 114, 3, GPIO_PULLEN, 32, 0x10, 30, 1), | |
| PIN_FIELD_BASE(118, 149, 4, GPIO_PULLEN, 32, 0, 0, 1), | |
| PIN_FIELD_BASE(184, 189, 6, GPIO_PULLEN, 32, 0x10, 12, 1) | |
| }; | |
| static const struct mtk_pin_field_calc mt6735_pin_pullsel_range[] = { | |
| PIN_FIELD_BASE(0, 4, 2, GPIO_PULLSEL, 32, 0, 23, 1), | |
| PIN_FIELD_BASE(5, 8, 3, GPIO_PULLSEL, 32, 0x10, 9, 1), | |
| PIN_FIELD_BASE(9, 12, 3, GPIO_PULLSEL, 32, 0x10, 20, 1), | |
| PIN_FIELD_BASE(13, 21, 1, GPIO_PULLSEL, 32, 0, 0, 1), | |
| PIN_FIELD_BASE(42, 44, 2, GPIO_PULLSEL, 32, 0, 0, 1), | |
| PIN_FIELD_BASE(47, 64, 2, GPIO_PULLSEL, 32, 0, 5, 1), | |
| PIN_FIELD_BASE(65, 73, 3, GPIO_PULLSEL, 32, 0x10, 0, 1), | |
| PIN_FIELD_BASE(74, 80, 3, GPIO_PULLSEL, 32, 0x10, 13, 1), | |
| PIN_FIELD_BASE(87, 114, 3, GPIO_PULLSEL, 32, 0x10, 30, 1), | |
| PIN_FIELD_BASE(118, 149, 4, GPIO_PULLSEL, 32, 0, 0, 1), | |
| PIN_FIELD_BASE(184, 189, 6, GPIO_PULLSEL, 32, 0x10, 12, 1) | |
| }; | |
| static const struct mtk_pin_reg_calc mt6735_reg_cals[PINCTRL_PIN_REG_MAX] = { | |
| [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6735_pin_dir_range), | |
| [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6735_pin_di_range), | |
| [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6735_pin_do_range), | |
| [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6735_pin_mode_range), | |
| [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6735_pin_smt_range), | |
| [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6735_pin_ies_range), | |
| [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt6735_pin_tdsel_range), | |
| [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt6735_pin_rdsel_range), | |
| [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6735_pin_drv_range), | |
| [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6735_pin_r0_range), | |
| [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6735_pin_r1_range), | |
| [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6735_pin_pupd_range), | |
| [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt6735_pin_pullen_range), | |
| [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt6735_pin_pullsel_range), | |
| }; | |
| static const struct mtk_pin_field_calc mt6735m_pin_dir_range[] = { | |
| PIN_FIELD(0, 197, GPIO_DIR, 0x10, 0, 1) | |
| }; | |
| static const struct mtk_pin_field_calc mt6735m_pin_di_range[] = { | |
| PIN_FIELD(0, 197, GPIO_DIN, 0x10, 0, 1) | |
| }; | |
| static const struct mtk_pin_field_calc mt6735m_pin_do_range[] = { | |
| PIN_FIELD(0, 197, GPIO_DOUT, 0x10, 0, 1) | |
| }; | |
| static const struct mtk_pin_field_calc mt6735m_pin_mode_range[] = { | |
| PIN_FIELD(0, 4, GPIO_MODE1, 0, 0, 3), | |
| PIN_FIELD(5, 9, GPIO_MODE1, 0, 16, 3), | |
| PIN_FIELD(10, 14, GPIO_MODE2, 0, 0, 3), | |
| PIN_FIELD(15, 19, GPIO_MODE2, 0, 16, 3), | |
| PIN_FIELD(20, 24, GPIO_MODE3, 0, 0, 3), | |
| PIN_FIELD(25, 29, GPIO_MODE3, 0, 16, 3), | |
| PIN_FIELD(30, 34, GPIO_MODE4, 0, 0, 3), | |
| PIN_FIELD(35, 39, GPIO_MODE4, 0, 16, 3), | |
| PIN_FIELD(40, 44, GPIO_MODE5, 0, 0, 3), | |
| PIN_FIELD(45, 49, GPIO_MODE5, 0, 16, 3), | |
| PIN_FIELD(50, 54, GPIO_MODE6, 0, 0, 3), | |
| PIN_FIELD(55, 59, GPIO_MODE6, 0, 16, 3), | |
| PIN_FIELD(60, 64, GPIO_MODE7, 0, 0, 3), | |
| PIN_FIELD(65, 69, GPIO_MODE7, 0, 16, 3), | |
| PIN_FIELD(70, 74, GPIO_MODE8, 0, 0, 3), | |
| PIN_FIELD(75, 79, GPIO_MODE8, 0, 16, 3), | |
| PIN_FIELD(80, 84, GPIO_MODE9, 0, 0, 3), | |
| PIN_FIELD(85, 89, GPIO_MODE9, 0, 16, 3), | |
| PIN_FIELD(90, 94, GPIO_MODE10, 0, 0, 3), | |
| PIN_FIELD(95, 99, GPIO_MODE10, 0, 16, 3), | |
| PIN_FIELD(100, 104, GPIO_MODE11, 0, 0, 3), | |
| PIN_FIELD(105, 109, GPIO_MODE11, 0, 16, 3), | |
| PIN_FIELD(110, 114, GPIO_MODE12, 0, 0, 3), | |
| PIN_FIELD(115, 119, GPIO_MODE12, 0, 16, 3), | |
| PIN_FIELD(120, 124, GPIO_MODE13, 0, 0, 3), | |
| PIN_FIELD(125, 129, GPIO_MODE13, 0, 16, 3), | |
| PIN_FIELD(130, 134, GPIO_MODE14, 0, 0, 3), | |
| PIN_FIELD(135, 139, GPIO_MODE14, 0, 16, 3), | |
| PIN_FIELD(140, 144, GPIO_MODE15, 0, 0, 3), | |
| PIN_FIELD(145, 149, GPIO_MODE15, 0, 16, 3), | |
| PIN_FIELD(150, 154, GPIO_MODE16, 0, 0, 3), | |
| PIN_FIELD(155, 159, GPIO_MODE16, 0, 16, 3), | |
| PIN_FIELD(160, 164, GPIO_MODE17, 0, 0, 3), | |
| PIN_FIELD(165, 169, GPIO_MODE17, 0, 16, 3), | |
| PIN_FIELD(170, 174, GPIO_MODE18, 0, 0, 3), | |
| PIN_FIELD(175, 179, GPIO_MODE18, 0, 16, 3), | |
| PIN_FIELD(180, 184, GPIO_MODE19, 0, 0, 3), | |
| PIN_FIELD(185, 189, GPIO_MODE19, 0, 16, 3), | |
| PIN_FIELD(190, 194, GPIO_MODE20, 0, 0, 3), | |
| PIN_FIELD(195, 197, GPIO_MODE20, 0, 16, 3), | |
| }; | |
| /* | |
| * Rather than redefining all tables for MT6735M just to remove the 6 MSDC2 | |
| * pins at the end, reuse the MT6735 tables and exclude the MSDC2 pin fields | |
| * by subtracting their count from the array size when possible | |
| */ | |
| static const struct mtk_pin_reg_calc mt6735m_reg_cals[PINCTRL_PIN_REG_MAX] = { | |
| [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6735m_pin_dir_range), | |
| [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6735m_pin_di_range), | |
| [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6735m_pin_do_range), | |
| [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6735m_pin_mode_range), | |
| [PINCTRL_PIN_REG_SMT] = { mt6735_pin_smt_range, | |
| ARRAY_SIZE(mt6735_pin_smt_range) - 3 }, | |
| [PINCTRL_PIN_REG_IES] = { mt6735_pin_ies_range, | |
| ARRAY_SIZE(mt6735_pin_ies_range) - 3 }, | |
| [PINCTRL_PIN_REG_TDSEL] = { mt6735_pin_tdsel_range, | |
| ARRAY_SIZE(mt6735_pin_tdsel_range) - 3 }, | |
| [PINCTRL_PIN_REG_RDSEL] = { mt6735_pin_rdsel_range, | |
| ARRAY_SIZE(mt6735_pin_rdsel_range) - 3 }, | |
| [PINCTRL_PIN_REG_DRV] = { mt6735_pin_drv_range, | |
| ARRAY_SIZE(mt6735_pin_drv_range) - 3 }, | |
| [PINCTRL_PIN_REG_R0] = { mt6735_pin_r0_range, | |
| ARRAY_SIZE(mt6735_pin_r0_range) - 6 }, | |
| [PINCTRL_PIN_REG_R1] = { mt6735_pin_r1_range, | |
| ARRAY_SIZE(mt6735_pin_r1_range) - 6 }, | |
| [PINCTRL_PIN_REG_PUPD] = { mt6735_pin_pupd_range, | |
| ARRAY_SIZE(mt6735_pin_pupd_range) - 6 }, | |
| [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt6735_pin_pullen_range), | |
| [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt6735_pin_pullsel_range), | |
| }; | |
| static const unsigned int mt6735_pull_type[] = { | |
| MTK_PULL_PULLSEL_TYPE, /* 0 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 1 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 2 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 3 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 4 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 5 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 6 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 7 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 8 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 9 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 10 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 11 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 12 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 13 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 14 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 15 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 16 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 17 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 18 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 19 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 20 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 21 */ | |
| /* MIPI CSI pins have no configurable pull resistors */ | |
| 0, /* 22 RDN0 */ | |
| 0, /* 23 RDP0 */ | |
| 0, /* 24 RDN1 */ | |
| 0, /* 25 RDP1 */ | |
| 0, /* 26 RCN */ | |
| 0, /* 27 RCP */ | |
| 0, /* 28 RDN2 */ | |
| 0, /* 29 RDP2 */ | |
| 0, /* 30 RDN3 */ | |
| 0, /* 31 RDP3 */ | |
| 0, /* 32 RDN0_A */ | |
| 0, /* 33 RDP0_A */ | |
| 0, /* 34 RDN1_A */ | |
| 0, /* 35 RDP1_A */ | |
| 0, /* 36 RCN_A */ | |
| 0, /* 37 RCP_A */ | |
| 0, /* 38 RDN2_A */ | |
| 0, /* 39 RDP2_A */ | |
| 0, /* 40 RDN3_A */ | |
| 0, /* 41 RDP3_A */ | |
| MTK_PULL_PULLSEL_TYPE, /* 42 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 43 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 44 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 45 CMMCLK0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 46 CMMCLK1 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 47 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 48 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 49 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 50 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 51 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 52 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 53 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 54 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 55 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 56 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 57 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 58 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 59 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 60 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 61 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 62 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 63 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 64 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 65 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 66 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 67 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 68 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 69 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 70 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 71 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 72 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 73 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 74 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 75 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 76 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 77 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 78 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 79 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 80 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 81 KROW0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 82 KROW1 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 83 KROW2 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 84 KCOL0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 85 KCOL1 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 86 KCOL2 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 87 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 88 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 89 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 90 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 91 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 92 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 93 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 94 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 95 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 96 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 97 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 98 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 99 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 100 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 101 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 102 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 103 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 104 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 105 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 106 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 107 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 108 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 109 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 110 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 111 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 112 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 113 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 114 */ | |
| /* Configuration for AUXADC pins is set by APMIXEDSYS */ | |
| 0, /* 115 AUXIN0 */ | |
| 0, /* 116 AUXIN1 */ | |
| 0, /* 117 AUXIN2 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 118 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 119 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 120 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 121 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 122 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 123 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 124 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 125 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 126 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 127 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 128 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 129 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 130 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 131 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 132 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 133 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 134 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 135 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 136 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 137 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 138 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 139 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 140 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 141 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 142 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 143 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 144 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 145 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 146 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 147 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 148 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 149 */ | |
| /* MIPI DSI pins have no configurable pull resistors */ | |
| 0, /* 150 TDP0 */ | |
| 0, /* 151 TDN0 */ | |
| 0, /* 152 TDP1 */ | |
| 0, /* 153 TDN1 */ | |
| 0, /* 154 TCP */ | |
| 0, /* 155 TCN */ | |
| 0, /* 156 TDP2 */ | |
| 0, /* 157 TDN2 */ | |
| 0, /* 158 TDP3 */ | |
| 0, /* 159 TDN3 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 160 MD_SIM2_SCLK */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 161 MD_SIM2_SRST */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 162 MD_SIM2_SDAT */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 163 MD_SIM1_SCLK */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 164 MD_SIM1_SRST */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 165 MD_SIM1_SDAT */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 166 MSDC1_CMD */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 167 MSDC1_CLK */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 168 MSDC1_DAT0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 169 MSDC1_DAT1 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 170 MSDC1_DAT2 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 171 MSDC1_DAT3 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 172 MSDC0_CMD */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 173 MSDC0_DSL */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 174 MSDC0_CLK */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 175 MSDC0_DAT0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 176 MSDC0_DAT1 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 177 MSDC0_DAT2 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 178 MSDC0_DAT3 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 179 MSDC0_DAT4 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 180 MSDC0_DAT5 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 181 MSDC0_DAT6 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 182 MSDC0_DAT7 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 183 MSDC0_RSTB */ | |
| MTK_PULL_PULLSEL_TYPE, /* 184 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 185 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 186 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 187 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 188 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 189 */ | |
| /* | |
| * GPS/WIFI/BT pins have no pull resistors configurable by the GPIO | |
| * controller. They might be configured by CONSYS but we can't know | |
| * for sure due to lack of documentation. | |
| */ | |
| 0, /* 190 GPS_RXQN */ | |
| 0, /* 191 GPS_RXQP */ | |
| 0, /* 192 GPS_RXIN */ | |
| 0, /* 193 GPS_RXIP */ | |
| 0, /* 194 WB_RXQN */ | |
| 0, /* 195 WB_RXQP */ | |
| 0, /* 196 WB_RXIN */ | |
| 0, /* 197 WB_RXIP */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 198 MSDC2_CMD */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 199 MSDC2_CLK */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 200 MSDC2_DAT0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 201 MSDC2_DAT1 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 202 MSDC2_DAT2 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 203 MSDC2_DAT3 */ | |
| /* No pull resistors for virtual EINT pins */ | |
| 0, /* 204 */ | |
| 0, /* 205 */ | |
| 0, /* 206 */ | |
| 0, /* 207 */ | |
| 0, /* 208 */ | |
| 0, /* 209 */ | |
| 0, /* 210 */ | |
| 0, /* 211 */ | |
| 0, /* 212 */ | |
| 0 /* 213 */ | |
| }; | |
| static const unsigned int mt6735m_pull_type[] = { | |
| MTK_PULL_PULLSEL_TYPE, /* 0 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 1 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 2 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 3 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 4 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 5 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 6 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 7 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 8 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 9 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 10 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 11 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 12 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 13 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 14 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 15 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 16 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 17 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 18 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 19 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 20 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 21 */ | |
| /* MIPI CSI pins have no configurable pull resistors */ | |
| 0, /* 22 RDN0 */ | |
| 0, /* 23 RDP0 */ | |
| 0, /* 24 RDN1 */ | |
| 0, /* 25 RDP1 */ | |
| 0, /* 26 RCN */ | |
| 0, /* 27 RCP */ | |
| 0, /* 28 RDN2 */ | |
| 0, /* 29 RDP2 */ | |
| 0, /* 30 RDN3 */ | |
| 0, /* 31 RDP3 */ | |
| 0, /* 32 RDN0_A */ | |
| 0, /* 33 RDP0_A */ | |
| 0, /* 34 RDN1_A */ | |
| 0, /* 35 RDP1_A */ | |
| 0, /* 36 RCN_A */ | |
| 0, /* 37 RCP_A */ | |
| 0, /* 38 RDN2_A */ | |
| 0, /* 39 RDP2_A */ | |
| 0, /* 40 RDN3_A */ | |
| 0, /* 41 RDP3_A */ | |
| MTK_PULL_PULLSEL_TYPE, /* 42 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 43 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 44 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 45 CMMCLK0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 46 CMMCLK1 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 47 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 48 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 49 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 50 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 51 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 52 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 53 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 54 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 55 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 56 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 57 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 58 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 59 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 60 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 61 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 62 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 63 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 64 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 65 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 66 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 67 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 68 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 69 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 70 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 71 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 72 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 73 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 74 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 75 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 76 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 77 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 78 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 79 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 80 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 81 KROW0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 82 KROW1 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 83 KROW2 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 84 KCOL0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 85 KCOL1 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 86 KCOL2 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 87 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 88 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 89 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 90 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 91 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 92 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 93 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 94 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 95 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 96 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 97 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 98 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 99 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 100 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 101 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 102 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 103 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 104 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 105 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 106 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 107 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 108 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 109 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 110 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 111 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 112 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 113 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 114 */ | |
| /* Configuration for AUXADC pins is set by APMIXEDSYS */ | |
| 0, /* 115 AUXIN0 */ | |
| 0, /* 116 AUXIN1 */ | |
| 0, /* 117 AUXIN2 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 118 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 119 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 120 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 121 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 122 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 123 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 124 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 125 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 126 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 127 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 128 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 129 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 130 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 131 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 132 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 133 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 134 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 135 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 136 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 137 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 138 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 139 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 140 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 141 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 142 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 143 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 144 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 145 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 146 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 147 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 148 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 149 */ | |
| /* MIPI DSI pins have no configurable pull resistors */ | |
| 0, /* 150 TDP0 */ | |
| 0, /* 151 TDN0 */ | |
| 0, /* 152 TDP1 */ | |
| 0, /* 153 TDN1 */ | |
| 0, /* 154 TCP */ | |
| 0, /* 155 TCN */ | |
| 0, /* 156 TDP2 */ | |
| 0, /* 157 TDN2 */ | |
| 0, /* 158 TDP3 */ | |
| 0, /* 159 TDN3 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 160 MD_SIM2_SCLK */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 161 MD_SIM2_SRST */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 162 MD_SIM2_SDAT */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 163 MD_SIM1_SCLK */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 164 MD_SIM1_SRST */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 165 MD_SIM1_SDAT */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 166 MSDC1_CMD */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 167 MSDC1_CLK */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 168 MSDC1_DAT0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 169 MSDC1_DAT1 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 170 MSDC1_DAT2 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 171 MSDC1_DAT3 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 172 MSDC0_CMD */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 173 MSDC0_DSL */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 174 MSDC0_CLK */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 175 MSDC0_DAT0 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 176 MSDC0_DAT1 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 177 MSDC0_DAT2 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 178 MSDC0_DAT3 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 179 MSDC0_DAT4 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 180 MSDC0_DAT5 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 181 MSDC0_DAT6 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 182 MSDC0_DAT7 */ | |
| MTK_PULL_PUPD_R1R0_TYPE, /* 183 MSDC0_RSTB */ | |
| MTK_PULL_PULLSEL_TYPE, /* 184 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 185 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 186 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 187 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 188 */ | |
| MTK_PULL_PULLSEL_TYPE, /* 189 */ | |
| /* | |
| * GPS/WIFI/BT pins have no pull resistors configurable by the GPIO | |
| * controller. They might be configured by CONSYS but we can't know | |
| * for sure due to lack of documentation. | |
| */ | |
| 0, /* 190 GPS_RXQN */ | |
| 0, /* 191 GPS_RXQP */ | |
| 0, /* 192 GPS_RXIN */ | |
| 0, /* 193 GPS_RXIP */ | |
| 0, /* 194 WB_RXQN */ | |
| 0, /* 195 WB_RXQP */ | |
| 0, /* 196 WB_RXIN */ | |
| 0, /* 197 WB_RXIP */ | |
| /* No pull resistors for virtual EINT pins */ | |
| 0, /* 198 */ | |
| 0, /* 199 */ | |
| 0, /* 200 */ | |
| 0, /* 201 */ | |
| 0, /* 202 */ | |
| 0, /* 203 */ | |
| 0, /* 204 */ | |
| 0, /* 205 */ | |
| 0, /* 206 */ | |
| 0, /* 207 */ | |
| 0, /* 208 */ | |
| 0, /* 209 */ | |
| 0, /* 210 */ | |
| 0, /* 211 */ | |
| 0, /* 212 */ | |
| 0 /* 213 */ | |
| }; | |
| static const char * const mt6735_pinctrl_register_base_names[] = { | |
| "gpio", "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5" | |
| }; | |
| static const struct mtk_eint_hw mt6735_eint_hw = { | |
| .port_mask = 7, | |
| .ports = 6, | |
| .ap_num = 224, | |
| .db_cnt = 16, | |
| .db_time = debounce_time_mt6765, | |
| }; | |
| static const struct mtk_pin_soc mt6735_data = { | |
| .reg_cal = mt6735_reg_cals, | |
| .pins = mtk_pins_mt6735, | |
| .npins = ARRAY_SIZE(mtk_pins_mt6735), | |
| .ngrps = ARRAY_SIZE(mtk_pins_mt6735), | |
| .eint_hw = &mt6735_eint_hw, | |
| .gpio_m = 0, | |
| .ies_present = true, | |
| .base_names = mt6735_pinctrl_register_base_names, | |
| .nbase_names = ARRAY_SIZE(mt6735_pinctrl_register_base_names), | |
| .pull_type = mt6735_pull_type, | |
| .bias_set_combo = mtk_pinconf_bias_set_combo, | |
| .bias_get_combo = mtk_pinconf_bias_get_combo, | |
| .drive_set = mtk_pinconf_drive_set_rev1, | |
| .drive_get = mtk_pinconf_drive_get_rev1, | |
| .adv_pull_get = mtk_pinconf_adv_pull_get, | |
| .adv_pull_set = mtk_pinconf_adv_pull_set, | |
| }; | |
| static const struct mtk_pin_soc mt6735m_data = { | |
| .reg_cal = mt6735m_reg_cals, | |
| .pins = mtk_pins_mt6735m, | |
| .npins = ARRAY_SIZE(mtk_pins_mt6735m), | |
| .ngrps = ARRAY_SIZE(mtk_pins_mt6735m), | |
| .eint_hw = &mt6735_eint_hw, | |
| .gpio_m = 0, | |
| .ies_present = true, | |
| .base_names = mt6735_pinctrl_register_base_names, | |
| .nbase_names = ARRAY_SIZE(mt6735_pinctrl_register_base_names), | |
| .pull_type = mt6735m_pull_type, | |
| .bias_set_combo = mtk_pinconf_bias_set_combo, | |
| .bias_get_combo = mtk_pinconf_bias_get_combo, | |
| .drive_set = mtk_pinconf_drive_set_rev1, | |
| .drive_get = mtk_pinconf_drive_get_rev1, | |
| .adv_pull_get = mtk_pinconf_adv_pull_get, | |
| .adv_pull_set = mtk_pinconf_adv_pull_set, | |
| }; | |
| static const struct of_device_id mt6735_pinctrl_match[] = { | |
| { .compatible = "mediatek,mt6735-pinctrl", .data = &mt6735_data }, | |
| { .compatible = "mediatek,mt6735m-pinctrl", .data = &mt6735m_data }, | |
| { /* sentinel */ } | |
| }; | |
| MODULE_DEVICE_TABLE(of, mt6735_pinctrl_match); | |
| static struct platform_driver mt6735_pinctrl_driver = { | |
| .probe = mtk_paris_pinctrl_probe, | |
| .driver = { | |
| .name = "mt6735-pinctrl", | |
| .of_match_table = mt6735_pinctrl_match, | |
| .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops), | |
| }, | |
| }; | |
| module_platform_driver(mt6735_pinctrl_driver); | |
| MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>"); | |
| MODULE_DESCRIPTION("MediaTek MT6735 pinctrl driver"); | |
| MODULE_LICENSE("GPL"); |