| // SPDX-License-Identifier: GPL-2.0-only | |
| // | |
| // The NAU83G60 Stereo Class-D Amplifier with DSP and I/V-sense driver. | |
| // | |
| // Copyright (C) 2026 Nuvoton Technology Corp. | |
| // Author: David Lin <ctlin0@nuvoton.com> | |
| // Seven Lee <wtli@nuvoton.com> | |
| // John Hsu <kchsu0@nuvoton.com> | |
| // Neo Chang <ylchang2@nuvoton.com> | |
| #ifndef __NAU8360_H__ | |
| #define __NAU8360_H__ | |
| #define NAU8360_R00_SOFTWARE_RST 0x00 | |
| #define NAU8360_R01_DSP_SOFTWARE_RST 0x01 | |
| #define NAU8360_R02_I2C_ADDR 0x02 | |
| #define NAU8360_R03_CLK_CTRL0 0x03 | |
| #define NAU8360_R04_CLK_CTRL1 0x04 | |
| #define NAU8360_R05_INTERRUPT_CTRL 0x05 | |
| #define NAU8360_R06_INT_CLR_STATUS 0x06 | |
| #define NAU8360_R07_GP_CTRL 0x07 | |
| #define NAU8360_R08_GP_CTRL0 0x08 | |
| #define NAU8360_R09_GP_CTRL1 0x09 | |
| #define NAU8360_R0A_GP_CTRL2 0x0a | |
| #define NAU8360_R0B_I2S_PCM_CTRL1 0x0b | |
| #define NAU8360_R0C_I2S_PCM_CTRL2 0x0c | |
| #define NAU8360_R0D_I2S_PCM_CTRL3 0x0d | |
| #define NAU8360_R0E_I2S_DATA_CTRL1 0x0e | |
| #define NAU8360_R0F_I2S_DATA_CTRL2 0x0f | |
| #define NAU8360_R10_I2S_DATA_CTRL3 0x10 | |
| #define NAU8360_R11_I2S_DATA_CTRL4 0x11 | |
| #define NAU8360_R12_PATH_CTRL 0x12 | |
| #define NAU8360_R16_NO_NAME 0x16 | |
| #define NAU8360_R17_I2S0_DATA_CTRL5 0x17 | |
| #define NAU8360_R1A_DSP_CORE_CTRL2 0x1a | |
| #define NAU8360_R21_VBAT_READOUT 0x21 | |
| #define NAU8360_R22_TEMP_READOUT 0x22 | |
| #define NAU8360_R2C_ALC_CTRL1 0x2c | |
| #define NAU8360_R2D_ALC_CTRL2 0x2d | |
| #define NAU8360_R2E_ALC_CTRL3 0x2e | |
| #define NAU8360_R31_UVLOP_CTRL1 0x31 | |
| #define NAU8360_R32_UVLOP_CTRL2 0x32 | |
| #define NAU8360_R33_UVLOP_CTRL3 0x33 | |
| #define NAU8360_R40_CLK_DET_CTRL 0x40 | |
| #define NAU8360_R41_CLK_CTL2 0x41 | |
| #define NAU8360_R46_I2C_DEVICE_ID 0x46 | |
| #define NAU8360_R5D_SINC_CFG 0x5d | |
| #define NAU8360_R5F_ANA_TRIM_CFG1 0x5f | |
| #define NAU8360_R60_RST 0x60 | |
| #define NAU8360_R67_ANALOG_CONTROL_0 0x67 | |
| #define NAU8360_R68_ANALOG_CONTROL_1 0x68 | |
| #define NAU8360_R69_ANALOG_CONTROL_3 0x69 | |
| #define NAU8360_R6A_SARADC_CFG0 0x6a | |
| #define NAU8360_R6B_SARADC_CFG1 0x6b | |
| #define NAU8360_R6C_IVSNS_CFG0 0x6c | |
| #define NAU8360_R6D_IVSNS_CFG1 0x6d | |
| #define NAU8360_R6E_DAC_CFG0 0x6e | |
| #define NAU8360_R71_CLK_DIV_CFG 0x71 | |
| #define NAU8360_R72_PLL_CFG0 0x72 | |
| #define NAU8360_R73_PLL_CFG1 0x73 | |
| #define NAU8360_R74_PLL_CFG2 0x74 | |
| #define NAU8360_R77_SOFT_SD 0x77 | |
| #define NAU8360_R78_PD_SW_DLDO 0x78 | |
| #define NAU8360_R79_EN_HIRC48M 0x79 | |
| #define NAU8360_R7A_DAC_TRIM_CFG2 0x7a | |
| #define NAU8360_R7B_IVSNS_TRIM_CFG 0x7b | |
| #define NAU8360_R7C_MISC_TRIM_CFG 0x7c | |
| #define NAU8360_R7E_CLK_GATED_EN 0x7e | |
| #define NAU8360_R86_HW3_CTL0 0x86 | |
| #define NAU8360_R88_ALC_CTRL6 0x88 | |
| #define NAU8360_R8A_HW3_VL_CTL7 0x8a | |
| #define NAU8360_R8B_HW3_VR_CTL8 0x8b | |
| #define NAU8360_R8C_HW3_CTL6 0x8c | |
| #define NAU8360_R8D_HW3_IL_CTL7 0x8d | |
| #define NAU8360_R8E_HW3_IR_CTL8 0x8e | |
| #define NAU8360_R8F_HW3_CTL9 0x8f | |
| #define NAU8360_R90_HW2_CTL0 0x90 | |
| #define NAU8360_R96_HW2_CTL6 0x96 | |
| #define NAU8360_R97_HW2_CTL7 0x97 | |
| #define NAU8360_R98_HW2_CTL8 0x98 | |
| #define NAU8360_R99_HW2_CTL9 0x99 | |
| #define NAU8360_R9A_HW1_CTL0 0x9a | |
| #define NAU8360_R9B_HW1_CTL1 0x9b | |
| #define NAU8360_R9C_HW1_CTL2 0x9c | |
| #define NAU8360_R9D_PEQ_CTL 0x9d | |
| #define NAU8360_RA0_LEFT_XODRC_CTRL 0xa0 | |
| #define NAU8360_RA2_RIGHT_XODRC_CTRL 0xa2 | |
| #define NAU8360_RA4_ANA_REG_0 0xa4 | |
| #define NAU8360_RA5_ANA_REG_1 0xa5 | |
| /* Left PEQ includes 15 band, 10 coeff per band, from start addr 0x100 */ | |
| #define NAU8360_R100_LEFT_BIQ0_COE 0x100 | |
| #define NAU8360_R10C_LEFT_BIQ1_COE 0x10c | |
| #define NAU8360_R118_LEFT_BIQ2_COE 0x118 | |
| #define NAU8360_R124_LEFT_BIQ3_COE 0x124 | |
| #define NAU8360_R130_LEFT_BIQ4_COE 0x130 | |
| #define NAU8360_R13C_LEFT_BIQ5_COE 0x13c | |
| #define NAU8360_R148_LEFT_BIQ6_COE 0x148 | |
| #define NAU8360_R154_LEFT_BIQ7_COE 0x154 | |
| #define NAU8360_R160_LEFT_BIQ8_COE 0x160 | |
| #define NAU8360_R16C_LEFT_BIQ9_COE 0x16c | |
| #define NAU8360_R178_LEFT_BIQ10_COE 0x178 | |
| #define NAU8360_R184_LEFT_BIQ11_COE 0x184 | |
| #define NAU8360_R190_LEFT_BIQ12_COE 0x190 | |
| #define NAU8360_R19C_LEFT_BIQ13_COE 0x19c | |
| #define NAU8360_R1A8_LEFT_BIQ14_COE 0x1a8 | |
| /* Right PEQ includes 15 band, 10 coeff per band, from start addr 0x200 */ | |
| #define NAU8360_R200_RIGHT_BIQ0_COE 0x200 | |
| #define NAU8360_R20C_RIGHT_BIQ1_COE 0x20c | |
| #define NAU8360_R218_RIGHT_BIQ2_COE 0x218 | |
| #define NAU8360_R224_RIGHT_BIQ3_COE 0x224 | |
| #define NAU8360_R230_RIGHT_BIQ4_COE 0x230 | |
| #define NAU8360_R23C_RIGHT_BIQ5_COE 0x23c | |
| #define NAU8360_R248_RIGHT_BIQ6_COE 0x248 | |
| #define NAU8360_R254_RIGHT_BIQ7_COE 0x254 | |
| #define NAU8360_R260_RIGHT_BIQ8_COE 0x260 | |
| #define NAU8360_R26C_RIGHT_BIQ9_COE 0x26c | |
| #define NAU8360_R278_RIGHT_BIQ10_COE 0x278 | |
| #define NAU8360_R284_RIGHT_BIQ11_COE 0x284 | |
| #define NAU8360_R290_RIGHT_BIQ12_COE 0x290 | |
| #define NAU8360_R29C_RIGHT_BIQ13_COE 0x29c | |
| #define NAU8360_R2A8_RIGHT_BIQ14_COE 0x2a8 | |
| #define NAU8360_RF000_DSP_COMM 0xf000 | |
| #define NAU8360_RF002_DSP_COMM 0xf002 | |
| #define NAU8360_REG_MAX NAU8360_RF002_DSP_COMM | |
| /* 16-bit control register address, and 16-bits control register data */ | |
| #define NAU8360_REG_ADDR_LEN 16 | |
| #define NAU8360_REG_DATA_LEN 16 | |
| /* NAU8360_R03_CLK_CTRL0 (0x03) */ | |
| #define NAU8360_MCLK_DIV_SFT 10 | |
| #define NAU8360_MCLK_DIV_MAX 0x3f | |
| #define NAU8360_MCLK_DIV_MASK (0x3f << NAU8360_MCLK_DIV_SFT) | |
| #define NAU8360_DSP_CLK_DIV_SFT 7 | |
| #define NAU8360_DSP_CLK_DIV_MAX 0x7 | |
| #define NAU8360_DSP_CLK_DIV_MASK (0x7 << NAU8360_DSP_CLK_DIV_SFT) | |
| #define NAU8360_DSP_CLK_SEL_SFT 5 | |
| #define NAU8360_DSP_CLK_SEL_MASK (0x3 << NAU8360_DSP_CLK_SEL_SFT) | |
| #define NAU8360_DSP_CLK_SEL_PLL (0x2 << NAU8360_DSP_CLK_SEL_SFT) | |
| #define NAU8360_DSP_CLK_SEL_HIRC48M (0x1 << NAU8360_DSP_CLK_SEL_SFT) | |
| #define NAU8360_DSP_CLK_SEL_MCLK (0x0 << NAU8360_DSP_CLK_SEL_SFT) | |
| /* NAU8360_R04_CLK_CTRL1 (0x4) */ | |
| #define NAU8360_MCLK_SEL_SFT 14 | |
| #define NAU8360_MCLK_SEL_MASK (0x3 << NAU8360_MCLK_SEL_SFT) | |
| #define NAU8360_MCLK_SEL_PLL (0x2 << NAU8360_MCLK_SEL_SFT) | |
| #define NAU8360_MCLK_SEL_HIRC48M (0x1 << NAU8360_MCLK_SEL_SFT) | |
| #define NAU8360_MCLK_SEL_MCLK (0x0 << NAU8360_MCLK_SEL_SFT) | |
| #define NAU8360_HW_CLK_SEL_SFT 10 | |
| #define NAU8360_HW_CLK_SEL_MASK (0x3 << NAU8360_HW_CLK_SEL_SFT) | |
| #define NAU8360_HW_CLK_SEL_PLL (0x2 << NAU8360_HW_CLK_SEL_SFT) | |
| #define NAU8360_HW_CLK_SEL_HIRC48M (0x1 << NAU8360_HW_CLK_SEL_SFT) | |
| #define NAU8360_HW_CLK_SEL_MCLK (0x0 << NAU8360_HW_CLK_SEL_SFT) | |
| #define NAU8360_HW_CLK_DIV_SFT 7 | |
| #define NAU8360_HW_CLK_DIV_MAX NAU8360_DSP_CLK_DIV_MAX | |
| #define NAU8360_HW_CLK_DIV_MASK (0x7 << NAU8360_HW_CLK_DIV_SFT) | |
| /* NAU8360_R07_GP_CTRL (0x7) */ | |
| #define NAU8360_GPIO1_IEOE_SFT 14 | |
| #define NAU8360_GPIO1_IEOE_MASK (0x3 << NAU8360_GPIO1_IEOE_SFT) | |
| #define NAU8360_GPIO2_IEOE_SFT 12 | |
| #define NAU8360_GPIO2_IEOE_MASK (0x3 << NAU8360_GPIO2_IEOE_SFT) | |
| #define NAU8360_GPIO3_IEOE_SFT 10 | |
| #define NAU8360_GPIO3_IEOE_MASK (0x3 << NAU8360_GPIO3_IEOE_SFT) | |
| #define NAU8360_GPIO4_IEOE_SFT 8 | |
| #define NAU8360_GPIO4_IEOE_MASK (0x3 << NAU8360_GPIO4_IEOE_SFT) | |
| #define NAU8360_GPIO1_IN_STAT_SFT 7 | |
| #define NAU8360_GPIO1_IN_STAT_MASK (0x1 << NAU8360_GPIO1_IN_STAT_SFT) | |
| #define NAU8360_GPIO2_IN_STAT_SFT 6 | |
| #define NAU8360_GPIO2_IN_STAT_MASK (0x1 << NAU8360_GPIO2_IN_STAT_SFT) | |
| #define NAU8360_GPIO3_IN_STAT_SFT 5 | |
| #define NAU8360_GPIO3_IN_STAT_MASK (0x1 << NAU8360_GPIO3_IN_STAT_SFT) | |
| #define NAU8360_GPIO4_IN_STAT_SFT 4 | |
| #define NAU8360_GPIO4_IN_STAT_MASK (0x1 << NAU8360_GPIO4_IN_STAT_SFT) | |
| /* NAU8360_R08_GP_CTRL0 (0x8) */ | |
| #define NAU8360_GPIO2_MUX_SFT 14 | |
| #define NAU8360_GPIO2_MUX_MASK (0x3 << NAU8360_GPIO2_MUX_SFT) | |
| #define NAU8360_GPIO2_SR_SFT 13 | |
| #define NAU8360_GPIO2_SR_MASK (0x1 << NAU8360_GPIO2_SR_SFT) | |
| #define NAU8360_GPIO2_CDS_SFT 11 | |
| #define NAU8360_GPIO2_CDS_MASK (0x3 << NAU8360_GPIO2_CDS_SFT) | |
| #define NAU8360_GPIO2_PS_SFT 10 | |
| #define NAU8360_GPIO2_PS_MASK (0x1 << NAU8360_GPIO2_PS_SFT) | |
| #define NAU8360_GPIO2_PE_SFT 9 | |
| #define NAU8360_GPIO2_PE_EN (0x1 << NAU8360_GPIO2_PE_SFT) | |
| #define NAU8360_GPIO1_MUX_SFT 6 | |
| #define NAU8360_GPIO1_MUX_MASK (0x3 << NAU8360_GPIO1_MUX_SFT) | |
| #define NAU8360_GPIO1_SR_SFT 5 | |
| #define NAU8360_GPIO1_SR_MASK (0x1 << NAU8360_GPIO1_SR_SFT) | |
| #define NAU8360_GPIO1_CDS_SFT 3 | |
| #define NAU8360_GPIO1_CDS_MASK (0x3 << NAU8360_GPIO1_CDS_SFT) | |
| #define NAU8360_GPIO1_PS_SFT 2 | |
| #define NAU8360_GPIO1_PS_MASK (0x1 << NAU8360_GPIO1_PS_SFT) | |
| #define NAU8360_GPIO1_PE_SFT 1 | |
| #define NAU8360_GPIO1_PE_EN (0x1 << NAU8360_GPIO1_PE_SFT) | |
| /* NAU8360_R09_GP_CTRL1 (0x9) */ | |
| #define NAU8360_GPIO4_MUX_SFT 14 | |
| #define NAU8360_GPIO4_MUX_MASK (0x3 << NAU8360_GPIO4_MUX_SFT) | |
| #define NAU8360_GPIO4_SR_SFT 13 | |
| #define NAU8360_GPIO4_SR_MASK (0x1 << NAU8360_GPIO4_SR_SFT) | |
| #define NAU8360_GPIO4_CDS_SFT 11 | |
| #define NAU8360_GPIO4_CDS_MASK (0x3 << NAU8360_GPIO4_CDS_SFT) | |
| #define NAU8360_GPIO4_PS_SFT 10 | |
| #define NAU8360_GPIO4_PS_MASK (0x1 << NAU8360_GPIO4_PS_SFT) | |
| #define NAU8360_GPIO4_PE_SFT 9 | |
| #define NAU8360_GPIO4_PE_EN (0x1 << NAU8360_GPIO4_PE_SFT) | |
| #define NAU8360_GPIO3_MUX_SFT 6 | |
| #define NAU8360_GPIO3_MUX_MASK (0x3 << NAU8360_GPIO3_MUX_SFT) | |
| #define NAU8360_GPIO3_SR_SFT 5 | |
| #define NAU8360_GPIO3_SR_MASK (0x1 << NAU8360_GPIO3_SR_SFT) | |
| #define NAU8360_GPIO3_CDS_SFT 3 | |
| #define NAU8360_GPIO3_CDS_MASK (0x3 << NAU8360_GPIO3_CDS_SFT) | |
| #define NAU8360_GPIO3_PS_SFT 2 | |
| #define NAU8360_GPIO3_PS_MASK (0x1 << NAU8360_GPIO3_PS_SFT) | |
| #define NAU8360_GPIO3_PE_SFT 1 | |
| #define NAU8360_GPIO3_PE_EN (0x1 << NAU8360_GPIO3_PE_SFT) | |
| /* NAU8360_R0B_I2S_PCM_CTRL1 (0x0b) */ | |
| #define NAU8360_EN_TDM_TX_SFT 15 | |
| #define NAU8360_EN_TDM_TX (0x1 << NAU8360_EN_TDM_TX_SFT) | |
| #define NAU8360_EN_TDM_RX_SFT 14 | |
| #define NAU8360_EN_TDM_RX (0x1 << NAU8360_EN_TDM_RX_SFT) | |
| #define NAU8360_FRAME_START_SFT 8 | |
| #define NAU8360_FRAME_START_MASK (0x1 << NAU8360_FRAME_START_SFT) | |
| #define NAU8360_FRAME_START_H2L (0x1 << NAU8360_FRAME_START_SFT) | |
| #define NAU8360_FRAME_START_L2H (0x0 << NAU8360_FRAME_START_SFT) | |
| #define NAU8360_RX_JUSTIFY_SFT 7 | |
| #define NAU8360_RX_JUSTIFY_MASK (0x1 << NAU8360_RX_JUSTIFY_SFT) | |
| #define NAU8360_RX_RIGHT_JUSTIFY (0x1 << NAU8360_RX_JUSTIFY_SFT) | |
| #define NAU8360_RX_LEFT_JUSTIFY (0x0 << NAU8360_RX_JUSTIFY_SFT) | |
| #define NAU8360_RX_OFFSET_SFT 2 | |
| #define NAU8360_RX_OFFSET_MASK (0x1f << NAU8360_RX_OFFSET_SFT) | |
| #define NAU8360_RX_OFFSET_I2S (0x1 << NAU8360_RX_OFFSET_SFT) | |
| #define NAU8360_RX_OFFSET_LEFT (0x0 << NAU8360_RX_OFFSET_SFT) | |
| #define NAU8360_RX_OFFSET_RIGHT (0x0 << NAU8360_RX_OFFSET_SFT) | |
| #define NAU8360_RX_OFFSET_PCM_A (0x1 << NAU8360_RX_OFFSET_SFT) | |
| #define NAU8360_RX_OFFSET_PCM_B (0x0 << NAU8360_RX_OFFSET_SFT) | |
| /* NAU8360_R0C_I2S_PCM_CTRL2 (0xc) */ | |
| #define NAU8360_TDM_DLEN_SFT 10 | |
| #define NAU8360_TDM_DLEN_MASK (0x3 << NAU8360_TDM_DLEN_SFT) | |
| #define NAU8360_TDM_DLEN_32 (0x3 << NAU8360_TDM_DLEN_SFT) | |
| #define NAU8360_TDM_DLEN_24 (0x2 << NAU8360_TDM_DLEN_SFT) | |
| #define NAU8360_TDM_DLEN_20 (0x1 << NAU8360_TDM_DLEN_SFT) | |
| #define NAU8360_TDM_DLEN_16 (0x0 << NAU8360_TDM_DLEN_SFT) | |
| #define NAU8360_TDM_CLEN_SFT 8 | |
| #define NAU8360_TDM_CLEN_MASK (0x3 << NAU8360_TDM_CLEN_SFT) | |
| #define NAU8360_TDM_CLEN_32 (0x2 << NAU8360_TDM_CLEN_SFT) | |
| #define NAU8360_TDM_CLEN_24 (0x1 << NAU8360_TDM_CLEN_SFT) | |
| #define NAU8360_TDM_CLEN_16 (0x0 << NAU8360_TDM_CLEN_SFT) | |
| #define NAU8360_RX_DACR_SFT 4 | |
| #define NAU8360_RX_DACR_MASK (0xf << NAU8360_RX_DACR_SFT) | |
| #define NAU8360_RX_DACL_MASK 0xf | |
| /* NAU8360_R0D_I2S_PCM_CTRL3 (0x0d) */ | |
| #define NAU8360_TX_FILL_SFT 12 | |
| #define NAU8360_TX_FILL_MASK (0x1 << NAU8360_TX_FILL_SFT) | |
| #define NAU8360_TX_FILL_HIGHZ (0x1 << NAU8360_TX_FILL_SFT) | |
| #define NAU8360_TX_FILL_ZERO (0x0 << NAU8360_TX_FILL_SFT) | |
| #define NAU8360_TX_OFFSET_SFT 9 | |
| #define NAU8360_TX_OFFSET_MASK (0x7 << NAU8360_TX_OFFSET_SFT) | |
| #define NAU8360_TX_OFFSET_I2S (0x1 << NAU8360_TX_OFFSET_SFT) | |
| #define NAU8360_TX_OFFSET_LEFT (0x0 << NAU8360_TX_OFFSET_SFT) | |
| #define NAU8360_TX_OFFSET_RIGHT (0x0 << NAU8360_TX_OFFSET_SFT) | |
| #define NAU8360_TX_OFFSET_PCM_A (0x1 << NAU8360_TX_OFFSET_SFT) | |
| #define NAU8360_TX_OFFSET_PCM_B (0x0 << NAU8360_TX_OFFSET_SFT) | |
| #define NAU8360_VSNS_L_SLEN_SFT 7 | |
| #define NAU8360_VSNS_L_SLEN_MASK (0x1 << NAU8360_VSNS_L_SLEN_SFT) | |
| #define NAU8360_VSNS_L_SLEN_16 (0x1 << NAU8360_VSNS_L_SLEN_SFT) | |
| #define NAU8360_VSNS_L_SLEN_8 (0x0 << NAU8360_VSNS_L_SLEN_SFT) | |
| #define NAU8360_VSNS_L_TX_EN_SFT 6 | |
| #define NAU8360_VSNS_L_TX_EN (0x1 << NAU8360_VSNS_L_TX_EN_SFT) | |
| #define NAU8360_VSNS_L_SLOT_MASK 0x3f | |
| /* NAU8360_R0E_I2S_DATA_CTRL1 (0x0e) */ | |
| #define NAU8360_ISNS_L_SLEN_SFT 15 | |
| #define NAU8360_ISNS_L_SLEN_MASK (0x1 << NAU8360_ISNS_L_SLEN_SFT) | |
| #define NAU8360_ISNS_L_SLEN_16 (0x1 << NAU8360_ISNS_L_SLEN_SFT) | |
| #define NAU8360_ISNS_L_SLEN_8 (0x0 << NAU8360_ISNS_L_SLEN_SFT) | |
| #define NAU8360_ISNS_L_TX_EN_SFT 14 | |
| #define NAU8360_ISNS_L_TX_EN (0x1 << NAU8360_ISNS_L_TX_EN_SFT) | |
| #define NAU8360_ISNS_L_SLOT_SFT 8 | |
| #define NAU8360_ISNS_L_SLOT_MASK (0x3f << NAU8360_ISNS_L_SLOT_SFT) | |
| #define NAU8360_PDM_L_SLEN_SFT 7 | |
| #define NAU8360_PDM_L_SLEN_MASK (0x1 << NAU8360_PDM_L_SLEN_SFT) | |
| #define NAU8360_PDM_L_SLEN_24 (0x1 << NAU8360_PDM_L_SLEN_SFT) | |
| #define NAU8360_PDM_L_SLEN_16 (0x0 << NAU8360_PDM_L_SLEN_SFT) | |
| #define NAU8360_PDM_L_TX_EN_SFT 6 | |
| #define NAU8360_PDM_L_TX_EN (0x1 << NAU8360_PDM_L_TX_EN_SFT) | |
| #define NAU8360_PDM_L_SLOT_MASK 0x3f | |
| /* NAU8360_R0F_I2S_DATA_CTRL2 (0xf) */ | |
| #define NAU8360_VBAT_TX_EN_SFT 14 | |
| #define NAU8360_VBAT_TX_EN (0x1 << NAU8360_VBAT_TX_EN_SFT) | |
| #define NAU8360_VBAT_SLOT_SFT 8 | |
| #define NAU8360_VBAT_SLOT_MASK (0x3f << NAU8360_VBAT_SLOT_SFT) | |
| #define NAU8360_PDM_R_SLEN_SFT 7 | |
| #define NAU8360_PDM_R_SLEN_MASK (0x1 << NAU8360_PDM_R_SLEN_SFT) | |
| #define NAU8360_PDM_R_SLEN_24 (0x1 << NAU8360_PDM_R_SLEN_SFT) | |
| #define NAU8360_PDM_R_SLEN_16 (0x0 << NAU8360_PDM_R_SLEN_SFT) | |
| #define NAU8360_PDM_R_TX_EN_SFT 6 | |
| #define NAU8360_PDM_R_TX_EN (0x1 << NAU8360_PDM_R_TX_EN_SFT) | |
| #define NAU8360_PDM_R_SLOT_MASK 0x3f | |
| /* NAU8360_R10_I2S_DATA_CTRL3 (0x10) */ | |
| #define NAU8360_RX_ANC_R_SFT 12 | |
| #define NAU8360_RX_ANC_R_MASK (0xf << NAU8360_RX_ANC_R_SFT) | |
| #define NAU8360_RX_ANC_L_SFT 8 | |
| #define NAU8360_RX_ANC_L_MASK (0xf << NAU8360_RX_ANC_L_SFT) | |
| #define NAU8360_TDM_LOOPBACK_SFT 7 | |
| #define NAU8360_TDM_LOOPBACK (0x1 << NAU8360_TDM_LOOPBACK_SFT) | |
| #define NAU8360_TEMP_TX_EN_SFT 6 | |
| #define NAU8360_TEMP_TX_EN (0x1 << NAU8360_TEMP_TX_EN_SFT) | |
| #define NAU8360_TEMP_SLOT_MASK 0x3f | |
| /* NAU8360_R11_I2S_DATA_CTRL4 (0x11) */ | |
| #define NAU8360_VSNS_R_SLEN_SFT 15 | |
| #define NAU8360_VSNS_R_SLEN_MASK (0x1 << NAU8360_VSNS_R_SLEN_SFT) | |
| #define NAU8360_VSNS_R_SLEN_16 (0x1 << NAU8360_VSNS_R_SLEN_SFT) | |
| #define NAU8360_VSNS_R_SLEN_8 (0x0 << NAU8360_VSNS_R_SLEN_SFT) | |
| #define NAU8360_VSNS_R_TX_EN_SFT 14 | |
| #define NAU8360_VSNS_R_TX_EN (0x1 << NAU8360_VSNS_R_TX_EN_SFT) | |
| #define NAU8360_VSNS_R_SLOT_SFT 8 | |
| #define NAU8360_VSNS_R_SLOT_MASK (0x3f << NAU8360_VSNS_R_SLOT_SFT) | |
| #define NAU8360_ISNS_R_SLEN_SFT 7 | |
| #define NAU8360_ISNS_R_SLEN_MASK (0x1 << NAU8360_ISNS_R_SLEN_SFT) | |
| #define NAU8360_ISNS_R_SLEN_16 (0x1 << NAU8360_ISNS_R_SLEN_SFT) | |
| #define NAU8360_ISNS_R_SLEN_8 (0x0 << NAU8360_ISNS_R_SLEN_SFT) | |
| #define NAU8360_ISNS_R_TX_EN_SFT 6 | |
| #define NAU8360_ISNS_R_TX_EN (0x1 << NAU8360_ISNS_R_TX_EN_SFT) | |
| #define NAU8360_ISNS_R_SLOT_MASK 0x3f | |
| /* NAU8360_R12_PATH_CTRL (0x12) */ | |
| #define NAU8360_SEL_HW1_SFT 9 | |
| #define NAU8360_SEL_HW1_MASK (0x1 << NAU8360_SEL_HW1_SFT) | |
| #define NAU8360_SEL_HW1_OUT (0x1 << NAU8360_SEL_HW1_SFT) | |
| #define NAU8360_SEL_HW1_BYP (0x0 << NAU8360_SEL_HW1_SFT) | |
| #define NAU8360_AUD_SEL_SFT 7 | |
| #define NAU8360_AUD_SEL_MASK (0x1 << NAU8360_AUD_SEL_SFT) | |
| #define NAU8360_AUD_SEL_SINCOUT (0x1 << NAU8360_AUD_SEL_SFT) | |
| #define NAU8360_AUD_SEL_SINCBYP (0x0 << NAU8360_AUD_SEL_SFT) | |
| #define NAU8360_SEL_HW2_SFT 6 | |
| #define NAU8360_SEL_HW2_MASK (0x1 << NAU8360_SEL_HW2_SFT) | |
| #define NAU8360_SEL_HW2_OUT (0x1 << NAU8360_SEL_HW2_SFT) | |
| #define NAU8360_SEL_HW2_BYP (0x0 << NAU8360_SEL_HW2_SFT) | |
| #define NAU8360_DAC_SEL_SFT 5 | |
| #define NAU8360_DAC_SEL_MASK (0x1 << NAU8360_DAC_SEL_SFT) | |
| #define NAU8360_DAC_SEL_DSP (0x1 << NAU8360_DAC_SEL_SFT) | |
| #define NAU8360_DAC_SEL_BYP (0x0 << NAU8360_DAC_SEL_SFT) | |
| #define NAU8360_SEL_HW3_SFT 4 | |
| #define NAU8360_SEL_HW3_MASK (0x1 << NAU8360_SEL_HW3_SFT) | |
| #define NAU8360_SEL_HW3_OUT (0x1 << NAU8360_SEL_HW3_SFT) | |
| #define NAU8360_SEL_HW3_BYP (0x0 << NAU8360_SEL_HW3_SFT) | |
| /* NAU8360_R17_I2S0_DATA_CTRL5 (0x17)*/ | |
| #define NAU8360_AEC_L_SLEN_SFT 15 | |
| #define NAU8360_AEC_L_SLEN_MASK (0x1 << NAU8360_AEC_L_SLEN_SFT) | |
| #define NAU8360_AEC_L_SLEN_32 (0x1 << NAU8360_AEC_L_SLEN_SFT) | |
| #define NAU8360_AEC_L_SLEN_16 (0x0 << NAU8360_AEC_L_SLEN_SFT) | |
| #define NAU8360_AEC_L_EN_SFT 14 | |
| #define NAU8360_AEC_L_EN (0x1 << NAU8360_AEC_L_EN_SFT) | |
| #define NAU8360_AEC_L_SLOT_SFT 8 | |
| #define NAU8360_AEC_L_SLOT_MASK (0x3f << NAU8360_AEC_L_SLOT_SFT) | |
| #define NAU8360_AEC_R_SLEN_SFT 7 | |
| #define NAU8360_AEC_R_SLEN_MASK (0x1 << NAU8360_AEC_R_SLEN_SFT) | |
| #define NAU8360_AEC_R_SLEN_32 (0x1 << NAU8360_AEC_R_SLEN_SFT) | |
| #define NAU8360_AEC_R_SLEN_16 (0x0 << NAU8360_AEC_R_SLEN_SFT) | |
| #define NAU8360_AEC_R_EN_SFT 6 | |
| #define NAU8360_AEC_R_EN (0x1 << NAU8360_AEC_R_EN_SFT) | |
| #define NAU8360_AEC_R_SLOT_MASK 0x3f | |
| /* NAU8360_R1A_DSP_CORE_CTRL2 (0x1a) */ | |
| #define NAU8360_DSP_RUNSTALL_SFT 4 | |
| #define NAU8360_DSP_RUNSTALL (0x1 << NAU8360_DSP_RUNSTALL_SFT) | |
| /* NAU8360_R21_VBAT_READOUT (0x21) */ | |
| #define NAU8360_VBAT_BASE 1108 | |
| #define NAU8360_VBAT_STEP 12353 | |
| /* NAU8360_R40_CLK_DET_CTRL (0x40) */ | |
| #define NAU8360_APWRUPEN_SFT 15 | |
| #define NAU8360_APWRUPEN (0x1 << NAU8360_APWRUPEN_SFT) | |
| #define NAU8360_CLKPWRUPEN_SFT 14 | |
| #define NAU8360_CLKPWRUPEN (0x1 << NAU8360_CLKPWRUPEN_SFT) | |
| #define NAU8360_SRATE_SFT 10 | |
| #define NAU8360_SRATE_MASK (0x7 << NAU8360_SRATE_SFT) | |
| #define NAU8360_SRATE_192000 (0x4 << NAU8360_SRATE_SFT) | |
| #define NAU8360_SRATE_96000 (0x3 << NAU8360_SRATE_SFT) | |
| #define NAU8360_SRATE_48000 (0x2 << NAU8360_SRATE_SFT) | |
| #define NAU8360_SRATE_32000 (0x1 << NAU8360_SRATE_SFT) | |
| #define NAU8360_SRATE_16000 (0x0 << NAU8360_SRATE_SFT) | |
| #define NAU8360_MCLK_RATE_SFT 7 | |
| #define NAU8360_MCLK_RATE_MASK (0x7 << NAU8360_MCLK_RATE_SFT) | |
| #define NAU8360_MCLK_RATE_24576 (0x4 << NAU8360_MCLK_RATE_SFT) | |
| #define NAU8360_MCLK_RATE_24000 (0x3 << NAU8360_MCLK_RATE_SFT) | |
| #define NAU8360_MCLK_RATE_19200 (0x2 << NAU8360_MCLK_RATE_SFT) | |
| #define NAU8360_MCLK_RATE_12288 (0x1 << NAU8360_MCLK_RATE_SFT) | |
| #define NAU8360_MCLK_RATE_12000 (0x0 << NAU8360_MCLK_RATE_SFT) | |
| #define NAU8360_FS_MCLK_DET_SFT 6 | |
| #define NAU8360_FS_MCLK_DET (0x1 << NAU8360_FS_MCLK_DET_SFT) | |
| #define NAU8360_FS_BCLK_DET_SFT 5 | |
| #define NAU8360_FS_BCLK_DET (0x1 << NAU8360_FS_BCLK_DET_SFT) | |
| /* NAU8360_R41_CLK_CTL2 (0x41) */ | |
| #define NAU8360_NOISE_FILTER_THD_SFT 12 | |
| #define NAU8360_NOISE_FILTER_THDT_MASK (0xf << NAU8360_NOISE_FILTER_THD_SFT) | |
| #define NAU8360_SEL_BLOCK_SIZE_SFT 6 | |
| #define NAU8360_SEL_BLOCK_SIZE_MASK (0x7 << NAU8360_SEL_BLOCK_SIZE_SFT) | |
| #define NAU8360_EN_ABCLKDET_SFT 3 | |
| #define NAU8360_EN_ABCLKDET (0x1 << NAU8360_EN_ABCLKDET_SFT) | |
| #define NAU8360_EN_DBCLKDET_SFT 2 | |
| #define NAU8360_EN_DBCLKDET (0x1 << NAU8360_EN_DBCLKDET_SFT) | |
| #define NAU8360_EN_AMCLKDET_SFT 1 | |
| #define NAU8360_EN_AMCLKDET (0x1 << NAU8360_EN_AMCLKDET_SFT) | |
| #define NAU8360_EN_DMCLKDET 0x1 | |
| /* NAU8360_R46_I2C_DEVICE_ID (0x46) */ | |
| #define NAU8360_REG_SI_REV_MASK 0xff | |
| #define NAU8360_REG_SI_REV_B 0xf2 | |
| #define NAU8360_REG_SI_REV_C 0xf5 | |
| /* NAU8360_R5D_SINC_CFG (0x5d) */ | |
| #define NAU8360_DAC_SINC_OSR_SFT 4 | |
| #define NAU8360_DAC_SINC_OSR_MASK (0x3 << NAU8360_DAC_SINC_OSR_SFT) | |
| #define NAU8360_DAC_SINC_OSR_250 (0x3 << NAU8360_DAC_SINC_OSR_SFT) | |
| #define NAU8360_DAC_SINC_OSR_200 (0x2 << NAU8360_DAC_SINC_OSR_SFT) | |
| #define NAU8360_DAC_SINC_OSR_128 (0x1 << NAU8360_DAC_SINC_OSR_SFT) | |
| #define NAU8360_DAC_SINC_OSR_0 (0x0 << NAU8360_DAC_SINC_OSR_SFT) | |
| #define NAU8360_IVSENSE_BS_OSR_MASK 0x3 | |
| #define NAU8360_IVSENSE_BS_OSR_25 0x3 | |
| #define NAU8360_IVSENSE_BS_OSR_64 0x2 | |
| #define NAU8360_IVSENSE_BS_OSR_32 0x1 | |
| #define NAU8360_IVSENSE_BS_OSR_16 0x0 | |
| /* NAU8360_R60_RST (0x60) */ | |
| #define NAU8360_PD_POR5_SFT 4 | |
| #define NAU8360_PD_POR5_PWD (0x1 << NAU8360_PD_POR5_SFT) | |
| #define NAU8360_EFUSE_CTRL_SFT 3 | |
| #define NAU8360_EFUSE_CTRL_EN (0x1 << NAU8360_EFUSE_CTRL_SFT) | |
| /* NAU8360_R67_ANALOG_CONTROL_0 (0x67) */ | |
| #define NAU8360_SCP_CLEAR_MODE_SFT 15 | |
| #define NAU8360_SCP_CLEAR_MODE_MASK (0x1 << NAU8360_SCP_CLEAR_MODE_SFT) | |
| #define NAU8360_SCP_CLEAR_MODE_AUTO (0x1 << NAU8360_SCP_CLEAR_MODE_SFT) | |
| #define NAU8360_SCP_CLEAR_MODE_MANU (0x0 << NAU8360_SCP_CLEAR_MODE_SFT) | |
| #define NAU8360_SCP_CLEAR_SFT 14 | |
| #define NAU8360_SCP_CLEAR (0x1 << NAU8360_SCP_CLEAR_SFT) | |
| #define NAU8360_HV_EN_SFT 13 | |
| #define NAU8360_HV_EN (0x1 << NAU8360_HV_EN_SFT) | |
| #define NAU8360_ANA_MUTE_SFT 8 | |
| #define NAU8360_ANA_MUTE (0x1 << NAU8360_ANA_MUTE_SFT) | |
| #define NAU8360_MOD_GAIN_SFT 5 | |
| #define NAU8360_MOD_GAIN_MASK (0x7 << NAU8360_MOD_GAIN_SFT) | |
| #define NAU8360_MOD_GAIN_20DB (0x7 << NAU8360_MOD_GAIN_SFT) | |
| #define NAU8360_MOD_GAIN_18DB (0x6 << NAU8360_MOD_GAIN_SFT) | |
| #define NAU8360_MOD_GAIN_16DB (0x5 << NAU8360_MOD_GAIN_SFT) | |
| #define NAU8360_MOD_GAIN_14DB (0x4 << NAU8360_MOD_GAIN_SFT) | |
| #define NAU8360_MOD_GAIN_12DB (0x3 << NAU8360_MOD_GAIN_SFT) | |
| #define NAU8360_MOD_GAIN_10DB (0x2 << NAU8360_MOD_GAIN_SFT) | |
| #define NAU8360_MOD_GAIN_8DB (0x1 << NAU8360_MOD_GAIN_SFT) | |
| #define NAU8360_MOD_GAIN_6DB (0x0 << NAU8360_MOD_GAIN_SFT) | |
| #define NAU8360_CM_COMP_SFT 4 | |
| #define NAU8360_CM_COMP_EN (0x1 << NAU8360_CM_COMP_SFT) | |
| #define NAU8360_V_PBTL_SFT 3 | |
| #define NAU8360_V_PBTL_EN (0x1 << NAU8360_V_PBTL_SFT) | |
| /* NAU8360_R68_ANALOG_CONTROL_1 (0x68) */ | |
| #define NAU8360_TRIMSCR_SFT 6 | |
| #define NAU8360_TRIMSCR_MASK (0x3 << NAU8360_TRIMSCR_SFT) | |
| #define NAU8360_TRIMSCR_HIGH (0x3 << NAU8360_TRIMSCR_SFT) | |
| #define NAU8360_TRIMSCR_MHIGH (0x2 << NAU8360_TRIMSCR_SFT) | |
| #define NAU8360_TRIMSCR_MLOW (0x1 << NAU8360_TRIMSCR_SFT) | |
| #define NAU8360_TRIMSCR_LOW (0x0 << NAU8360_TRIMSCR_SFT) | |
| #define NAU8360_DTX_SFT 5 | |
| #define NAU8360_DTX_EN (0x1 << NAU8360_DTX_SFT) | |
| #define NAU8360_DRVCTL_SEGL_SFT 4 | |
| #define NAU8360_DRVCTL_SEGL_FULL (0x1 << NAU8360_DRVCTL_SEGL_SFT) | |
| #define NAU8360_DRVCTL_SEGR_SFT 2 | |
| #define NAU8360_DRVCTL_SEGR_FULL (0x1 << NAU8360_DRVCTL_SEGR_SFT) | |
| #define NAU8360_SCP_TEST_SFT 1 | |
| #define NAU8360_SCP_TEST (0x1 << NAU8360_SCP_TEST_SFT) | |
| #define NAU8360_SEG_AUTO_CTRL_EN 0x1 | |
| /* NAU8360_R69_ANALOG_CONTROL_3 (0x69) */ | |
| #define NAU8360_ANA_STATUS_OTP_SFT 8 | |
| #define NAU8360_ANA_STATUS_OTP_MASK (0x1 << NAU8360_ANA_STATUS_OTP_SFT) | |
| #define NAU8360_ANA_STATUS_OVLO_SFT 7 | |
| #define NAU8360_ANA_STATUS_OVLO_MASK (0x1 << NAU8360_ANA_STATUS_OVLO_SFT) | |
| #define NAU8360_ANA_STATUS_UVLO_SFT 6 | |
| #define NAU8360_ANA_STATUS_UVLO_MASK (0x1 << NAU8360_ANA_STATUS_UVLO_SFT) | |
| #define NAU8360_ANA_STATUS_SCP_SFT 4 | |
| #define NAU8360_ANA_STATUS_SCP_MASK (0x1 << NAU8360_ANA_STATUS_SCP_SFT) | |
| #define NAU8360_ANA_STATUS_EN_V2I_SFT 3 | |
| #define NAU8360_ANA_STATUS_EN_V2I_MASK (0x1 << NAU8360_ANA_STATUS_EN_V2I_SFT) | |
| #define NAU8360_ANA_STATUS_FAULT_SFT 2 | |
| #define NAU8360_ANA_STATUS_FAULT_MASK (0x1 << NAU8360_ANA_STATUS_FAULT_SFT) | |
| #define NAU8360_ANA_STATUS_DC_DET_SFT 1 | |
| #define NAU8360_ANA_STATUS_DC_DET_MASK (0x1 << NAU8360_ANA_STATUS_DC_DET_SFT) | |
| #define NAU8360_ANA_STATUS_EN_ALL_MASK 0x1 | |
| /* NAU8360_R6A_SARADC_CFG0 (0x6a) */ | |
| #define NAU8360_SARADC_SFT 15 | |
| #define NAU8360_SARADC_EN (0x1 << NAU8360_SARADC_SFT) | |
| #define NAU8360_RESETB_SARADC_SFT 14 | |
| #define NAU8360_RESETB_SARADC_MASK (0x1 << NAU8360_RESETB_SARADC_SFT) | |
| #define NAU8360_RESETB_SARADC_NOR (0x1 << NAU8360_RESETB_SARADC_SFT) | |
| #define NAU8360_RESETB_SARADC_RST (0x0 << NAU8360_RESETB_SARADC_SFT) | |
| #define NAU8360_SARADC_CAL_SFT 13 | |
| #define NAU8360_SARADC_CAL (0x1 << NAU8360_SARADC_CAL_SFT) | |
| #define NAU8360_SARADC_DIV_SFT 12 | |
| #define NAU8360_SARADC_DIV (0x1 << NAU8360_SARADC_DIV_SFT) | |
| #define NAU8360_SARADC_CALSEL_SFT 9 | |
| #define NAU8360_SARADC_CALSEL_MASK (0x7 << NAU8360_SARADC_CALSEL_SFT) | |
| #define NAU8360_TRIMSMPL_SFT 3 | |
| #define NAU8360_TRIMSMPL_MASK (0x7 << NAU8360_TRIMSMPL_SFT) | |
| #define NAU8360_SAR_INPUT_CH_SEL_SFT 2 | |
| #define NAU8360_SAR_INPUT_CH_SEL_MASK (0x1 << NAU8360_SAR_INPUT_CH_SEL_SFT) | |
| #define NAU8360_VBAT_AVG_SFT 1 | |
| #define NAU8360_VBAT_AVG_EN (0x1 << NAU8360_VBAT_AVG_SFT) | |
| #define NAU8360_VTEMP_AVG_EN 0x1 | |
| /* NAU8360_R6B_SARADC_CFG1 (0x6b) */ | |
| #define NAU8360_VTEMP_SFT 15 | |
| #define NAU8360_VTEMP_EN (0x1 << NAU8360_VTEMP_SFT) | |
| #define NAU8360_VBATDIV_SFT 14 | |
| #define NAU8360_VBATDIV_EN (0x1 << NAU8360_VBATDIV_SFT) | |
| #define NAU8360_VREF_SFT 10 | |
| #define NAU8360_VREF_EN (0x1 << NAU8360_VREF_SFT) | |
| #define NAU8360_PRELOAD_VREF_SFT 9 | |
| #define NAU8360_PRELOAD_VREF_EN (0x1 << NAU8360_PRELOAD_VREF_SFT) | |
| #define NAU8360_VTEMP_AVG_N_SFT 2 | |
| #define NAU8360_VTEMP_AVG_N_MASK (0x3 << NAU8360_VTEMP_AVG_N_SFT) | |
| #define NAU8360_VTEMP_AVG_N_512 (0x3 << NAU8360_VTEMP_AVG_N_SFT) | |
| #define NAU8360_VTEMP_AVG_N_128 (0x2 << NAU8360_VTEMP_AVG_N_SFT) | |
| #define NAU8360_VTEMP_AVG_N_32 (0x1 << NAU8360_VTEMP_AVG_N_SFT) | |
| #define NAU8360_VTEMP_AVG_N_1 (0x0 << NAU8360_VTEMP_AVG_N_SFT) | |
| #define NAU8360_VBAT_AVG_N_MASK 0x3 | |
| #define NAU8360_VBAT_AVG_N_512 0x3 | |
| #define NAU8360_VBAT_AVG_N_128 0x2 | |
| #define NAU8360_VBAT_AVG_N_32 0x1 | |
| #define NAU8360_VBAT_AVG_N_1 0 | |
| /* NAU8360_R6C_IVSNS_CFG0 (0x6c) */ | |
| #define NAU8360_PD_VSNS_R_SFT 15 | |
| #define NAU8360_PD_VSNS_R_PMD (0x1 << NAU8360_PD_VSNS_R_SFT) | |
| #define NAU8360_PD_VSNS_L_SFT 14 | |
| #define NAU8360_PD_VSNS_L_PMD (0x1 << NAU8360_PD_VSNS_L_SFT) | |
| #define NAU8360_PD_ISNS_R_SFT 13 | |
| #define NAU8360_PD_ISNS_R_PMD (0x1 << NAU8360_PD_ISNS_R_SFT) | |
| #define NAU8360_PD_ISNS_L_SFT 12 | |
| #define NAU8360_PD_ISNS_L_PMD (0x1 << NAU8360_PD_ISNS_L_SFT) | |
| #define NAU8360_RESET_SC_VADC_R_SFT 11 | |
| #define NAU8360_RESET_SC_VADC_R_RST (0x1 << NAU8360_RESET_SC_VADC_R_SFT) | |
| #define NAU8360_RESET_SC_VADC_L_SFT 10 | |
| #define NAU8360_RESET_SC_VADC_L_RST (0x1 << NAU8360_RESET_SC_VADC_L_SFT) | |
| #define NAU8360_RESET_SC_IADC_R_SFT 9 | |
| #define NAU8360_RESET_SC_IADC_R_RST (0x1 << NAU8360_RESET_SC_IADC_R_SFT) | |
| #define NAU8360_RESET_SC_IADC_L_SFT 8 | |
| #define NAU8360_RESET_SC_IADC_L_RST (0x1 << NAU8360_RESET_SC_IADC_L_SFT) | |
| #define NAU8360_PBTL_ISENE_LR_SFT 7 | |
| #define NAU8360_PBTL_ISENE_LR_MASK (0x1 << NAU8360_PBTL_ISENE_LR_SFT) | |
| #define NAU8360_PBTL_ISENE_LR_ILR (0x1 << NAU8360_PBTL_ISENE_LR_SFT) | |
| #define NAU8360_PBTL_ISENE_LR_I2R (0x0 << NAU8360_PBTL_ISENE_LR_SFT) | |
| #define NAU8360_PD_LDO_SDM_IVSNS_SFT 6 | |
| #define NAU8360_PD_LDO_SDM_IVSNS_PMD (0x1 << NAU8360_PD_LDO_SDM_IVSNS_SFT) | |
| /* NAU8360_R6D_IVSNS_CFG1 (0x6d) */ | |
| #define NAU8360_PD_V2I_IVSNS_SFT 13 | |
| #define NAU8360_PD_V2I_IVSNS_MASK (0x1 << NAU8360_PD_V2I_IVSNS_SFT) | |
| #define NAU8360_PD_VREF_SDM_IVSNS_SFT 12 | |
| #define NAU8360_PD_VREF_SDM_IVSNS_MASK (0x1 << NAU8360_PD_VREF_SDM_IVSNS_SFT) | |
| #define NAU8360_VSNS_PGA_CUR_SET_SFT 10 | |
| #define NAU8360_VSNS_PGA_CUR_SET_MASK (0x3 << NAU8360_VSNS_PGA_CUR_SET_SFT) | |
| #define NAU8360_VSNS_GAIN_SFT 8 | |
| #define NAU8360_VSNS_GAIN_MASK (0x3 << NAU8360_VSNS_GAIN_SFT) | |
| #define NAU8360_VREF_CUR_SFT 6 | |
| #define NAU8360_VREF_CUR_MASK (0x3 << NAU8360_VREF_CUR_SFT) | |
| #define NAU8360_ISNS_PGA_CUR_SFT 4 | |
| #define NAU8360_ISNS_PGA_CUR_MASK (0x3 << NAU8360_ISNS_PGA_CUR_SFT) | |
| #define NAU8360_ISNS_GAIN_SFT 2 | |
| #define NAU8360_ISNS_GAIN_MASK (0x3 << NAU8360_ISNS_GAIN_SFT) | |
| #define NAU8360_SDM_DELAY_TRIM_MASK 0x3 | |
| /* NAU8360_R6E_DAC_CFG0 (0x6e) */ | |
| #define NAU8360_PD_DACL_SFT 11 | |
| #define NAU8360_PD_DACL_DIS (0x1 << NAU8360_PD_DACL_SFT) | |
| #define NAU8360_PD_DACR_SFT 10 | |
| #define NAU8360_PD_DACR_DIS (0x1 << NAU8360_PD_DACR_SFT) | |
| #define NAU8360_PD_CHOP_DAC_SFT 9 | |
| #define NAU8360_PD_CHOP_DAC_MASK (0x1 << NAU8360_PD_CHOP_DAC_SFT) | |
| #define NAU8360_DAC_RES_SFT 7 | |
| #define NAU8360_DAC_RES_MASK (0x1 << NAU8360_DAC_RES_SFT) | |
| #define NAU8360_DAC_CUR_SFT 6 | |
| #define NAU8360_DAC_CUR_MASK (0x1 << NAU8360_DAC_CUR_SFT) | |
| #define NAU8360_DAC_CUR_3_2DB (0x1 << NAU8360_DAC_CUR_SFT) | |
| #define NAU8360_DAC_CUR_0DB (0x0 << NAU8360_DAC_CUR_SFT) | |
| #define NAU8360_DAC_BUFOPCUR_SFT 4 | |
| #define NAU8360_DAC_BUFOPCUR_MASK (0x3 << NAU8360_DAC_BUFOPCUR_SFT) | |
| #define NAU8360_DAC_IVOPCUR_SFT 2 | |
| #define NAU8360_DAC_IVOPCUR_MASK (0x3 << NAU8360_DAC_IVOPCUR_SFT) | |
| #define NAU8360_DAC_LPFOP_CUR_MASK 0x3 | |
| /* NAU8360_R71_CLK_DIV_CFG (0x71) */ | |
| #define NAU8360_IVSNS_CLK_INV_SEL_SFT 10 | |
| #define NAU8360_IVSNS_CLK_INV_SEL_MASK (0x1 << NAU8360_IVSNS_CLK_INV_SEL_SFT) | |
| #define NAU8360_CLK_ANA_SEL_SFT 7 | |
| #define NAU8360_CLK_ANA_SEL_MASK (0x3 << NAU8360_CLK_ANA_SEL_SFT) | |
| #define NAU8360_CLK_ANA_SEL_PLL (0x2 << NAU8360_CLK_ANA_SEL_SFT) | |
| #define NAU8360_CLK_ANA_SEL_BCLK (0x1 << NAU8360_CLK_ANA_SEL_SFT) | |
| #define NAU8360_CLK_ANA_SEL_MCLK (0x0 << NAU8360_CLK_ANA_SEL_SFT) | |
| #define NAU8360_IVSNS_CLK_DIV_SFT 4 | |
| #define NAU8360_IVSNS_CLK_DIV_MASK (0x7 << NAU8360_IVSNS_CLK_DIV_SFT) | |
| #define NAU8360_DAC_OUTPUT_EDGE_SFT 3 | |
| #define NAU8360_DAC_OUTPUT_EDGE_MASK (0x1 << NAU8360_DAC_OUTPUT_EDGE_SFT) | |
| #define NAU8360_DAC_CLK_DIV_SFT 1 | |
| #define NAU8360_DAC_CLK_DIV_MASK (0x3 << NAU8360_DAC_CLK_DIV_SFT) | |
| #define NAU8360_DAC_CLK_DIV_8 (0x3 << NAU8360_DAC_CLK_DIV_SFT) | |
| #define NAU8360_DAC_CLK_DIV_4 (0x2 << NAU8360_DAC_CLK_DIV_SFT) | |
| #define NAU8360_DAC_CLK_DIV_2 (0x1 << NAU8360_DAC_CLK_DIV_SFT) | |
| #define NAU8360_DAC_CLK_DIV_1 (0x0 << NAU8360_DAC_CLK_DIV_SFT) | |
| #define NAU8360_DAC_CHOP_CLK_DIV_MASK 0x1 | |
| #define NAU8360_DAC_CHOP_CLK_DIV_32 0x1 | |
| #define NAU8360_DAC_CHOP_CLK_DIV_16 0x0 | |
| /* NAU8360_R72_PLL_CFG0 (0x72) */ | |
| #define NAU8360_PLLOUT_DIV_SFT 10 | |
| #define NAU8360_PLLOUT_DIV_MAX 0x1f | |
| #define NAU8360_PLLOUT_DIV_MASK (0x1f << NAU8360_PLLOUT_DIV_SFT) | |
| #define NAU8360_PLLOUT_DIV_BYPASS (0x0 << NAU8360_PLLOUT_DIV_SFT) | |
| #define NAU8360_PLL_CLK_SEL_SFT 8 | |
| #define NAU8360_PLL_CLK_SEL_MASK (0x3 << NAU8360_PLL_CLK_SEL_SFT) | |
| #define NAU8360_PLL_CLK_SEL_HIRC (0x3 << NAU8360_PLL_CLK_SEL_SFT) | |
| #define NAU8360_PLL_CLK_SEL_BCLK (0x1 << NAU8360_PLL_CLK_SEL_SFT) | |
| #define NAU8360_PLL_CLK_SEL_MCLK (0x0 << NAU8360_PLL_CLK_SEL_SFT) | |
| #define NAU8360_PD_PLL_SFT 7 | |
| #define NAU8360_PD_PLL_MASK (0x1 << NAU8360_PD_PLL_SFT) | |
| #define NAU8360_PD_PLL_DIS (0x1 << NAU8360_PD_PLL_SFT) | |
| #define NAU8360_PD_PLL_EN (0x0 << NAU8360_PD_PLL_SFT) | |
| /* NAU8360_R73_PLL_CFG1 (0x73) */ | |
| #define NAU8360_RSEL_SFT 13 | |
| #define NAU8360_RSEL_MASK (0x3 << NAU8360_RSEL_SFT) | |
| #define NAU8360_MSEL_SFT 8 | |
| #define NAU8360_MSEL_MASK (0x1f << NAU8360_MSEL_SFT) | |
| #define NAU8360_NSEL_MASK 0xff | |
| /* NAU8360_R74_PLL_CFG2 (0x74) */ | |
| #define NAU8360_XSEL_MASK 0xfff | |
| /* NAU8360_R77_SOFT_SD (0x77) */ | |
| #define NAU8360_SOFT_SD 0x55AA | |
| #define NAU8360_SOFT_SD_EN 0 | |
| /* NAU8360_R78_PD_SW_DLDO (0x78) */ | |
| #define NAU8360_PD_SW_DLDO 0xAA55 | |
| #define NAU8360_PD_SW_DLDO_EN 0 | |
| /* NAU8360_R7A_DAC_TRIM_CFG2 (0x7a) */ | |
| #define NAU8360_DAC_TEMP_SLOPE_SFT 8 | |
| #define NAU8360_DAC_TEMP_SLOPE_MASK (0x7f << NAU8360_DAC_TEMP_SLOPE_SFT) | |
| /* NAU8360_R7B_IVSNS_TRIM_CFG (0x7b) */ | |
| #define NAU8360_ISNS_TEMP_SLOPE_SFT 8 | |
| #define NAU8360_ISNS_TEMP_SLOPE_MASK (0x7f << NAU8360_ISNS_TEMP_SLOPE_SFT) | |
| #define NAU8360_VSNS_TEMP_SLOPE_MASK 0x7f | |
| /* NAU8360_R7C_MISC_TRIM_CFG (0x7c) */ | |
| #define NAU8360_DAC_OS_SB_SFT 13 | |
| #define NAU8360_DAC_OS_SB_SFT_MASK (0x7 << NAU8360_DAC_OS_SB_SFT) | |
| #define NAU8360_DAC_GAIN_SB_SFT 11 | |
| #define NAU8360_DAC_GAIN_SB_MASK (0x3 << NAU8360_DAC_GAIN_SB_SFT) | |
| #define NAU8360_DAC_TEMP_SB_SFT 9 | |
| #define NAU8360_DAC_TEMP_SB_MASK (0x3 << NAU8360_DAC_TEMP_SB_SFT) | |
| #define NAU8360_ISNS_TEMP_SB_SFT 6 | |
| #define NAU8360_ISNS_TEMP_SB_MASK (0x7 << NAU8360_ISNS_TEMP_SB_SFT) | |
| #define NAU8360_VSNS_TEMP_SB_SFT 4 | |
| #define NAU8360_VSNS_TEMP_SB_MASK (0x3 << NAU8360_VSNS_TEMP_SB_SFT) | |
| #define NAU8360_ISNS_GAIN_SB_SFT 2 | |
| #define NAU8360_ISNS_GAIN_SB_MASK (0x3 << NAU8360_ISNS_GAIN_SB_SFT) | |
| #define NAU8360_VSNS_GAIN_SB_MASK 0x3 | |
| /* NAU8360_R7E_CLK_GATED_EN (0x7e)*/ | |
| #define NAU8360_CLK_GATED_EN 0xa5a5 | |
| #define NAU8360_CLK_GATED_DIS 0 | |
| /* NAU8360_R86_HW3_CTL0 (0x86) */ | |
| #define NAU8360_HW3_DRAM_CLR_SFT 14 | |
| #define NAU8360_HW3_DRAM_CLR (0x1 << NAU8360_HW3_DRAM_CLR_SFT) | |
| #define NAU8360_HW3_STALL_SFT 13 | |
| #define NAU8360_HW3_STALL (0x1 << NAU8360_HW3_STALL_SFT) | |
| /* NAU8360_R8C_HW3_CTL6 (0x8c)*/ | |
| #define NAU8360_HW3_DROOP_SFT 2 | |
| #define NAU8360_HW3_DROOP_MASK (0x1 << NAU8360_HW3_DROOP_SFT) | |
| #define NAU8360_HW3_DROOP_192K (0x1 << NAU8360_HW3_DROOP_SFT) | |
| #define NAU8360_HW3_DROOP_96K (0x0 << NAU8360_HW3_DROOP_SFT) | |
| #define NAU8360_HW3_FS_MASK 0x1 | |
| #define NAU8360_HW3_FS_192K 0x1 | |
| #define NAU8360_HW3_FS_96K 0x0 | |
| /* NAU8360_R8F_HW3_CTL9 (0x8f)*/ | |
| #define NAU8360_HW3_CH_MUTE_SFT 8 | |
| #define NAU8360_HW3_CH_MUTE (0x1 << NAU8360_HW3_CH_MUTE_SFT) | |
| #define NAU8360_HW3_ZERO_THD_MASK 0xff | |
| /* NAU8360_R90_HW2_CTL0 (0x90) */ | |
| #define NAU8360_HW2_DRAM_CLR_SFT 14 | |
| #define NAU8360_HW2_DRAM_CLR (0x1 << NAU8360_HW2_DRAM_CLR_SFT) | |
| #define NAU8360_HW2_STALL_SFT 13 | |
| #define NAU8360_HW2_STALL (0x1 << NAU8360_HW2_STALL_SFT) | |
| /* NAU8360_R96_HW2_CTL6 (0x96) */ | |
| #define NAU8360_HW1_ANC_EN_SFT 15 | |
| #define NAU8360_HW1_ANC_EN (0x1 << NAU8360_HW1_ANC_EN_SFT) | |
| #define NAU8360_HW2_DROOP_SEL_SFT 3 | |
| #define NAU8360_HW2_DROOP_SEL_MASK (0x1 << NAU8360_HW2_DROOP_SEL_SFT) | |
| #define NAU8360_HW2_DROOP_SEL_LARGE (0x1 << NAU8360_HW2_DROOP_SEL_SFT) | |
| #define NAU8360_HW2_DROOP_SEL_SMALL (0x0 << NAU8360_HW2_DROOP_SEL_SFT) | |
| #define NAU8360_HW2_DROOP_EN_SFT 2 | |
| #define NAU8360_HW2_DROOP_EN (0x1 << NAU8360_HW2_DROOP_EN_SFT) | |
| #define NAU8360_HW2_LATENCY_SFT 1 | |
| #define NAU8360_HW2_LATENCY_MASK (0x1 << NAU8360_HW2_LATENCY_SFT) | |
| #define NAU8360_HW2_LATENCY_LOW (0x1 << NAU8360_HW2_LATENCY_SFT) | |
| #define NAU8360_HW2_LATENCY_NOR (0x0 << NAU8360_HW2_LATENCY_SFT) | |
| #define NAU8360_HW2_FS_MASK 0x1 | |
| #define NAU8360_HW2_FS_192K 0x1 | |
| #define NAU8360_HW2_FS_96K 0x0 | |
| /* NAU8360_R99_HW2_CTL9 (0x99) */ | |
| #define NAU8360_HW2_VSR_SFT 9 | |
| #define NAU8360_HW2_VSR_MASK (0x3 << NAU8360_HW2_VSR_SFT) | |
| #define NAU8360_HW2_CH_MUTE_SFT 8 | |
| #define NAU8360_HW2_CH_MUTE (0x1 << NAU8360_HW2_CH_MUTE_SFT) | |
| #define NAU8360_HW2_ZERO_THD_MASK 0xff | |
| /* NAU8360_R9C_HW1_CTL2 (0x9c) */ | |
| #define NAU8360_MUTE_INTRVL_SFT 11 | |
| #define NAU8360_MUTE_INTRVL_MASK (0x3 << NAU8360_MUTE_INTRVL_SFT) | |
| #define NAU8360_MUTE_INTRVL_699MS (0x3 << NAU8360_MUTE_INTRVL_SFT) | |
| #define NAU8360_MUTE_INTRVL_466MS (0x2 << NAU8360_MUTE_INTRVL_SFT) | |
| #define NAU8360_MUTE_INTRVL_233MS (0x1 << NAU8360_MUTE_INTRVL_SFT) | |
| #define NAU8360_HW1_CH_MUTE_SFT 8 | |
| #define NAU8360_HW1_CH_MUTE (0x1 << NAU8360_HW1_CH_MUTE_SFT) | |
| #define NAU8360_HW1_ZERO_THD_MASK 0xff | |
| /* NAU8360_R9D_PEQ_CTL (0x9d) */ | |
| #define NAU8360_PEQ_BAND_SFT 12 | |
| #define NAU8360_PEQ_BAND_MASK (0xf << NAU8360_PEQ_BAND_SFT) | |
| #define NAU8360_HW1_MEM_TEST_SFT 2 | |
| #define NAU8360_HW1_MEM_TEST (0x1 << NAU8360_HW1_MEM_TEST_SFT) | |
| #define NAU8360_HW1_MEM_CLEAR_SFT 1 | |
| #define NAU8360_HW1_MEM_CLEAR (0x1 << NAU8360_HW1_MEM_CLEAR_SFT) | |
| #define NAU8360_PEQ_STALL 0x1 | |
| /* NAU8360_RA4_ANA_REG_0 (0xa4) */ | |
| #define NAU8360_MSEL_SAW_SFT 8 | |
| #define NAU8360_MSEL_SAW_MASK (0xff << NAU8360_MSEL_SAW_SFT) | |
| #define NAU8360_FTRIM_PWM_SFT 6 | |
| #define NAU8360_FTRIM_PWM_MASK (0x3 << NAU8360_MSEL_SAW_SFT) | |
| #define NAU8360_SEL_STCLK_SFT 5 | |
| #define NAU8360_SEL_STCLK_MASK (0x1 << NAU8360_SEL_STCLK_SFT) | |
| #define NAU8360_SEL_STCLK_IVCLK (0x1 << NAU8360_SEL_STCLK_SFT) | |
| #define NAU8360_SEL_STCLK_FREERUN (0x0 << NAU8360_SEL_STCLK_SFT) | |
| #define NAU8360_NSEL_SAW_MASK 0x1f | |
| /* NAU8360_RA5_ANA_REG_1 (0xa5) */ | |
| #define NAU8360_ICP_SAW_SET_SFT 14 | |
| #define NAU8360_ICP_SAW_SET_MASK (0x3 << NAU8360_ICP_SAW_SET_SFT) | |
| #define NAU8360_VSAW_LV_SFT 12 | |
| #define NAU8360_VSAW_LV_MASK (0x3 << NAU8360_VSAW_LV_SFT) | |
| #define NAU8360_KVCO_SAW_SFT 10 | |
| #define NAU8360_KVCO_SAW_MASK (0x3 << NAU8360_KVCO_SAW_SFT) | |
| #define NAU8360_TRIM_LPF_SFT 8 | |
| #define NAU8360_TRIM_LPF_MASK (0x3 << NAU8360_TRIM_LPF_SFT) | |
| #define NAU8360_SAW_PLL_SFT 7 | |
| #define NAU8360_SAW_PLL_MASK (0x1 << NAU8360_SAW_PLL_SFT) | |
| #define NAU8360_SAW_PLL_NOR (0x1 << NAU8360_SAW_PLL_SFT) | |
| #define NAU8360_SAW_PLL_RST (0x0 << NAU8360_SAW_PLL_SFT) | |
| #define NAU8360_CLASSD_SHT_SFT 6 | |
| #define NAU8360_CLASSD_SHT_IN (0x1 << NAU8360_CLASSD_SHT_SFT) | |
| #define NAU8360_HVEN_SYNC_SFT 5 | |
| #define NAU8360_HVEN_SYNC_SAW (0x1 << NAU8360_HVEN_SYNC_SFT) | |
| #define NAU8360_SYNC_SAW_CLK_SFT 4 | |
| #define NAU8360_SYNC_SAW_CLK_INVT (0x1 << NAU8360_SYNC_SAW_CLK_SFT) | |
| #define NAU8360_DEPOP_CAP_SFT 2 | |
| #define NAU8360_DEPOP_CAP_MASK (0x3 << NAU8360_DEPOP_CAP_SFT) | |
| #define NAU8360_DEPOP_CAP_48PF (0x3 << NAU8360_DEPOP_CAP_SFT) | |
| #define NAU8360_DEPOP_CAP_36PF (0x2 << NAU8360_DEPOP_CAP_SFT) | |
| #define NAU8360_DEPOP_CAP_24PF (0x1 << NAU8360_DEPOP_CAP_SFT) | |
| #define NAU8360_DEPOP_CAP_12PF (0x0 << NAU8360_DEPOP_CAP_SFT) | |
| #define NAU8360_SW_BG_IO_SFT 1 | |
| #define NAU8360_SW_BG_IO_CONN (0x1 << NAU8360_SW_BG_IO_SFT) | |
| #define NAU8360_SW_VPTC_IO_EN 0x1 | |
| /* NAU8360 VBAT Range Thresholds */ | |
| #define NAU8360_VBAT_MIN 8 | |
| #define NAU8360_VBAT_MID_THRES 13 | |
| #define NAU8360_VBAT_HIGH_THRES 19 | |
| #define NAU8360_VBAT_MAX 24 | |
| /* NAU8360_R100_LEFT_BIQ0_COE (0x100) | |
| * NAU8360_R200_RIGHT_BIQ0_COE (0x200) | |
| */ | |
| #define NAU8360_TOT_BAND_PER_CH 15 | |
| #define NAU8360_TOT_BAND_COE 10 | |
| #define NAU8360_TOT_BAND_COE_RANGE (NAU8360_TOT_BAND_COE + 2) | |
| #define NAU8360_PEQ_REG_WIDTH (NAU8360_TOT_BAND_COE - 1) | |
| /* DSP stereo core */ | |
| #define NAU8360_DSP_CORE_NUM 2 | |
| #define NAU8360_DSP_ADDR_BYNAME(x) \ | |
| (strstr((x), "Left") ? NAU8360_RF000_DSP_COMM : NAU8360_RF002_DSP_COMM) | |
| #define NAU8360_I2C_REG_LEN 2 | |
| #define NAU8360_I2C_RXBUF_LEN 4 | |
| #define NAU8360_I2C_TXBUF_LEN 6 | |
| #define NAU8360_CODEC_DAI "nau8360-hifi" | |
| /* clock source */ | |
| enum { | |
| NAU8360_CLK_SRC_MCLK, | |
| NAU8360_CLK_SRC_PLL, | |
| NAU8360_CLK_SRC_ICLK, | |
| NAU8360_CLK_SRC_BCLK, | |
| }; | |
| /* clock target */ | |
| enum { | |
| NAU8360_CLK_ID_DIG, /* DIG_SYS + DSP + HW */ | |
| NAU8360_CLK_ID_ANA, /* IV + DAC */ | |
| NAU8360_CLK_ID_INT, /* HIRC48M standby */ | |
| }; | |
| enum { | |
| NAU8360_MCLK_FS_RATIO_250 = 250, | |
| NAU8360_MCLK_FS_RATIO_256 = 256, | |
| NAU8360_MCLK_FS_RATIO_400 = 400, | |
| NAU8360_MCLK_FS_RATIO_500 = 500, | |
| NAU8360_MCLK_FS_RATIO_512 = 512, | |
| }; | |
| enum { | |
| NAU8360_PEQ_BAND_8 = 8, | |
| NAU8360_PEQ_BAND_12 = 12, | |
| NAU8360_PEQ_BAND_15 = 15, | |
| }; | |
| #define NAU8360_TDM_MAX_CHAN 8 | |
| #define TDM_SLOT_NONE 255 | |
| enum { | |
| NAU8360_TDM_DACL, | |
| NAU8360_TDM_DACR, | |
| NAU8360_TDM_ANCL, | |
| NAU8360_TDM_ANCR, | |
| NAU8360_TDM_RXN, | |
| }; | |
| enum { | |
| NAU8360_TDM_AECL, | |
| NAU8360_TDM_AECR, | |
| NAU8360_TDM_ISNSL, | |
| NAU8360_TDM_ISNSR, | |
| NAU8360_TDM_VSNSL, | |
| NAU8360_TDM_VSNSR, | |
| NAU8360_TDM_TJ, | |
| NAU8360_TDM_VBAT, | |
| NAU8360_TDM_TXN, | |
| }; | |
| /* DAC Source Path*/ | |
| enum { | |
| NAU8360_DAC_SRC_HW1 = 0, | |
| NAU8360_DAC_SRC_DSP, | |
| }; | |
| /* PLL Source */ | |
| enum { | |
| NAU8360_PLL_MCLK, | |
| NAU8360_PLL_BCLK, | |
| NAU8360_PLL_INTERNAL, | |
| }; | |
| struct nau8360_pll { | |
| int src; | |
| int input; | |
| int output; | |
| int msel; | |
| int rsel; | |
| int nsel; | |
| int xsel; | |
| }; | |
| struct nau8360 { | |
| struct device *dev; | |
| struct regmap *regmap; | |
| struct mutex lock; | |
| struct snd_soc_dapm_context *dapm; | |
| int sys_clk; | |
| int anc_enable; | |
| int pbtl_enable; | |
| int dac_cur_enable; | |
| int kcs_setup_size; | |
| struct nau8360_pll pll; | |
| u32 tdm_tx_func_slot[NAU8360_TDM_TXN]; | |
| u32 tdm_rx_func_slot[NAU8360_TDM_RXN]; | |
| u8 i2c_read_reg[NAU8360_I2C_REG_LEN] ____cacheline_aligned; | |
| u8 i2c_read_buf[NAU8360_I2C_RXBUF_LEN] ____cacheline_aligned; | |
| u8 i2c_write_buf[NAU8360_I2C_TXBUF_LEN] ____cacheline_aligned; | |
| struct work_struct load_fw_work; | |
| const char *dsp_firmware[NAU8360_DSP_CORE_NUM]; | |
| bool load_fw_done; | |
| }; | |
| #endif /* __NAU8360_H__ */ |