| /* |
| * libata-core.c - helper library for ATA |
| * |
| * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| * Please ALWAYS copy linux-ide@vger.kernel.org |
| * on emails. |
| * |
| * Copyright 2003-2004 Red Hat, Inc. All rights reserved. |
| * Copyright 2003-2004 Jeff Garzik |
| * |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2, or (at your option) |
| * any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; see the file COPYING. If not, write to |
| * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| * |
| * |
| * libata documentation is available via 'make {ps|pdf}docs', |
| * as Documentation/DocBook/libata.* |
| * |
| * Hardware documentation available from http://www.t13.org/ and |
| * http://www.sata-io.org/ |
| * |
| */ |
| |
| #include <linux/config.h> |
| #include <linux/kernel.h> |
| #include <linux/module.h> |
| #include <linux/pci.h> |
| #include <linux/init.h> |
| #include <linux/list.h> |
| #include <linux/mm.h> |
| #include <linux/highmem.h> |
| #include <linux/spinlock.h> |
| #include <linux/blkdev.h> |
| #include <linux/delay.h> |
| #include <linux/timer.h> |
| #include <linux/interrupt.h> |
| #include <linux/completion.h> |
| #include <linux/suspend.h> |
| #include <linux/workqueue.h> |
| #include <linux/jiffies.h> |
| #include <linux/scatterlist.h> |
| #include <scsi/scsi.h> |
| #include "scsi_priv.h" |
| #include <scsi/scsi_cmnd.h> |
| #include <scsi/scsi_host.h> |
| #include <linux/libata.h> |
| #include <asm/io.h> |
| #include <asm/semaphore.h> |
| #include <asm/byteorder.h> |
| |
| #include "libata.h" |
| |
| static unsigned int ata_busy_sleep (struct ata_port *ap, |
| unsigned long tmout_pat, |
| unsigned long tmout); |
| static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev); |
| static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev); |
| static void ata_set_mode(struct ata_port *ap); |
| static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev); |
| static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift); |
| static int fgb(u32 bitmap); |
| static int ata_choose_xfer_mode(const struct ata_port *ap, |
| u8 *xfer_mode_out, |
| unsigned int *xfer_shift_out); |
| static void __ata_qc_complete(struct ata_queued_cmd *qc); |
| |
| static unsigned int ata_unique_id = 1; |
| static struct workqueue_struct *ata_wq; |
| |
| int atapi_enabled = 0; |
| module_param(atapi_enabled, int, 0444); |
| MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)"); |
| |
| MODULE_AUTHOR("Jeff Garzik"); |
| MODULE_DESCRIPTION("Library module for ATA devices"); |
| MODULE_LICENSE("GPL"); |
| MODULE_VERSION(DRV_VERSION); |
| |
| /** |
| * ata_tf_load_pio - send taskfile registers to host controller |
| * @ap: Port to which output is sent |
| * @tf: ATA taskfile register set |
| * |
| * Outputs ATA taskfile to standard ATA host controller. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf) |
| { |
| struct ata_ioports *ioaddr = &ap->ioaddr; |
| unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; |
| |
| if (tf->ctl != ap->last_ctl) { |
| outb(tf->ctl, ioaddr->ctl_addr); |
| ap->last_ctl = tf->ctl; |
| ata_wait_idle(ap); |
| } |
| |
| if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { |
| outb(tf->hob_feature, ioaddr->feature_addr); |
| outb(tf->hob_nsect, ioaddr->nsect_addr); |
| outb(tf->hob_lbal, ioaddr->lbal_addr); |
| outb(tf->hob_lbam, ioaddr->lbam_addr); |
| outb(tf->hob_lbah, ioaddr->lbah_addr); |
| VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", |
| tf->hob_feature, |
| tf->hob_nsect, |
| tf->hob_lbal, |
| tf->hob_lbam, |
| tf->hob_lbah); |
| } |
| |
| if (is_addr) { |
| outb(tf->feature, ioaddr->feature_addr); |
| outb(tf->nsect, ioaddr->nsect_addr); |
| outb(tf->lbal, ioaddr->lbal_addr); |
| outb(tf->lbam, ioaddr->lbam_addr); |
| outb(tf->lbah, ioaddr->lbah_addr); |
| VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", |
| tf->feature, |
| tf->nsect, |
| tf->lbal, |
| tf->lbam, |
| tf->lbah); |
| } |
| |
| if (tf->flags & ATA_TFLAG_DEVICE) { |
| outb(tf->device, ioaddr->device_addr); |
| VPRINTK("device 0x%X\n", tf->device); |
| } |
| |
| ata_wait_idle(ap); |
| } |
| |
| /** |
| * ata_tf_load_mmio - send taskfile registers to host controller |
| * @ap: Port to which output is sent |
| * @tf: ATA taskfile register set |
| * |
| * Outputs ATA taskfile to standard ATA host controller using MMIO. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
| { |
| struct ata_ioports *ioaddr = &ap->ioaddr; |
| unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; |
| |
| if (tf->ctl != ap->last_ctl) { |
| writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr); |
| ap->last_ctl = tf->ctl; |
| ata_wait_idle(ap); |
| } |
| |
| if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { |
| writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr); |
| writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr); |
| writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr); |
| writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr); |
| writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr); |
| VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", |
| tf->hob_feature, |
| tf->hob_nsect, |
| tf->hob_lbal, |
| tf->hob_lbam, |
| tf->hob_lbah); |
| } |
| |
| if (is_addr) { |
| writeb(tf->feature, (void __iomem *) ioaddr->feature_addr); |
| writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr); |
| writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr); |
| writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr); |
| writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr); |
| VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", |
| tf->feature, |
| tf->nsect, |
| tf->lbal, |
| tf->lbam, |
| tf->lbah); |
| } |
| |
| if (tf->flags & ATA_TFLAG_DEVICE) { |
| writeb(tf->device, (void __iomem *) ioaddr->device_addr); |
| VPRINTK("device 0x%X\n", tf->device); |
| } |
| |
| ata_wait_idle(ap); |
| } |
| |
| |
| /** |
| * ata_tf_load - send taskfile registers to host controller |
| * @ap: Port to which output is sent |
| * @tf: ATA taskfile register set |
| * |
| * Outputs ATA taskfile to standard ATA host controller using MMIO |
| * or PIO as indicated by the ATA_FLAG_MMIO flag. |
| * Writes the control, feature, nsect, lbal, lbam, and lbah registers. |
| * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect, |
| * hob_lbal, hob_lbam, and hob_lbah. |
| * |
| * This function waits for idle (!BUSY and !DRQ) after writing |
| * registers. If the control register has a new value, this |
| * function also waits for idle after writing control and before |
| * writing the remaining registers. |
| * |
| * May be used as the tf_load() entry in ata_port_operations. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
| { |
| if (ap->flags & ATA_FLAG_MMIO) |
| ata_tf_load_mmio(ap, tf); |
| else |
| ata_tf_load_pio(ap, tf); |
| } |
| |
| /** |
| * ata_exec_command_pio - issue ATA command to host controller |
| * @ap: port to which command is being issued |
| * @tf: ATA taskfile register set |
| * |
| * Issues PIO write to ATA command register, with proper |
| * synchronization with interrupt handler / other threads. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| */ |
| |
| static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf) |
| { |
| DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); |
| |
| outb(tf->command, ap->ioaddr.command_addr); |
| ata_pause(ap); |
| } |
| |
| |
| /** |
| * ata_exec_command_mmio - issue ATA command to host controller |
| * @ap: port to which command is being issued |
| * @tf: ATA taskfile register set |
| * |
| * Issues MMIO write to ATA command register, with proper |
| * synchronization with interrupt handler / other threads. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| */ |
| |
| static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
| { |
| DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); |
| |
| writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr); |
| ata_pause(ap); |
| } |
| |
| |
| /** |
| * ata_exec_command - issue ATA command to host controller |
| * @ap: port to which command is being issued |
| * @tf: ATA taskfile register set |
| * |
| * Issues PIO/MMIO write to ATA command register, with proper |
| * synchronization with interrupt handler / other threads. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| */ |
| void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
| { |
| if (ap->flags & ATA_FLAG_MMIO) |
| ata_exec_command_mmio(ap, tf); |
| else |
| ata_exec_command_pio(ap, tf); |
| } |
| |
| /** |
| * ata_tf_to_host - issue ATA taskfile to host controller |
| * @ap: port to which command is being issued |
| * @tf: ATA taskfile register set |
| * |
| * Issues ATA taskfile register set to ATA host controller, |
| * with proper synchronization with interrupt handler and |
| * other threads. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| */ |
| |
| static inline void ata_tf_to_host(struct ata_port *ap, |
| const struct ata_taskfile *tf) |
| { |
| ap->ops->tf_load(ap, tf); |
| ap->ops->exec_command(ap, tf); |
| } |
| |
| /** |
| * ata_tf_read_pio - input device's ATA taskfile shadow registers |
| * @ap: Port from which input is read |
| * @tf: ATA taskfile register set for storing input |
| * |
| * Reads ATA taskfile registers for currently-selected device |
| * into @tf. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf) |
| { |
| struct ata_ioports *ioaddr = &ap->ioaddr; |
| |
| tf->command = ata_check_status(ap); |
| tf->feature = inb(ioaddr->error_addr); |
| tf->nsect = inb(ioaddr->nsect_addr); |
| tf->lbal = inb(ioaddr->lbal_addr); |
| tf->lbam = inb(ioaddr->lbam_addr); |
| tf->lbah = inb(ioaddr->lbah_addr); |
| tf->device = inb(ioaddr->device_addr); |
| |
| if (tf->flags & ATA_TFLAG_LBA48) { |
| outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr); |
| tf->hob_feature = inb(ioaddr->error_addr); |
| tf->hob_nsect = inb(ioaddr->nsect_addr); |
| tf->hob_lbal = inb(ioaddr->lbal_addr); |
| tf->hob_lbam = inb(ioaddr->lbam_addr); |
| tf->hob_lbah = inb(ioaddr->lbah_addr); |
| } |
| } |
| |
| /** |
| * ata_tf_read_mmio - input device's ATA taskfile shadow registers |
| * @ap: Port from which input is read |
| * @tf: ATA taskfile register set for storing input |
| * |
| * Reads ATA taskfile registers for currently-selected device |
| * into @tf via MMIO. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf) |
| { |
| struct ata_ioports *ioaddr = &ap->ioaddr; |
| |
| tf->command = ata_check_status(ap); |
| tf->feature = readb((void __iomem *)ioaddr->error_addr); |
| tf->nsect = readb((void __iomem *)ioaddr->nsect_addr); |
| tf->lbal = readb((void __iomem *)ioaddr->lbal_addr); |
| tf->lbam = readb((void __iomem *)ioaddr->lbam_addr); |
| tf->lbah = readb((void __iomem *)ioaddr->lbah_addr); |
| tf->device = readb((void __iomem *)ioaddr->device_addr); |
| |
| if (tf->flags & ATA_TFLAG_LBA48) { |
| writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr); |
| tf->hob_feature = readb((void __iomem *)ioaddr->error_addr); |
| tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr); |
| tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr); |
| tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr); |
| tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr); |
| } |
| } |
| |
| |
| /** |
| * ata_tf_read - input device's ATA taskfile shadow registers |
| * @ap: Port from which input is read |
| * @tf: ATA taskfile register set for storing input |
| * |
| * Reads ATA taskfile registers for currently-selected device |
| * into @tf. |
| * |
| * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48 |
| * is set, also reads the hob registers. |
| * |
| * May be used as the tf_read() entry in ata_port_operations. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
| { |
| if (ap->flags & ATA_FLAG_MMIO) |
| ata_tf_read_mmio(ap, tf); |
| else |
| ata_tf_read_pio(ap, tf); |
| } |
| |
| /** |
| * ata_check_status_pio - Read device status reg & clear interrupt |
| * @ap: port where the device is |
| * |
| * Reads ATA taskfile status register for currently-selected device |
| * and return its value. This also clears pending interrupts |
| * from this device |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| static u8 ata_check_status_pio(struct ata_port *ap) |
| { |
| return inb(ap->ioaddr.status_addr); |
| } |
| |
| /** |
| * ata_check_status_mmio - Read device status reg & clear interrupt |
| * @ap: port where the device is |
| * |
| * Reads ATA taskfile status register for currently-selected device |
| * via MMIO and return its value. This also clears pending interrupts |
| * from this device |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| static u8 ata_check_status_mmio(struct ata_port *ap) |
| { |
| return readb((void __iomem *) ap->ioaddr.status_addr); |
| } |
| |
| |
| /** |
| * ata_check_status - Read device status reg & clear interrupt |
| * @ap: port where the device is |
| * |
| * Reads ATA taskfile status register for currently-selected device |
| * and return its value. This also clears pending interrupts |
| * from this device |
| * |
| * May be used as the check_status() entry in ata_port_operations. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| u8 ata_check_status(struct ata_port *ap) |
| { |
| if (ap->flags & ATA_FLAG_MMIO) |
| return ata_check_status_mmio(ap); |
| return ata_check_status_pio(ap); |
| } |
| |
| |
| /** |
| * ata_altstatus - Read device alternate status reg |
| * @ap: port where the device is |
| * |
| * Reads ATA taskfile alternate status register for |
| * currently-selected device and return its value. |
| * |
| * Note: may NOT be used as the check_altstatus() entry in |
| * ata_port_operations. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| u8 ata_altstatus(struct ata_port *ap) |
| { |
| if (ap->ops->check_altstatus) |
| return ap->ops->check_altstatus(ap); |
| |
| if (ap->flags & ATA_FLAG_MMIO) |
| return readb((void __iomem *)ap->ioaddr.altstatus_addr); |
| return inb(ap->ioaddr.altstatus_addr); |
| } |
| |
| |
| /** |
| * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure |
| * @tf: Taskfile to convert |
| * @fis: Buffer into which data will output |
| * @pmp: Port multiplier port |
| * |
| * Converts a standard ATA taskfile to a Serial ATA |
| * FIS structure (Register - Host to Device). |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp) |
| { |
| fis[0] = 0x27; /* Register - Host to Device FIS */ |
| fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number, |
| bit 7 indicates Command FIS */ |
| fis[2] = tf->command; |
| fis[3] = tf->feature; |
| |
| fis[4] = tf->lbal; |
| fis[5] = tf->lbam; |
| fis[6] = tf->lbah; |
| fis[7] = tf->device; |
| |
| fis[8] = tf->hob_lbal; |
| fis[9] = tf->hob_lbam; |
| fis[10] = tf->hob_lbah; |
| fis[11] = tf->hob_feature; |
| |
| fis[12] = tf->nsect; |
| fis[13] = tf->hob_nsect; |
| fis[14] = 0; |
| fis[15] = tf->ctl; |
| |
| fis[16] = 0; |
| fis[17] = 0; |
| fis[18] = 0; |
| fis[19] = 0; |
| } |
| |
| /** |
| * ata_tf_from_fis - Convert SATA FIS to ATA taskfile |
| * @fis: Buffer from which data will be input |
| * @tf: Taskfile to output |
| * |
| * Converts a serial ATA FIS structure to a standard ATA taskfile. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf) |
| { |
| tf->command = fis[2]; /* status */ |
| tf->feature = fis[3]; /* error */ |
| |
| tf->lbal = fis[4]; |
| tf->lbam = fis[5]; |
| tf->lbah = fis[6]; |
| tf->device = fis[7]; |
| |
| tf->hob_lbal = fis[8]; |
| tf->hob_lbam = fis[9]; |
| tf->hob_lbah = fis[10]; |
| |
| tf->nsect = fis[12]; |
| tf->hob_nsect = fis[13]; |
| } |
| |
| static const u8 ata_rw_cmds[] = { |
| /* pio multi */ |
| ATA_CMD_READ_MULTI, |
| ATA_CMD_WRITE_MULTI, |
| ATA_CMD_READ_MULTI_EXT, |
| ATA_CMD_WRITE_MULTI_EXT, |
| /* pio */ |
| ATA_CMD_PIO_READ, |
| ATA_CMD_PIO_WRITE, |
| ATA_CMD_PIO_READ_EXT, |
| ATA_CMD_PIO_WRITE_EXT, |
| /* dma */ |
| ATA_CMD_READ, |
| ATA_CMD_WRITE, |
| ATA_CMD_READ_EXT, |
| ATA_CMD_WRITE_EXT |
| }; |
| |
| /** |
| * ata_rwcmd_protocol - set taskfile r/w commands and protocol |
| * @qc: command to examine and configure |
| * |
| * Examine the device configuration and tf->flags to calculate |
| * the proper read/write commands and protocol to use. |
| * |
| * LOCKING: |
| * caller. |
| */ |
| void ata_rwcmd_protocol(struct ata_queued_cmd *qc) |
| { |
| struct ata_taskfile *tf = &qc->tf; |
| struct ata_device *dev = qc->dev; |
| |
| int index, lba48, write; |
| |
| lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0; |
| write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0; |
| |
| if (dev->flags & ATA_DFLAG_PIO) { |
| tf->protocol = ATA_PROT_PIO; |
| index = dev->multi_count ? 0 : 4; |
| } else { |
| tf->protocol = ATA_PROT_DMA; |
| index = 8; |
| } |
| |
| tf->command = ata_rw_cmds[index + lba48 + write]; |
| } |
| |
| static const char * xfer_mode_str[] = { |
| "UDMA/16", |
| "UDMA/25", |
| "UDMA/33", |
| "UDMA/44", |
| "UDMA/66", |
| "UDMA/100", |
| "UDMA/133", |
| "UDMA7", |
| "MWDMA0", |
| "MWDMA1", |
| "MWDMA2", |
| "PIO0", |
| "PIO1", |
| "PIO2", |
| "PIO3", |
| "PIO4", |
| }; |
| |
| /** |
| * ata_udma_string - convert UDMA bit offset to string |
| * @mask: mask of bits supported; only highest bit counts. |
| * |
| * Determine string which represents the highest speed |
| * (highest bit in @udma_mask). |
| * |
| * LOCKING: |
| * None. |
| * |
| * RETURNS: |
| * Constant C string representing highest speed listed in |
| * @udma_mask, or the constant C string "<n/a>". |
| */ |
| |
| static const char *ata_mode_string(unsigned int mask) |
| { |
| int i; |
| |
| for (i = 7; i >= 0; i--) |
| if (mask & (1 << i)) |
| goto out; |
| for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--) |
| if (mask & (1 << i)) |
| goto out; |
| for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--) |
| if (mask & (1 << i)) |
| goto out; |
| |
| return "<n/a>"; |
| |
| out: |
| return xfer_mode_str[i]; |
| } |
| |
| /** |
| * ata_pio_devchk - PATA device presence detection |
| * @ap: ATA channel to examine |
| * @device: Device to examine (starting at zero) |
| * |
| * This technique was originally described in |
| * Hale Landis's ATADRVR (www.ata-atapi.com), and |
| * later found its way into the ATA/ATAPI spec. |
| * |
| * Write a pattern to the ATA shadow registers, |
| * and if a device is present, it will respond by |
| * correctly storing and echoing back the |
| * ATA shadow register contents. |
| * |
| * LOCKING: |
| * caller. |
| */ |
| |
| static unsigned int ata_pio_devchk(struct ata_port *ap, |
| unsigned int device) |
| { |
| struct ata_ioports *ioaddr = &ap->ioaddr; |
| u8 nsect, lbal; |
| |
| ap->ops->dev_select(ap, device); |
| |
| outb(0x55, ioaddr->nsect_addr); |
| outb(0xaa, ioaddr->lbal_addr); |
| |
| outb(0xaa, ioaddr->nsect_addr); |
| outb(0x55, ioaddr->lbal_addr); |
| |
| outb(0x55, ioaddr->nsect_addr); |
| outb(0xaa, ioaddr->lbal_addr); |
| |
| nsect = inb(ioaddr->nsect_addr); |
| lbal = inb(ioaddr->lbal_addr); |
| |
| if ((nsect == 0x55) && (lbal == 0xaa)) |
| return 1; /* we found a device */ |
| |
| return 0; /* nothing found */ |
| } |
| |
| /** |
| * ata_mmio_devchk - PATA device presence detection |
| * @ap: ATA channel to examine |
| * @device: Device to examine (starting at zero) |
| * |
| * This technique was originally described in |
| * Hale Landis's ATADRVR (www.ata-atapi.com), and |
| * later found its way into the ATA/ATAPI spec. |
| * |
| * Write a pattern to the ATA shadow registers, |
| * and if a device is present, it will respond by |
| * correctly storing and echoing back the |
| * ATA shadow register contents. |
| * |
| * LOCKING: |
| * caller. |
| */ |
| |
| static unsigned int ata_mmio_devchk(struct ata_port *ap, |
| unsigned int device) |
| { |
| struct ata_ioports *ioaddr = &ap->ioaddr; |
| u8 nsect, lbal; |
| |
| ap->ops->dev_select(ap, device); |
| |
| writeb(0x55, (void __iomem *) ioaddr->nsect_addr); |
| writeb(0xaa, (void __iomem *) ioaddr->lbal_addr); |
| |
| writeb(0xaa, (void __iomem *) ioaddr->nsect_addr); |
| writeb(0x55, (void __iomem *) ioaddr->lbal_addr); |
| |
| writeb(0x55, (void __iomem *) ioaddr->nsect_addr); |
| writeb(0xaa, (void __iomem *) ioaddr->lbal_addr); |
| |
| nsect = readb((void __iomem *) ioaddr->nsect_addr); |
| lbal = readb((void __iomem *) ioaddr->lbal_addr); |
| |
| if ((nsect == 0x55) && (lbal == 0xaa)) |
| return 1; /* we found a device */ |
| |
| return 0; /* nothing found */ |
| } |
| |
| /** |
| * ata_devchk - PATA device presence detection |
| * @ap: ATA channel to examine |
| * @device: Device to examine (starting at zero) |
| * |
| * Dispatch ATA device presence detection, depending |
| * on whether we are using PIO or MMIO to talk to the |
| * ATA shadow registers. |
| * |
| * LOCKING: |
| * caller. |
| */ |
| |
| static unsigned int ata_devchk(struct ata_port *ap, |
| unsigned int device) |
| { |
| if (ap->flags & ATA_FLAG_MMIO) |
| return ata_mmio_devchk(ap, device); |
| return ata_pio_devchk(ap, device); |
| } |
| |
| /** |
| * ata_dev_classify - determine device type based on ATA-spec signature |
| * @tf: ATA taskfile register set for device to be identified |
| * |
| * Determine from taskfile register contents whether a device is |
| * ATA or ATAPI, as per "Signature and persistence" section |
| * of ATA/PI spec (volume 1, sect 5.14). |
| * |
| * LOCKING: |
| * None. |
| * |
| * RETURNS: |
| * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN |
| * the event of failure. |
| */ |
| |
| unsigned int ata_dev_classify(const struct ata_taskfile *tf) |
| { |
| /* Apple's open source Darwin code hints that some devices only |
| * put a proper signature into the LBA mid/high registers, |
| * So, we only check those. It's sufficient for uniqueness. |
| */ |
| |
| if (((tf->lbam == 0) && (tf->lbah == 0)) || |
| ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) { |
| DPRINTK("found ATA device by sig\n"); |
| return ATA_DEV_ATA; |
| } |
| |
| if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) || |
| ((tf->lbam == 0x69) && (tf->lbah == 0x96))) { |
| DPRINTK("found ATAPI device by sig\n"); |
| return ATA_DEV_ATAPI; |
| } |
| |
| DPRINTK("unknown device\n"); |
| return ATA_DEV_UNKNOWN; |
| } |
| |
| /** |
| * ata_dev_try_classify - Parse returned ATA device signature |
| * @ap: ATA channel to examine |
| * @device: Device to examine (starting at zero) |
| * |
| * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
| * an ATA/ATAPI-defined set of values is placed in the ATA |
| * shadow registers, indicating the results of device detection |
| * and diagnostics. |
| * |
| * Select the ATA device, and read the values from the ATA shadow |
| * registers. Then parse according to the Error register value, |
| * and the spec-defined values examined by ata_dev_classify(). |
| * |
| * LOCKING: |
| * caller. |
| */ |
| |
| static u8 ata_dev_try_classify(struct ata_port *ap, unsigned int device) |
| { |
| struct ata_device *dev = &ap->device[device]; |
| struct ata_taskfile tf; |
| unsigned int class; |
| u8 err; |
| |
| ap->ops->dev_select(ap, device); |
| |
| memset(&tf, 0, sizeof(tf)); |
| |
| ap->ops->tf_read(ap, &tf); |
| err = tf.feature; |
| |
| dev->class = ATA_DEV_NONE; |
| |
| /* see if device passed diags */ |
| if (err == 1) |
| /* do nothing */ ; |
| else if ((device == 0) && (err == 0x81)) |
| /* do nothing */ ; |
| else |
| return err; |
| |
| /* determine if device if ATA or ATAPI */ |
| class = ata_dev_classify(&tf); |
| if (class == ATA_DEV_UNKNOWN) |
| return err; |
| if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0)) |
| return err; |
| |
| dev->class = class; |
| |
| return err; |
| } |
| |
| /** |
| * ata_dev_id_string - Convert IDENTIFY DEVICE page into string |
| * @id: IDENTIFY DEVICE results we will examine |
| * @s: string into which data is output |
| * @ofs: offset into identify device page |
| * @len: length of string to return. must be an even number. |
| * |
| * The strings in the IDENTIFY DEVICE page are broken up into |
| * 16-bit chunks. Run through the string, and output each |
| * 8-bit chunk linearly, regardless of platform. |
| * |
| * LOCKING: |
| * caller. |
| */ |
| |
| void ata_dev_id_string(const u16 *id, unsigned char *s, |
| unsigned int ofs, unsigned int len) |
| { |
| unsigned int c; |
| |
| while (len > 0) { |
| c = id[ofs] >> 8; |
| *s = c; |
| s++; |
| |
| c = id[ofs] & 0xff; |
| *s = c; |
| s++; |
| |
| ofs++; |
| len -= 2; |
| } |
| } |
| |
| |
| /** |
| * ata_noop_dev_select - Select device 0/1 on ATA bus |
| * @ap: ATA channel to manipulate |
| * @device: ATA device (numbered from zero) to select |
| * |
| * This function performs no actual function. |
| * |
| * May be used as the dev_select() entry in ata_port_operations. |
| * |
| * LOCKING: |
| * caller. |
| */ |
| void ata_noop_dev_select (struct ata_port *ap, unsigned int device) |
| { |
| } |
| |
| |
| /** |
| * ata_std_dev_select - Select device 0/1 on ATA bus |
| * @ap: ATA channel to manipulate |
| * @device: ATA device (numbered from zero) to select |
| * |
| * Use the method defined in the ATA specification to |
| * make either device 0, or device 1, active on the |
| * ATA channel. Works with both PIO and MMIO. |
| * |
| * May be used as the dev_select() entry in ata_port_operations. |
| * |
| * LOCKING: |
| * caller. |
| */ |
| |
| void ata_std_dev_select (struct ata_port *ap, unsigned int device) |
| { |
| u8 tmp; |
| |
| if (device == 0) |
| tmp = ATA_DEVICE_OBS; |
| else |
| tmp = ATA_DEVICE_OBS | ATA_DEV1; |
| |
| if (ap->flags & ATA_FLAG_MMIO) { |
| writeb(tmp, (void __iomem *) ap->ioaddr.device_addr); |
| } else { |
| outb(tmp, ap->ioaddr.device_addr); |
| } |
| ata_pause(ap); /* needed; also flushes, for mmio */ |
| } |
| |
| /** |
| * ata_dev_select - Select device 0/1 on ATA bus |
| * @ap: ATA channel to manipulate |
| * @device: ATA device (numbered from zero) to select |
| * @wait: non-zero to wait for Status register BSY bit to clear |
| * @can_sleep: non-zero if context allows sleeping |
| * |
| * Use the method defined in the ATA specification to |
| * make either device 0, or device 1, active on the |
| * ATA channel. |
| * |
| * This is a high-level version of ata_std_dev_select(), |
| * which additionally provides the services of inserting |
| * the proper pauses and status polling, where needed. |
| * |
| * LOCKING: |
| * caller. |
| */ |
| |
| void ata_dev_select(struct ata_port *ap, unsigned int device, |
| unsigned int wait, unsigned int can_sleep) |
| { |
| VPRINTK("ENTER, ata%u: device %u, wait %u\n", |
| ap->id, device, wait); |
| |
| if (wait) |
| ata_wait_idle(ap); |
| |
| ap->ops->dev_select(ap, device); |
| |
| if (wait) { |
| if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI) |
| msleep(150); |
| ata_wait_idle(ap); |
| } |
| } |
| |
| /** |
| * ata_dump_id - IDENTIFY DEVICE info debugging output |
| * @dev: Device whose IDENTIFY DEVICE page we will dump |
| * |
| * Dump selected 16-bit words from a detected device's |
| * IDENTIFY PAGE page. |
| * |
| * LOCKING: |
| * caller. |
| */ |
| |
| static inline void ata_dump_id(const struct ata_device *dev) |
| { |
| DPRINTK("49==0x%04x " |
| "53==0x%04x " |
| "63==0x%04x " |
| "64==0x%04x " |
| "75==0x%04x \n", |
| dev->id[49], |
| dev->id[53], |
| dev->id[63], |
| dev->id[64], |
| dev->id[75]); |
| DPRINTK("80==0x%04x " |
| "81==0x%04x " |
| "82==0x%04x " |
| "83==0x%04x " |
| "84==0x%04x \n", |
| dev->id[80], |
| dev->id[81], |
| dev->id[82], |
| dev->id[83], |
| dev->id[84]); |
| DPRINTK("88==0x%04x " |
| "93==0x%04x\n", |
| dev->id[88], |
| dev->id[93]); |
| } |
| |
| /* |
| * Compute the PIO modes available for this device. This is not as |
| * trivial as it seems if we must consider early devices correctly. |
| * |
| * FIXME: pre IDE drive timing (do we care ?). |
| */ |
| |
| static unsigned int ata_pio_modes(const struct ata_device *adev) |
| { |
| u16 modes; |
| |
| /* Usual case. Word 53 indicates word 88 is valid */ |
| if (adev->id[ATA_ID_FIELD_VALID] & (1 << 2)) { |
| modes = adev->id[ATA_ID_PIO_MODES] & 0x03; |
| modes <<= 3; |
| modes |= 0x7; |
| return modes; |
| } |
| |
| /* If word 88 isn't valid then Word 51 holds the PIO timing number |
| for the maximum. Turn it into a mask and return it */ |
| modes = (2 << (adev->id[ATA_ID_OLD_PIO_MODES] & 0xFF)) - 1 ; |
| return modes; |
| } |
| |
| static int ata_qc_wait_err(struct ata_queued_cmd *qc, |
| struct completion *wait) |
| { |
| int rc = 0; |
| |
| if (wait_for_completion_timeout(wait, 30 * HZ) < 1) { |
| /* timeout handling */ |
| unsigned int err_mask = ac_err_mask(ata_chk_status(qc->ap)); |
| |
| if (!err_mask) { |
| printk(KERN_WARNING "ata%u: slow completion (cmd %x)\n", |
| qc->ap->id, qc->tf.command); |
| } else { |
| printk(KERN_WARNING "ata%u: qc timeout (cmd %x)\n", |
| qc->ap->id, qc->tf.command); |
| rc = -EIO; |
| } |
| |
| ata_qc_complete(qc, err_mask); |
| } |
| |
| return rc; |
| } |
| |
| /** |
| * ata_dev_identify - obtain IDENTIFY x DEVICE page |
| * @ap: port on which device we wish to probe resides |
| * @device: device bus address, starting at zero |
| * |
| * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE |
| * command, and read back the 512-byte device information page. |
| * The device information page is fed to us via the standard |
| * PIO-IN protocol, but we hand-code it here. (TODO: investigate |
| * using standard PIO-IN paths) |
| * |
| * After reading the device information page, we use several |
| * bits of information from it to initialize data structures |
| * that will be used during the lifetime of the ata_device. |
| * Other data from the info page is used to disqualify certain |
| * older ATA devices we do not wish to support. |
| * |
| * LOCKING: |
| * Inherited from caller. Some functions called by this function |
| * obtain the host_set lock. |
| */ |
| |
| static void ata_dev_identify(struct ata_port *ap, unsigned int device) |
| { |
| struct ata_device *dev = &ap->device[device]; |
| unsigned int major_version; |
| u16 tmp; |
| unsigned long xfer_modes; |
| unsigned int using_edd; |
| DECLARE_COMPLETION(wait); |
| struct ata_queued_cmd *qc; |
| unsigned long flags; |
| int rc; |
| |
| if (!ata_dev_present(dev)) { |
| DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n", |
| ap->id, device); |
| return; |
| } |
| |
| if (ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET)) |
| using_edd = 0; |
| else |
| using_edd = 1; |
| |
| DPRINTK("ENTER, host %u, dev %u\n", ap->id, device); |
| |
| assert (dev->class == ATA_DEV_ATA || dev->class == ATA_DEV_ATAPI || |
| dev->class == ATA_DEV_NONE); |
| |
| ata_dev_select(ap, device, 1, 1); /* select device 0/1 */ |
| |
| qc = ata_qc_new_init(ap, dev); |
| BUG_ON(qc == NULL); |
| |
| ata_sg_init_one(qc, dev->id, sizeof(dev->id)); |
| qc->dma_dir = DMA_FROM_DEVICE; |
| qc->tf.protocol = ATA_PROT_PIO; |
| qc->nsect = 1; |
| |
| retry: |
| if (dev->class == ATA_DEV_ATA) { |
| qc->tf.command = ATA_CMD_ID_ATA; |
| DPRINTK("do ATA identify\n"); |
| } else { |
| qc->tf.command = ATA_CMD_ID_ATAPI; |
| DPRINTK("do ATAPI identify\n"); |
| } |
| |
| qc->waiting = &wait; |
| qc->complete_fn = ata_qc_complete_noop; |
| |
| spin_lock_irqsave(&ap->host_set->lock, flags); |
| rc = ata_qc_issue(qc); |
| spin_unlock_irqrestore(&ap->host_set->lock, flags); |
| |
| if (rc) |
| goto err_out; |
| else |
| ata_qc_wait_err(qc, &wait); |
| |
| spin_lock_irqsave(&ap->host_set->lock, flags); |
| ap->ops->tf_read(ap, &qc->tf); |
| spin_unlock_irqrestore(&ap->host_set->lock, flags); |
| |
| if (qc->tf.command & ATA_ERR) { |
| /* |
| * arg! EDD works for all test cases, but seems to return |
| * the ATA signature for some ATAPI devices. Until the |
| * reason for this is found and fixed, we fix up the mess |
| * here. If IDENTIFY DEVICE returns command aborted |
| * (as ATAPI devices do), then we issue an |
| * IDENTIFY PACKET DEVICE. |
| * |
| * ATA software reset (SRST, the default) does not appear |
| * to have this problem. |
| */ |
| if ((using_edd) && (dev->class == ATA_DEV_ATA)) { |
| u8 err = qc->tf.feature; |
| if (err & ATA_ABORTED) { |
| dev->class = ATA_DEV_ATAPI; |
| qc->cursg = 0; |
| qc->cursg_ofs = 0; |
| qc->cursect = 0; |
| qc->nsect = 1; |
| goto retry; |
| } |
| } |
| goto err_out; |
| } |
| |
| swap_buf_le16(dev->id, ATA_ID_WORDS); |
| |
| /* print device capabilities */ |
| printk(KERN_DEBUG "ata%u: dev %u cfg " |
| "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n", |
| ap->id, device, dev->id[49], |
| dev->id[82], dev->id[83], dev->id[84], |
| dev->id[85], dev->id[86], dev->id[87], |
| dev->id[88]); |
| |
| /* |
| * common ATA, ATAPI feature tests |
| */ |
| |
| /* we require DMA support (bits 8 of word 49) */ |
| if (!ata_id_has_dma(dev->id)) { |
| printk(KERN_DEBUG "ata%u: no dma\n", ap->id); |
| goto err_out_nosup; |
| } |
| |
| /* quick-n-dirty find max transfer mode; for printk only */ |
| xfer_modes = dev->id[ATA_ID_UDMA_MODES]; |
| if (!xfer_modes) |
| xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA; |
| if (!xfer_modes) |
| xfer_modes = ata_pio_modes(dev); |
| |
| ata_dump_id(dev); |
| |
| /* ATA-specific feature tests */ |
| if (dev->class == ATA_DEV_ATA) { |
| if (!ata_id_is_ata(dev->id)) /* sanity check */ |
| goto err_out_nosup; |
| |
| /* get major version */ |
| tmp = dev->id[ATA_ID_MAJOR_VER]; |
| for (major_version = 14; major_version >= 1; major_version--) |
| if (tmp & (1 << major_version)) |
| break; |
| |
| /* |
| * The exact sequence expected by certain pre-ATA4 drives is: |
| * SRST RESET |
| * IDENTIFY |
| * INITIALIZE DEVICE PARAMETERS |
| * anything else.. |
| * Some drives were very specific about that exact sequence. |
| */ |
| if (major_version < 4 || (!ata_id_has_lba(dev->id))) { |
| ata_dev_init_params(ap, dev); |
| |
| /* current CHS translation info (id[53-58]) might be |
| * changed. reread the identify device info. |
| */ |
| ata_dev_reread_id(ap, dev); |
| } |
| |
| if (ata_id_has_lba(dev->id)) { |
| dev->flags |= ATA_DFLAG_LBA; |
| |
| if (ata_id_has_lba48(dev->id)) { |
| dev->flags |= ATA_DFLAG_LBA48; |
| dev->n_sectors = ata_id_u64(dev->id, 100); |
| } else { |
| dev->n_sectors = ata_id_u32(dev->id, 60); |
| } |
| |
| /* print device info to dmesg */ |
| printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n", |
| ap->id, device, |
| major_version, |
| ata_mode_string(xfer_modes), |
| (unsigned long long)dev->n_sectors, |
| dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA"); |
| } else { |
| /* CHS */ |
| |
| /* Default translation */ |
| dev->cylinders = dev->id[1]; |
| dev->heads = dev->id[3]; |
| dev->sectors = dev->id[6]; |
| dev->n_sectors = dev->cylinders * dev->heads * dev->sectors; |
| |
| if (ata_id_current_chs_valid(dev->id)) { |
| /* Current CHS translation is valid. */ |
| dev->cylinders = dev->id[54]; |
| dev->heads = dev->id[55]; |
| dev->sectors = dev->id[56]; |
| |
| dev->n_sectors = ata_id_u32(dev->id, 57); |
| } |
| |
| /* print device info to dmesg */ |
| printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n", |
| ap->id, device, |
| major_version, |
| ata_mode_string(xfer_modes), |
| (unsigned long long)dev->n_sectors, |
| (int)dev->cylinders, (int)dev->heads, (int)dev->sectors); |
| |
| } |
| |
| ap->host->max_cmd_len = 16; |
| } |
| |
| /* ATAPI-specific feature tests */ |
| else if (dev->class == ATA_DEV_ATAPI) { |
| if (ata_id_is_ata(dev->id)) /* sanity check */ |
| goto err_out_nosup; |
| |
| rc = atapi_cdb_len(dev->id); |
| if ((rc < 12) || (rc > ATAPI_CDB_LEN)) { |
| printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id); |
| goto err_out_nosup; |
| } |
| ap->cdb_len = (unsigned int) rc; |
| ap->host->max_cmd_len = (unsigned char) ap->cdb_len; |
| |
| /* print device info to dmesg */ |
| printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n", |
| ap->id, device, |
| ata_mode_string(xfer_modes)); |
| } |
| |
| DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap)); |
| return; |
| |
| err_out_nosup: |
| printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n", |
| ap->id, device); |
| err_out: |
| dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */ |
| DPRINTK("EXIT, err\n"); |
| } |
| |
| |
| static inline u8 ata_dev_knobble(const struct ata_port *ap) |
| { |
| return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ap->device->id))); |
| } |
| |
| /** |
| * ata_dev_config - Run device specific handlers and check for |
| * SATA->PATA bridges |
| * @ap: Bus |
| * @i: Device |
| * |
| * LOCKING: |
| */ |
| |
| void ata_dev_config(struct ata_port *ap, unsigned int i) |
| { |
| /* limit bridge transfers to udma5, 200 sectors */ |
| if (ata_dev_knobble(ap)) { |
| printk(KERN_INFO "ata%u(%u): applying bridge limits\n", |
| ap->id, ap->device->devno); |
| ap->udma_mask &= ATA_UDMA5; |
| ap->host->max_sectors = ATA_MAX_SECTORS; |
| ap->host->hostt->max_sectors = ATA_MAX_SECTORS; |
| ap->device->flags |= ATA_DFLAG_LOCK_SECTORS; |
| } |
| |
| if (ap->ops->dev_config) |
| ap->ops->dev_config(ap, &ap->device[i]); |
| } |
| |
| /** |
| * ata_bus_probe - Reset and probe ATA bus |
| * @ap: Bus to probe |
| * |
| * Master ATA bus probing function. Initiates a hardware-dependent |
| * bus reset, then attempts to identify any devices found on |
| * the bus. |
| * |
| * LOCKING: |
| * PCI/etc. bus probe sem. |
| * |
| * RETURNS: |
| * Zero on success, non-zero on error. |
| */ |
| |
| static int ata_bus_probe(struct ata_port *ap) |
| { |
| unsigned int i, found = 0; |
| |
| ap->ops->phy_reset(ap); |
| if (ap->flags & ATA_FLAG_PORT_DISABLED) |
| goto err_out; |
| |
| for (i = 0; i < ATA_MAX_DEVICES; i++) { |
| ata_dev_identify(ap, i); |
| if (ata_dev_present(&ap->device[i])) { |
| found = 1; |
| ata_dev_config(ap,i); |
| } |
| } |
| |
| if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED)) |
| goto err_out_disable; |
| |
| ata_set_mode(ap); |
| if (ap->flags & ATA_FLAG_PORT_DISABLED) |
| goto err_out_disable; |
| |
| return 0; |
| |
| err_out_disable: |
| ap->ops->port_disable(ap); |
| err_out: |
| return -1; |
| } |
| |
| /** |
| * ata_port_probe - Mark port as enabled |
| * @ap: Port for which we indicate enablement |
| * |
| * Modify @ap data structure such that the system |
| * thinks that the entire port is enabled. |
| * |
| * LOCKING: host_set lock, or some other form of |
| * serialization. |
| */ |
| |
| void ata_port_probe(struct ata_port *ap) |
| { |
| ap->flags &= ~ATA_FLAG_PORT_DISABLED; |
| } |
| |
| /** |
| * __sata_phy_reset - Wake/reset a low-level SATA PHY |
| * @ap: SATA port associated with target SATA PHY. |
| * |
| * This function issues commands to standard SATA Sxxx |
| * PHY registers, to wake up the phy (and device), and |
| * clear any reset condition. |
| * |
| * LOCKING: |
| * PCI/etc. bus probe sem. |
| * |
| */ |
| void __sata_phy_reset(struct ata_port *ap) |
| { |
| u32 sstatus; |
| unsigned long timeout = jiffies + (HZ * 5); |
| |
| if (ap->flags & ATA_FLAG_SATA_RESET) { |
| /* issue phy wake/reset */ |
| scr_write_flush(ap, SCR_CONTROL, 0x301); |
| /* Couldn't find anything in SATA I/II specs, but |
| * AHCI-1.1 10.4.2 says at least 1 ms. */ |
| mdelay(1); |
| } |
| scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */ |
| |
| /* wait for phy to become ready, if necessary */ |
| do { |
| msleep(200); |
| sstatus = scr_read(ap, SCR_STATUS); |
| if ((sstatus & 0xf) != 1) |
| break; |
| } while (time_before(jiffies, timeout)); |
| |
| /* TODO: phy layer with polling, timeouts, etc. */ |
| if (sata_dev_present(ap)) |
| ata_port_probe(ap); |
| else { |
| sstatus = scr_read(ap, SCR_STATUS); |
| printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n", |
| ap->id, sstatus); |
| ata_port_disable(ap); |
| } |
| |
| if (ap->flags & ATA_FLAG_PORT_DISABLED) |
| return; |
| |
| if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) { |
| ata_port_disable(ap); |
| return; |
| } |
| |
| ap->cbl = ATA_CBL_SATA; |
| } |
| |
| /** |
| * sata_phy_reset - Reset SATA bus. |
| * @ap: SATA port associated with target SATA PHY. |
| * |
| * This function resets the SATA bus, and then probes |
| * the bus for devices. |
| * |
| * LOCKING: |
| * PCI/etc. bus probe sem. |
| * |
| */ |
| void sata_phy_reset(struct ata_port *ap) |
| { |
| __sata_phy_reset(ap); |
| if (ap->flags & ATA_FLAG_PORT_DISABLED) |
| return; |
| ata_bus_reset(ap); |
| } |
| |
| /** |
| * ata_port_disable - Disable port. |
| * @ap: Port to be disabled. |
| * |
| * Modify @ap data structure such that the system |
| * thinks that the entire port is disabled, and should |
| * never attempt to probe or communicate with devices |
| * on this port. |
| * |
| * LOCKING: host_set lock, or some other form of |
| * serialization. |
| */ |
| |
| void ata_port_disable(struct ata_port *ap) |
| { |
| ap->device[0].class = ATA_DEV_NONE; |
| ap->device[1].class = ATA_DEV_NONE; |
| ap->flags |= ATA_FLAG_PORT_DISABLED; |
| } |
| |
| /* |
| * This mode timing computation functionality is ported over from |
| * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik |
| */ |
| /* |
| * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds). |
| * These were taken from ATA/ATAPI-6 standard, rev 0a, except |
| * for PIO 5, which is a nonstandard extension and UDMA6, which |
| * is currently supported only by Maxtor drives. |
| */ |
| |
| static const struct ata_timing ata_timing[] = { |
| |
| { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 }, |
| { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 }, |
| { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 }, |
| { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 }, |
| |
| { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 }, |
| { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 }, |
| { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 }, |
| |
| /* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */ |
| |
| { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 }, |
| { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 }, |
| { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 }, |
| |
| { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 }, |
| { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 }, |
| { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 }, |
| |
| /* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */ |
| { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 }, |
| { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 }, |
| |
| { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 }, |
| { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 }, |
| { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 }, |
| |
| /* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */ |
| |
| { 0xFF } |
| }; |
| |
| #define ENOUGH(v,unit) (((v)-1)/(unit)+1) |
| #define EZ(v,unit) ((v)?ENOUGH(v,unit):0) |
| |
| static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT) |
| { |
| q->setup = EZ(t->setup * 1000, T); |
| q->act8b = EZ(t->act8b * 1000, T); |
| q->rec8b = EZ(t->rec8b * 1000, T); |
| q->cyc8b = EZ(t->cyc8b * 1000, T); |
| q->active = EZ(t->active * 1000, T); |
| q->recover = EZ(t->recover * 1000, T); |
| q->cycle = EZ(t->cycle * 1000, T); |
| q->udma = EZ(t->udma * 1000, UT); |
| } |
| |
| void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b, |
| struct ata_timing *m, unsigned int what) |
| { |
| if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup); |
| if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b); |
| if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b); |
| if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b); |
| if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active); |
| if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover); |
| if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle); |
| if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma); |
| } |
| |
| static const struct ata_timing* ata_timing_find_mode(unsigned short speed) |
| { |
| const struct ata_timing *t; |
| |
| for (t = ata_timing; t->mode != speed; t++) |
| if (t->mode == 0xFF) |
| return NULL; |
| return t; |
| } |
| |
| int ata_timing_compute(struct ata_device *adev, unsigned short speed, |
| struct ata_timing *t, int T, int UT) |
| { |
| const struct ata_timing *s; |
| struct ata_timing p; |
| |
| /* |
| * Find the mode. |
| */ |
| |
| if (!(s = ata_timing_find_mode(speed))) |
| return -EINVAL; |
| |
| memcpy(t, s, sizeof(*s)); |
| |
| /* |
| * If the drive is an EIDE drive, it can tell us it needs extended |
| * PIO/MW_DMA cycle timing. |
| */ |
| |
| if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */ |
| memset(&p, 0, sizeof(p)); |
| if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) { |
| if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO]; |
| else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY]; |
| } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) { |
| p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN]; |
| } |
| ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B); |
| } |
| |
| /* |
| * Convert the timing to bus clock counts. |
| */ |
| |
| ata_timing_quantize(t, t, T, UT); |
| |
| /* |
| * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T |
| * and some other commands. We have to ensure that the DMA cycle timing is |
| * slower/equal than the fastest PIO timing. |
| */ |
| |
| if (speed > XFER_PIO_4) { |
| ata_timing_compute(adev, adev->pio_mode, &p, T, UT); |
| ata_timing_merge(&p, t, t, ATA_TIMING_ALL); |
| } |
| |
| /* |
| * Lenghten active & recovery time so that cycle time is correct. |
| */ |
| |
| if (t->act8b + t->rec8b < t->cyc8b) { |
| t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2; |
| t->rec8b = t->cyc8b - t->act8b; |
| } |
| |
| if (t->active + t->recover < t->cycle) { |
| t->active += (t->cycle - (t->active + t->recover)) / 2; |
| t->recover = t->cycle - t->active; |
| } |
| |
| return 0; |
| } |
| |
| static const struct { |
| unsigned int shift; |
| u8 base; |
| } xfer_mode_classes[] = { |
| { ATA_SHIFT_UDMA, XFER_UDMA_0 }, |
| { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 }, |
| { ATA_SHIFT_PIO, XFER_PIO_0 }, |
| }; |
| |
| static inline u8 base_from_shift(unsigned int shift) |
| { |
| int i; |
| |
| for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) |
| if (xfer_mode_classes[i].shift == shift) |
| return xfer_mode_classes[i].base; |
| |
| return 0xff; |
| } |
| |
| static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev) |
| { |
| int ofs, idx; |
| u8 base; |
| |
| if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED)) |
| return; |
| |
| if (dev->xfer_shift == ATA_SHIFT_PIO) |
| dev->flags |= ATA_DFLAG_PIO; |
| |
| ata_dev_set_xfermode(ap, dev); |
| |
| base = base_from_shift(dev->xfer_shift); |
| ofs = dev->xfer_mode - base; |
| idx = ofs + dev->xfer_shift; |
| WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str)); |
| |
| DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n", |
| idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs); |
| |
| printk(KERN_INFO "ata%u: dev %u configured for %s\n", |
| ap->id, dev->devno, xfer_mode_str[idx]); |
| } |
| |
| static int ata_host_set_pio(struct ata_port *ap) |
| { |
| unsigned int mask; |
| int x, i; |
| u8 base, xfer_mode; |
| |
| mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO); |
| x = fgb(mask); |
| if (x < 0) { |
| printk(KERN_WARNING "ata%u: no PIO support\n", ap->id); |
| return -1; |
| } |
| |
| base = base_from_shift(ATA_SHIFT_PIO); |
| xfer_mode = base + x; |
| |
| DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n", |
| (int)base, (int)xfer_mode, mask, x); |
| |
| for (i = 0; i < ATA_MAX_DEVICES; i++) { |
| struct ata_device *dev = &ap->device[i]; |
| if (ata_dev_present(dev)) { |
| dev->pio_mode = xfer_mode; |
| dev->xfer_mode = xfer_mode; |
| dev->xfer_shift = ATA_SHIFT_PIO; |
| if (ap->ops->set_piomode) |
| ap->ops->set_piomode(ap, dev); |
| } |
| } |
| |
| return 0; |
| } |
| |
| static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode, |
| unsigned int xfer_shift) |
| { |
| int i; |
| |
| for (i = 0; i < ATA_MAX_DEVICES; i++) { |
| struct ata_device *dev = &ap->device[i]; |
| if (ata_dev_present(dev)) { |
| dev->dma_mode = xfer_mode; |
| dev->xfer_mode = xfer_mode; |
| dev->xfer_shift = xfer_shift; |
| if (ap->ops->set_dmamode) |
| ap->ops->set_dmamode(ap, dev); |
| } |
| } |
| } |
| |
| /** |
| * ata_set_mode - Program timings and issue SET FEATURES - XFER |
| * @ap: port on which timings will be programmed |
| * |
| * Set ATA device disk transfer mode (PIO3, UDMA6, etc.). |
| * |
| * LOCKING: |
| * PCI/etc. bus probe sem. |
| * |
| */ |
| static void ata_set_mode(struct ata_port *ap) |
| { |
| unsigned int xfer_shift; |
| u8 xfer_mode; |
| int rc; |
| |
| /* step 1: always set host PIO timings */ |
| rc = ata_host_set_pio(ap); |
| if (rc) |
| goto err_out; |
| |
| /* step 2: choose the best data xfer mode */ |
| xfer_mode = xfer_shift = 0; |
| rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift); |
| if (rc) |
| goto err_out; |
| |
| /* step 3: if that xfer mode isn't PIO, set host DMA timings */ |
| if (xfer_shift != ATA_SHIFT_PIO) |
| ata_host_set_dma(ap, xfer_mode, xfer_shift); |
| |
| /* step 4: update devices' xfer mode */ |
| ata_dev_set_mode(ap, &ap->device[0]); |
| ata_dev_set_mode(ap, &ap->device[1]); |
| |
| if (ap->flags & ATA_FLAG_PORT_DISABLED) |
| return; |
| |
| if (ap->ops->post_set_mode) |
| ap->ops->post_set_mode(ap); |
| |
| return; |
| |
| err_out: |
| ata_port_disable(ap); |
| } |
| |
| /** |
| * ata_busy_sleep - sleep until BSY clears, or timeout |
| * @ap: port containing status register to be polled |
| * @tmout_pat: impatience timeout |
| * @tmout: overall timeout |
| * |
| * Sleep until ATA Status register bit BSY clears, |
| * or a timeout occurs. |
| * |
| * LOCKING: None. |
| * |
| */ |
| |
| static unsigned int ata_busy_sleep (struct ata_port *ap, |
| unsigned long tmout_pat, |
| unsigned long tmout) |
| { |
| unsigned long timer_start, timeout; |
| u8 status; |
| |
| status = ata_busy_wait(ap, ATA_BUSY, 300); |
| timer_start = jiffies; |
| timeout = timer_start + tmout_pat; |
| while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) { |
| msleep(50); |
| status = ata_busy_wait(ap, ATA_BUSY, 3); |
| } |
| |
| if (status & ATA_BUSY) |
| printk(KERN_WARNING "ata%u is slow to respond, " |
| "please be patient\n", ap->id); |
| |
| timeout = timer_start + tmout; |
| while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) { |
| msleep(50); |
| status = ata_chk_status(ap); |
| } |
| |
| if (status & ATA_BUSY) { |
| printk(KERN_ERR "ata%u failed to respond (%lu secs)\n", |
| ap->id, tmout / HZ); |
| return 1; |
| } |
| |
| return 0; |
| } |
| |
| static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask) |
| { |
| struct ata_ioports *ioaddr = &ap->ioaddr; |
| unsigned int dev0 = devmask & (1 << 0); |
| unsigned int dev1 = devmask & (1 << 1); |
| unsigned long timeout; |
| |
| /* if device 0 was found in ata_devchk, wait for its |
| * BSY bit to clear |
| */ |
| if (dev0) |
| ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT); |
| |
| /* if device 1 was found in ata_devchk, wait for |
| * register access, then wait for BSY to clear |
| */ |
| timeout = jiffies + ATA_TMOUT_BOOT; |
| while (dev1) { |
| u8 nsect, lbal; |
| |
| ap->ops->dev_select(ap, 1); |
| if (ap->flags & ATA_FLAG_MMIO) { |
| nsect = readb((void __iomem *) ioaddr->nsect_addr); |
| lbal = readb((void __iomem *) ioaddr->lbal_addr); |
| } else { |
| nsect = inb(ioaddr->nsect_addr); |
| lbal = inb(ioaddr->lbal_addr); |
| } |
| if ((nsect == 1) && (lbal == 1)) |
| break; |
| if (time_after(jiffies, timeout)) { |
| dev1 = 0; |
| break; |
| } |
| msleep(50); /* give drive a breather */ |
| } |
| if (dev1) |
| ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT); |
| |
| /* is all this really necessary? */ |
| ap->ops->dev_select(ap, 0); |
| if (dev1) |
| ap->ops->dev_select(ap, 1); |
| if (dev0) |
| ap->ops->dev_select(ap, 0); |
| } |
| |
| /** |
| * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command. |
| * @ap: Port to reset and probe |
| * |
| * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and |
| * probe the bus. Not often used these days. |
| * |
| * LOCKING: |
| * PCI/etc. bus probe sem. |
| * Obtains host_set lock. |
| * |
| */ |
| |
| static unsigned int ata_bus_edd(struct ata_port *ap) |
| { |
| struct ata_taskfile tf; |
| unsigned long flags; |
| |
| /* set up execute-device-diag (bus reset) taskfile */ |
| /* also, take interrupts to a known state (disabled) */ |
| DPRINTK("execute-device-diag\n"); |
| ata_tf_init(ap, &tf, 0); |
| tf.ctl |= ATA_NIEN; |
| tf.command = ATA_CMD_EDD; |
| tf.protocol = ATA_PROT_NODATA; |
| |
| /* do bus reset */ |
| spin_lock_irqsave(&ap->host_set->lock, flags); |
| ata_tf_to_host(ap, &tf); |
| spin_unlock_irqrestore(&ap->host_set->lock, flags); |
| |
| /* spec says at least 2ms. but who knows with those |
| * crazy ATAPI devices... |
| */ |
| msleep(150); |
| |
| return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT); |
| } |
| |
| static unsigned int ata_bus_softreset(struct ata_port *ap, |
| unsigned int devmask) |
| { |
| struct ata_ioports *ioaddr = &ap->ioaddr; |
| |
| DPRINTK("ata%u: bus reset via SRST\n", ap->id); |
| |
| /* software reset. causes dev0 to be selected */ |
| if (ap->flags & ATA_FLAG_MMIO) { |
| writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr); |
| udelay(20); /* FIXME: flush */ |
| writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr); |
| udelay(20); /* FIXME: flush */ |
| writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr); |
| } else { |
| outb(ap->ctl, ioaddr->ctl_addr); |
| udelay(10); |
| outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr); |
| udelay(10); |
| outb(ap->ctl, ioaddr->ctl_addr); |
| } |
| |
| /* spec mandates ">= 2ms" before checking status. |
| * We wait 150ms, because that was the magic delay used for |
| * ATAPI devices in Hale Landis's ATADRVR, for the period of time |
| * between when the ATA command register is written, and then |
| * status is checked. Because waiting for "a while" before |
| * checking status is fine, post SRST, we perform this magic |
| * delay here as well. |
| */ |
| msleep(150); |
| |
| ata_bus_post_reset(ap, devmask); |
| |
| return 0; |
| } |
| |
| /** |
| * ata_bus_reset - reset host port and associated ATA channel |
| * @ap: port to reset |
| * |
| * This is typically the first time we actually start issuing |
| * commands to the ATA channel. We wait for BSY to clear, then |
| * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its |
| * result. Determine what devices, if any, are on the channel |
| * by looking at the device 0/1 error register. Look at the signature |
| * stored in each device's taskfile registers, to determine if |
| * the device is ATA or ATAPI. |
| * |
| * LOCKING: |
| * PCI/etc. bus probe sem. |
| * Obtains host_set lock. |
| * |
| * SIDE EFFECTS: |
| * Sets ATA_FLAG_PORT_DISABLED if bus reset fails. |
| */ |
| |
| void ata_bus_reset(struct ata_port *ap) |
| { |
| struct ata_ioports *ioaddr = &ap->ioaddr; |
| unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; |
| u8 err; |
| unsigned int dev0, dev1 = 0, rc = 0, devmask = 0; |
| |
| DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no); |
| |
| /* determine if device 0/1 are present */ |
| if (ap->flags & ATA_FLAG_SATA_RESET) |
| dev0 = 1; |
| else { |
| dev0 = ata_devchk(ap, 0); |
| if (slave_possible) |
| dev1 = ata_devchk(ap, 1); |
| } |
| |
| if (dev0) |
| devmask |= (1 << 0); |
| if (dev1) |
| devmask |= (1 << 1); |
| |
| /* select device 0 again */ |
| ap->ops->dev_select(ap, 0); |
| |
| /* issue bus reset */ |
| if (ap->flags & ATA_FLAG_SRST) |
| rc = ata_bus_softreset(ap, devmask); |
| else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) { |
| /* set up device control */ |
| if (ap->flags & ATA_FLAG_MMIO) |
| writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr); |
| else |
| outb(ap->ctl, ioaddr->ctl_addr); |
| rc = ata_bus_edd(ap); |
| } |
| |
| if (rc) |
| goto err_out; |
| |
| /* |
| * determine by signature whether we have ATA or ATAPI devices |
| */ |
| err = ata_dev_try_classify(ap, 0); |
| if ((slave_possible) && (err != 0x81)) |
| ata_dev_try_classify(ap, 1); |
| |
| /* re-enable interrupts */ |
| if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */ |
| ata_irq_on(ap); |
| |
| /* is double-select really necessary? */ |
| if (ap->device[1].class != ATA_DEV_NONE) |
| ap->ops->dev_select(ap, 1); |
| if (ap->device[0].class != ATA_DEV_NONE) |
| ap->ops->dev_select(ap, 0); |
| |
| /* if no devices were detected, disable this port */ |
| if ((ap->device[0].class == ATA_DEV_NONE) && |
| (ap->device[1].class == ATA_DEV_NONE)) |
| goto err_out; |
| |
| if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) { |
| /* set up device control for ATA_FLAG_SATA_RESET */ |
| if (ap->flags & ATA_FLAG_MMIO) |
| writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr); |
| else |
| outb(ap->ctl, ioaddr->ctl_addr); |
| } |
| |
| DPRINTK("EXIT\n"); |
| return; |
| |
| err_out: |
| printk(KERN_ERR "ata%u: disabling port\n", ap->id); |
| ap->ops->port_disable(ap); |
| |
| DPRINTK("EXIT\n"); |
| } |
| |
| static void ata_pr_blacklisted(const struct ata_port *ap, |
| const struct ata_device *dev) |
| { |
| printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n", |
| ap->id, dev->devno); |
| } |
| |
| static const char * ata_dma_blacklist [] = { |
| "WDC AC11000H", |
| "WDC AC22100H", |
| "WDC AC32500H", |
| "WDC AC33100H", |
| "WDC AC31600H", |
| "WDC AC32100H", |
| "WDC AC23200L", |
| "Compaq CRD-8241B", |
| "CRD-8400B", |
| "CRD-8480B", |
| "CRD-8482B", |
| "CRD-84", |
| "SanDisk SDP3B", |
| "SanDisk SDP3B-64", |
| "SANYO CD-ROM CRD", |
| "HITACHI CDR-8", |
| "HITACHI CDR-8335", |
| "HITACHI CDR-8435", |
| "Toshiba CD-ROM XM-6202B", |
| "TOSHIBA CD-ROM XM-1702BC", |
| "CD-532E-A", |
| "E-IDE CD-ROM CR-840", |
| "CD-ROM Drive/F5A", |
| "WPI CDD-820", |
| "SAMSUNG CD-ROM SC-148C", |
| "SAMSUNG CD-ROM SC", |
| "SanDisk SDP3B-64", |
| "ATAPI CD-ROM DRIVE 40X MAXIMUM", |
| "_NEC DV5800A", |
| }; |
| |
| static int ata_dma_blacklisted(const struct ata_device *dev) |
| { |
| unsigned char model_num[40]; |
| char *s; |
| unsigned int len; |
| int i; |
| |
| ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS, |
| sizeof(model_num)); |
| s = &model_num[0]; |
| len = strnlen(s, sizeof(model_num)); |
| |
| /* ATAPI specifies that empty space is blank-filled; remove blanks */ |
| while ((len > 0) && (s[len - 1] == ' ')) { |
| len--; |
| s[len] = 0; |
| } |
| |
| for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++) |
| if (!strncmp(ata_dma_blacklist[i], s, len)) |
| return 1; |
| |
| return 0; |
| } |
| |
| static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift) |
| { |
| const struct ata_device *master, *slave; |
| unsigned int mask; |
| |
| master = &ap->device[0]; |
| slave = &ap->device[1]; |
| |
| assert (ata_dev_present(master) || ata_dev_present(slave)); |
| |
| if (shift == ATA_SHIFT_UDMA) { |
| mask = ap->udma_mask; |
| if (ata_dev_present(master)) { |
| mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff); |
| if (ata_dma_blacklisted(master)) { |
| mask = 0; |
| ata_pr_blacklisted(ap, master); |
| } |
| } |
| if (ata_dev_present(slave)) { |
| mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff); |
| if (ata_dma_blacklisted(slave)) { |
| mask = 0; |
| ata_pr_blacklisted(ap, slave); |
| } |
| } |
| } |
| else if (shift == ATA_SHIFT_MWDMA) { |
| mask = ap->mwdma_mask; |
| if (ata_dev_present(master)) { |
| mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07); |
| if (ata_dma_blacklisted(master)) { |
| mask = 0; |
| ata_pr_blacklisted(ap, master); |
| } |
| } |
| if (ata_dev_present(slave)) { |
| mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07); |
| if (ata_dma_blacklisted(slave)) { |
| mask = 0; |
| ata_pr_blacklisted(ap, slave); |
| } |
| } |
| } |
| else if (shift == ATA_SHIFT_PIO) { |
| mask = ap->pio_mask; |
| if (ata_dev_present(master)) { |
| /* spec doesn't return explicit support for |
| * PIO0-2, so we fake it |
| */ |
| u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03; |
| tmp_mode <<= 3; |
| tmp_mode |= 0x7; |
| mask &= tmp_mode; |
| } |
| if (ata_dev_present(slave)) { |
| /* spec doesn't return explicit support for |
| * PIO0-2, so we fake it |
| */ |
| u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03; |
| tmp_mode <<= 3; |
| tmp_mode |= 0x7; |
| mask &= tmp_mode; |
| } |
| } |
| else { |
| mask = 0xffffffff; /* shut up compiler warning */ |
| BUG(); |
| } |
| |
| return mask; |
| } |
| |
| /* find greatest bit */ |
| static int fgb(u32 bitmap) |
| { |
| unsigned int i; |
| int x = -1; |
| |
| for (i = 0; i < 32; i++) |
| if (bitmap & (1 << i)) |
| x = i; |
| |
| return x; |
| } |
| |
| /** |
| * ata_choose_xfer_mode - attempt to find best transfer mode |
| * @ap: Port for which an xfer mode will be selected |
| * @xfer_mode_out: (output) SET FEATURES - XFER MODE code |
| * @xfer_shift_out: (output) bit shift that selects this mode |
| * |
| * Based on host and device capabilities, determine the |
| * maximum transfer mode that is amenable to all. |
| * |
| * LOCKING: |
| * PCI/etc. bus probe sem. |
| * |
| * RETURNS: |
| * Zero on success, negative on error. |
| */ |
| |
| static int ata_choose_xfer_mode(const struct ata_port *ap, |
| u8 *xfer_mode_out, |
| unsigned int *xfer_shift_out) |
| { |
| unsigned int mask, shift; |
| int x, i; |
| |
| for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) { |
| shift = xfer_mode_classes[i].shift; |
| mask = ata_get_mode_mask(ap, shift); |
| |
| x = fgb(mask); |
| if (x >= 0) { |
| *xfer_mode_out = xfer_mode_classes[i].base + x; |
| *xfer_shift_out = shift; |
| return 0; |
| } |
| } |
| |
| return -1; |
| } |
| |
| /** |
| * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command |
| * @ap: Port associated with device @dev |
| * @dev: Device to which command will be sent |
| * |
| * Issue SET FEATURES - XFER MODE command to device @dev |
| * on port @ap. |
| * |
| * LOCKING: |
| * PCI/etc. bus probe sem. |
| */ |
| |
| static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev) |
| { |
| DECLARE_COMPLETION(wait); |
| struct ata_queued_cmd *qc; |
| int rc; |
| unsigned long flags; |
| |
| /* set up set-features taskfile */ |
| DPRINTK("set features - xfer mode\n"); |
| |
| qc = ata_qc_new_init(ap, dev); |
| BUG_ON(qc == NULL); |
| |
| qc->tf.command = ATA_CMD_SET_FEATURES; |
| qc->tf.feature = SETFEATURES_XFER; |
| qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE; |
| qc->tf.protocol = ATA_PROT_NODATA; |
| qc->tf.nsect = dev->xfer_mode; |
| |
| qc->waiting = &wait; |
| qc->complete_fn = ata_qc_complete_noop; |
| |
| spin_lock_irqsave(&ap->host_set->lock, flags); |
| rc = ata_qc_issue(qc); |
| spin_unlock_irqrestore(&ap->host_set->lock, flags); |
| |
| if (rc) |
| ata_port_disable(ap); |
| else |
| ata_qc_wait_err(qc, &wait); |
| |
| DPRINTK("EXIT\n"); |
| } |
| |
| /** |
| * ata_dev_reread_id - Reread the device identify device info |
| * @ap: port where the device is |
| * @dev: device to reread the identify device info |
| * |
| * LOCKING: |
| */ |
| |
| static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev) |
| { |
| DECLARE_COMPLETION(wait); |
| struct ata_queued_cmd *qc; |
| unsigned long flags; |
| int rc; |
| |
| qc = ata_qc_new_init(ap, dev); |
| BUG_ON(qc == NULL); |
| |
| ata_sg_init_one(qc, dev->id, sizeof(dev->id)); |
| qc->dma_dir = DMA_FROM_DEVICE; |
| |
| if (dev->class == ATA_DEV_ATA) { |
| qc->tf.command = ATA_CMD_ID_ATA; |
| DPRINTK("do ATA identify\n"); |
| } else { |
| qc->tf.command = ATA_CMD_ID_ATAPI; |
| DPRINTK("do ATAPI identify\n"); |
| } |
| |
| qc->tf.flags |= ATA_TFLAG_DEVICE; |
| qc->tf.protocol = ATA_PROT_PIO; |
| qc->nsect = 1; |
| |
| qc->waiting = &wait; |
| qc->complete_fn = ata_qc_complete_noop; |
| |
| spin_lock_irqsave(&ap->host_set->lock, flags); |
| rc = ata_qc_issue(qc); |
| spin_unlock_irqrestore(&ap->host_set->lock, flags); |
| |
| if (rc) |
| goto err_out; |
| |
| ata_qc_wait_err(qc, &wait); |
| |
| swap_buf_le16(dev->id, ATA_ID_WORDS); |
| |
| ata_dump_id(dev); |
| |
| DPRINTK("EXIT\n"); |
| |
| return; |
| err_out: |
| ata_port_disable(ap); |
| } |
| |
| /** |
| * ata_dev_init_params - Issue INIT DEV PARAMS command |
| * @ap: Port associated with device @dev |
| * @dev: Device to which command will be sent |
| * |
| * LOCKING: |
| */ |
| |
| static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev) |
| { |
| DECLARE_COMPLETION(wait); |
| struct ata_queued_cmd *qc; |
| int rc; |
| unsigned long flags; |
| u16 sectors = dev->id[6]; |
| u16 heads = dev->id[3]; |
| |
| /* Number of sectors per track 1-255. Number of heads 1-16 */ |
| if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16) |
| return; |
| |
| /* set up init dev params taskfile */ |
| DPRINTK("init dev params \n"); |
| |
| qc = ata_qc_new_init(ap, dev); |
| BUG_ON(qc == NULL); |
| |
| qc->tf.command = ATA_CMD_INIT_DEV_PARAMS; |
| qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE; |
| qc->tf.protocol = ATA_PROT_NODATA; |
| qc->tf.nsect = sectors; |
| qc->tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */ |
| |
| qc->waiting = &wait; |
| qc->complete_fn = ata_qc_complete_noop; |
| |
| spin_lock_irqsave(&ap->host_set->lock, flags); |
| rc = ata_qc_issue(qc); |
| spin_unlock_irqrestore(&ap->host_set->lock, flags); |
| |
| if (rc) |
| ata_port_disable(ap); |
| else |
| ata_qc_wait_err(qc, &wait); |
| |
| DPRINTK("EXIT\n"); |
| } |
| |
| /** |
| * ata_sg_clean - Unmap DMA memory associated with command |
| * @qc: Command containing DMA memory to be released |
| * |
| * Unmap all mapped DMA memory associated with this command. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| */ |
| |
| static void ata_sg_clean(struct ata_queued_cmd *qc) |
| { |
| struct ata_port *ap = qc->ap; |
| struct scatterlist *sg = qc->__sg; |
| int dir = qc->dma_dir; |
| void *pad_buf = NULL; |
| |
| assert(qc->flags & ATA_QCFLAG_DMAMAP); |
| assert(sg != NULL); |
| |
| if (qc->flags & ATA_QCFLAG_SINGLE) |
| assert(qc->n_elem == 1); |
| |
| VPRINTK("unmapping %u sg elements\n", qc->n_elem); |
| |
| /* if we padded the buffer out to 32-bit bound, and data |
| * xfer direction is from-device, we must copy from the |
| * pad buffer back into the supplied buffer |
| */ |
| if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE)) |
| pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ); |
| |
| if (qc->flags & ATA_QCFLAG_SG) { |
| if (qc->n_elem) |
| dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir); |
| /* restore last sg */ |
| sg[qc->orig_n_elem - 1].length += qc->pad_len; |
| if (pad_buf) { |
| struct scatterlist *psg = &qc->pad_sgent; |
| void *addr = kmap_atomic(psg->page, KM_IRQ0); |
| memcpy(addr + psg->offset, pad_buf, qc->pad_len); |
| kunmap_atomic(psg->page, KM_IRQ0); |
| } |
| } else { |
| if (sg_dma_len(&sg[0]) > 0) |
| dma_unmap_single(ap->host_set->dev, |
| sg_dma_address(&sg[0]), sg_dma_len(&sg[0]), |
| dir); |
| /* restore sg */ |
| sg->length += qc->pad_len; |
| if (pad_buf) |
| memcpy(qc->buf_virt + sg->length - qc->pad_len, |
| pad_buf, qc->pad_len); |
| } |
| |
| qc->flags &= ~ATA_QCFLAG_DMAMAP; |
| qc->__sg = NULL; |
| } |
| |
| /** |
| * ata_fill_sg - Fill PCI IDE PRD table |
| * @qc: Metadata associated with taskfile to be transferred |
| * |
| * Fill PCI IDE PRD (scatter-gather) table with segments |
| * associated with the current disk command. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| * |
| */ |
| static void ata_fill_sg(struct ata_queued_cmd *qc) |
| { |
| struct ata_port *ap = qc->ap; |
| struct scatterlist *sg; |
| unsigned int idx; |
| |
| assert(qc->__sg != NULL); |
| assert(qc->n_elem > 0); |
| |
| idx = 0; |
| ata_for_each_sg(sg, qc) { |
| u32 addr, offset; |
| u32 sg_len, len; |
| |
| /* determine if physical DMA addr spans 64K boundary. |
| * Note h/w doesn't support 64-bit, so we unconditionally |
| * truncate dma_addr_t to u32. |
| */ |
| addr = (u32) sg_dma_address(sg); |
| sg_len = sg_dma_len(sg); |
| |
| while (sg_len) { |
| offset = addr & 0xffff; |
| len = sg_len; |
| if ((offset + sg_len) > 0x10000) |
| len = 0x10000 - offset; |
| |
| ap->prd[idx].addr = cpu_to_le32(addr); |
| ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff); |
| VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); |
| |
| idx++; |
| sg_len -= len; |
| addr += len; |
| } |
| } |
| |
| if (idx) |
| ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); |
| } |
| /** |
| * ata_check_atapi_dma - Check whether ATAPI DMA can be supported |
| * @qc: Metadata associated with taskfile to check |
| * |
| * Allow low-level driver to filter ATA PACKET commands, returning |
| * a status indicating whether or not it is OK to use DMA for the |
| * supplied PACKET command. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| * |
| * RETURNS: 0 when ATAPI DMA can be used |
| * nonzero otherwise |
| */ |
| int ata_check_atapi_dma(struct ata_queued_cmd *qc) |
| { |
| struct ata_port *ap = qc->ap; |
| int rc = 0; /* Assume ATAPI DMA is OK by default */ |
| |
| if (ap->ops->check_atapi_dma) |
| rc = ap->ops->check_atapi_dma(qc); |
| |
| return rc; |
| } |
| /** |
| * ata_qc_prep - Prepare taskfile for submission |
| * @qc: Metadata associated with taskfile to be prepared |
| * |
| * Prepare ATA taskfile for submission. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| */ |
| void ata_qc_prep(struct ata_queued_cmd *qc) |
| { |
| if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
| return; |
| |
| ata_fill_sg(qc); |
| } |
| |
| /** |
| * ata_sg_init_one - Associate command with memory buffer |
| * @qc: Command to be associated |
| * @buf: Memory buffer |
| * @buflen: Length of memory buffer, in bytes. |
| * |
| * Initialize the data-related elements of queued_cmd @qc |
| * to point to a single memory buffer, @buf of byte length @buflen. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| */ |
| |
| void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen) |
| { |
| struct scatterlist *sg; |
| |
| qc->flags |= ATA_QCFLAG_SINGLE; |
| |
| memset(&qc->sgent, 0, sizeof(qc->sgent)); |
| qc->__sg = &qc->sgent; |
| qc->n_elem = 1; |
| qc->orig_n_elem = 1; |
| qc->buf_virt = buf; |
| |
| sg = qc->__sg; |
| sg_init_one(sg, buf, buflen); |
| } |
| |
| /** |
| * ata_sg_init - Associate command with scatter-gather table. |
| * @qc: Command to be associated |
| * @sg: Scatter-gather table. |
| * @n_elem: Number of elements in s/g table. |
| * |
| * Initialize the data-related elements of queued_cmd @qc |
| * to point to a scatter-gather table @sg, containing @n_elem |
| * elements. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| */ |
| |
| void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg, |
| unsigned int n_elem) |
| { |
| qc->flags |= ATA_QCFLAG_SG; |
| qc->__sg = sg; |
| qc->n_elem = n_elem; |
| qc->orig_n_elem = n_elem; |
| } |
| |
| /** |
| * ata_sg_setup_one - DMA-map the memory buffer associated with a command. |
| * @qc: Command with memory buffer to be mapped. |
| * |
| * DMA-map the memory buffer associated with queued_cmd @qc. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| * |
| * RETURNS: |
| * Zero on success, negative on error. |
| */ |
| |
| static int ata_sg_setup_one(struct ata_queued_cmd *qc) |
| { |
| struct ata_port *ap = qc->ap; |
| int dir = qc->dma_dir; |
| struct scatterlist *sg = qc->__sg; |
| dma_addr_t dma_address; |
| |
| /* we must lengthen transfers to end on a 32-bit boundary */ |
| qc->pad_len = sg->length & 3; |
| if (qc->pad_len) { |
| void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ); |
| struct scatterlist *psg = &qc->pad_sgent; |
| |
| assert(qc->dev->class == ATA_DEV_ATAPI); |
| |
| memset(pad_buf, 0, ATA_DMA_PAD_SZ); |
| |
| if (qc->tf.flags & ATA_TFLAG_WRITE) |
| memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len, |
| qc->pad_len); |
| |
| sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ); |
| sg_dma_len(psg) = ATA_DMA_PAD_SZ; |
| /* trim sg */ |
| sg->length -= qc->pad_len; |
| |
| DPRINTK("padding done, sg->length=%u pad_len=%u\n", |
| sg->length, qc->pad_len); |
| } |
| |
| if (!sg->length) { |
| sg_dma_address(sg) = 0; |
| goto skip_map; |
| } |
| |
| dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt, |
| sg->length, dir); |
| if (dma_mapping_error(dma_address)) { |
| /* restore sg */ |
| sg->length += qc->pad_len; |
| return -1; |
| } |
| |
| sg_dma_address(sg) = dma_address; |
| skip_map: |
| sg_dma_len(sg) = sg->length; |
| |
| DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg), |
| qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); |
| |
| return 0; |
| } |
| |
| /** |
| * ata_sg_setup - DMA-map the scatter-gather table associated with a command. |
| * @qc: Command with scatter-gather table to be mapped. |
| * |
| * DMA-map the scatter-gather table associated with queued_cmd @qc. |
| * |
| * LOCKING: |
| * spin_lock_irqsave(host_set lock) |
| * |
| * RETURNS: |
| * Zero on success, negative on error. |
| * |
| */ |
| |
| static int ata_sg_setup(struct ata_queued_cmd *qc) |
| { |
| struct ata_port *ap = qc->ap; |
| struct scatterlist *sg = qc->__sg; |
| struct scatterlist *lsg = &sg[qc->n_elem - 1]; |
| int n_elem, pre_n_elem, dir, trim_sg = 0; |
| |
| VPRINTK("ENTER, ata%u\n", ap->id); |
| assert(qc->flags & ATA_QCFLAG_SG); |
| |
| /* we must lengthen transfers to end on a 32-bit boundary */ |
| qc->pad_len = lsg->length & 3; |
| if (qc->pad_len) { |
| void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ); |
| struct scatterlist *psg = &qc->pad_sgent; |
| unsigned int offset; |
| |
| assert(qc->dev->class == ATA_DEV_ATAPI); |
| |
| memset(pad_buf, 0, ATA_DMA_PAD_SZ); |
| |
| /* |
| * psg->page/offset are used to copy to-be-written |
| * data in this function or read data in ata_sg_clean. |
| */ |
| offset = lsg->offset + lsg->length - qc->pad_len; |
| psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT); |
| psg->offset = offset_in_page(offset); |
| |
| if (qc->tf.flags & ATA_TFLAG_WRITE) { |
| void *addr = kmap_atomic(psg->page, KM_IRQ0); |
| memcpy(pad_buf, addr + psg->offset, qc->pad_len); |
| kunmap_atomic(psg->page, KM_IRQ0); |
| } |
| |
| sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ); |
| sg_dma_len(psg) = ATA_DMA_PAD_SZ; |
| /* trim last sg */ |
| lsg->length -= qc->pad_len; |
| if (lsg->length == 0) |
| trim_sg = 1; |
| |
| DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n", |
| qc->n_elem - 1, lsg->length, qc->pad_len); |
| } |
| |
| pre_n_elem = qc->n_elem; |
| if (trim_sg && pre_n_elem) |
| pre_n_elem--; |
| |
| if (!pre_n_elem) { |
| n_elem = 0; |
| goto skip_map; |
| } |
| |
| dir = qc->dma_dir; |
| n_elem = dma_map_sg(ap->host_set->dev, sg, pre_n_elem, dir); |
| if (n_elem < 1) { |
| /* restore last sg */ |
| lsg->length += qc->pad_len; |
| return -1; |
| } |
| |
| DPRINTK("%d sg elements mapped\n", n_elem); |
| |
| skip_map: |
| qc->n_elem = n_elem; |
| |
| return 0; |
| } |
| |
| /** |
| * ata_poll_qc_complete - turn irq back on and finish qc |
| * @qc: Command to complete |
| * @err_mask: ATA status register content |
| * |
| * LOCKING: |
| * None. (grabs host lock) |
| */ |
| |
| void ata_poll_qc_complete(struct ata_queued_cmd *qc, unsigned int err_mask) |
| { |
| struct ata_port *ap = qc->ap; |
| unsigned long flags; |
| |
| spin_lock_irqsave(&ap->host_set->lock, flags); |
| ap->flags &= ~ATA_FLAG_NOINTR; |
| ata_irq_on(ap); |
| ata_qc_complete(qc, err_mask); |
| spin_unlock_irqrestore(&ap->host_set->lock, flags); |
| } |
| |
| /** |
| * ata_pio_poll - |
| * @ap: the target ata_port |
| * |
| * LOCKING: |
| * None. (executing in kernel thread context) |
| * |
| * RETURNS: |
| * timeout value to use |
| */ |
| |
| static unsigned long ata_pio_poll(struct ata_port *ap) |
| { |
| u8 status; |
| unsigned int poll_state = HSM_ST_UNKNOWN; |
| unsigned int reg_state = HSM_ST_UNKNOWN; |
| |
| switch (ap->hsm_task_state) { |
| case HSM_ST: |
| case HSM_ST_POLL: |
| poll_state = HSM_ST_POLL; |
| reg_state = HSM_ST; |
| break; |
| case HSM_ST_LAST: |
| case HSM_ST_LAST_POLL: |
| poll_state = HSM_ST_LAST_POLL; |
| reg_state = HSM_ST_LAST; |
| break; |
| default: |
| BUG(); |
| break; |
| } |
| |
| status = ata_chk_status(ap); |
| if (status & ATA_BUSY) { |
| if (time_after(jiffies, ap->pio_task_timeout)) { |
| ap->hsm_task_state = HSM_ST_TMOUT; |
| return 0; |
| } |
| ap->hsm_task_state = poll_state; |
| return ATA_SHORT_PAUSE; |
| } |
| |
| ap->hsm_task_state = reg_state; |
| return 0; |
| } |
| |
| /** |
| * ata_pio_complete - check if drive is busy or idle |
| * @ap: the target ata_port |
| * |
| * LOCKING: |
| * None. (executing in kernel thread context) |
| * |
| * RETURNS: |
| * Non-zero if qc completed, zero otherwise. |
| */ |
| |
| static int ata_pio_complete (struct ata_port *ap) |
| { |
| struct ata_queued_cmd *qc; |
| u8 drv_stat; |
| |
| /* |
| * This is purely heuristic. This is a fast path. Sometimes when |
| * we enter, BSY will be cleared in a chk-status or two. If not, |
| * the drive is probably seeking or something. Snooze for a couple |
| * msecs, then chk-status again. If still busy, fall back to |
| * HSM_ST_POLL state. |
| */ |
| drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 10); |
| if (drv_stat & (ATA_BUSY | ATA_DRQ)) { |
| msleep(2); |
| drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 10); |
| if (drv_stat & (ATA_BUSY | ATA_DRQ)) { |
| ap->hsm_task_state = HSM_ST_LAST_POLL; |
| ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO; |
| return 0; |
| } |
| } |
| |
| drv_stat = ata_wait_idle(ap); |
| if (!ata_ok(drv_stat)) { |
| ap->hsm_task_state = HSM_ST_ERR; |
| return 0; |
| } |
| |
| qc = ata_qc_from_tag(ap, ap->active_tag); |
| assert(qc != NULL); |
| |
| ap->hsm_task_state = HSM_ST_IDLE; |
| |
| ata_poll_qc_complete(qc, 0); |
| |
| /* another command may start at this point */ |
| |
| return 1; |
| } |
| |
| |
| /** |
| * swap_buf_le16 - swap halves of 16-words in place |
| * @buf: Buffer to swap |
| * @buf_words: Number of 16-bit words in buffer. |
| * |
| * Swap halves of 16-bit words if needed to convert from |
| * little-endian byte order to native cpu byte order, or |
| * vice-versa. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| void swap_buf_le16(u16 *buf, unsigned int buf_words) |
| { |
| #ifdef __BIG_ENDIAN |
| unsigned int i; |
| |
| for (i = 0; i < buf_words; i++) |
| buf[i] = le16_to_cpu(buf[i]); |
| #endif /* __BIG_ENDIAN */ |
| } |
| |
| /** |
| * ata_mmio_data_xfer - Transfer data by MMIO |
| * @ap: port to read/write |
| * @buf: data buffer |
| * @buflen: buffer length |
| * @write_data: read/write |
| * |
| * Transfer data from/to the device data register by MMIO. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf, |
| unsigned int buflen, int write_data) |
| { |
| unsigned int i; |
| unsigned int words = buflen >> 1; |
| u16 *buf16 = (u16 *) buf; |
| void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr; |
| |
| /* Transfer multiple of 2 bytes */ |
| if (write_data) { |
| for (i = 0; i < words; i++) |
| writew(le16_to_cpu(buf16[i]), mmio); |
| } else { |
| for (i = 0; i < words; i++) |
| buf16[i] = cpu_to_le16(readw(mmio)); |
| } |
| |
| /* Transfer trailing 1 byte, if any. */ |
| if (unlikely(buflen & 0x01)) { |
| u16 align_buf[1] = { 0 }; |
| unsigned char *trailing_buf = buf + buflen - 1; |
| |
| if (write_data) { |
| memcpy(align_buf, trailing_buf, 1); |
| writew(le16_to_cpu(align_buf[0]), mmio); |
| } else { |
| align_buf[0] = cpu_to_le16(readw(mmio)); |
| memcpy(trailing_buf, align_buf, 1); |
| } |
| } |
| } |
| |
| /** |
| * ata_pio_data_xfer - Transfer data by PIO |
| * @ap: port to read/write |
| * @buf: data buffer |
| * @buflen: buffer length |
| * @write_data: read/write |
| * |
| * Transfer data from/to the device data register by PIO. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf, |
| unsigned int buflen, int write_data) |
| { |
| unsigned int words = buflen >> 1; |
| |
| /* Transfer multiple of 2 bytes */ |
| if (write_data) |
| outsw(ap->ioaddr.data_addr, buf, words); |
| else |
| insw(ap->ioaddr.data_addr, buf, words); |
| |
| /* Transfer trailing 1 byte, if any. */ |
| if (unlikely(buflen & 0x01)) { |
| u16 align_buf[1] = { 0 }; |
| unsigned char *trailing_buf = buf + buflen - 1; |
| |
| if (write_data) { |
| memcpy(align_buf, trailing_buf, 1); |
| outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr); |
| } else { |
| align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr)); |
| memcpy(trailing_buf, align_buf, 1); |
| } |
| } |
| } |
| |
| /** |
| * ata_data_xfer - Transfer data from/to the data register. |
| * @ap: port to read/write |
| * @buf: data buffer |
| * @buflen: buffer length |
| * @do_write: read/write |
| * |
| * Transfer data from/to the device data register. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| static void ata_data_xfer(struct ata_port *ap, unsigned char *buf, |
| unsigned int buflen, int do_write) |
| { |
| if (ap->flags & ATA_FLAG_MMIO) |
| ata_mmio_data_xfer(ap, buf, buflen, do_write); |
| else |
| ata_pio_data_xfer(ap, buf, buflen, do_write); |
| } |
| |
| /** |
| * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data. |
| * @qc: Command on going |
| * |
| * Transfer ATA_SECT_SIZE of data from/to the ATA device. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| static void ata_pio_sector(struct ata_queued_cmd *qc) |
| { |
| int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); |
| struct scatterlist *sg = qc->__sg; |
| struct ata_port *ap = qc->ap; |
| struct page *page; |
| unsigned int offset; |
| unsigned char *buf; |
| |
| if (qc->cursect == (qc->nsect - 1)) |
| ap->hsm_task_state = HSM_ST_LAST; |
| |
| page = sg[qc->cursg].page; |
| offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE; |
| |
| /* get the current page and offset */ |
| page = nth_page(page, (offset >> PAGE_SHIFT)); |
| offset %= PAGE_SIZE; |
| |
| buf = kmap(page) + offset; |
| |
| qc->cursect++; |
| qc->cursg_ofs++; |
| |
| if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) { |
| qc->cursg++; |
| qc->cursg_ofs = 0; |
| } |
| |
| DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); |
| |
| /* do the actual data transfer */ |
| do_write = (qc->tf.flags & ATA_TFLAG_WRITE); |
| ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write); |
| |
| kunmap(page); |
| } |
| |
| /** |
| * __atapi_pio_bytes - Transfer data from/to the ATAPI device. |
| * @qc: Command on going |
| * @bytes: number of bytes |
| * |
| * Transfer Transfer data from/to the ATAPI device. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| * |
| */ |
| |
| static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) |
| { |
| int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); |
| struct scatterlist *sg = qc->__sg; |
| struct ata_port *ap = qc->ap; |
| struct page *page; |
| unsigned char *buf; |
| unsigned int offset, count; |
| |
| if (qc->curbytes + bytes >= qc->nbytes) |
| ap->hsm_task_state = HSM_ST_LAST; |
| |
| next_sg: |
| if (unlikely(qc->cursg >= qc->n_elem)) { |
| /* |
| * The end of qc->sg is reached and the device expects |
| * more data to transfer. In order not to overrun qc->sg |
| * and fulfill length specified in the byte count register, |
| * - for read case, discard trailing data from the device |
| * - for write case, padding zero data to the device |
| */ |
| u16 pad_buf[1] = { 0 }; |
| unsigned int words = bytes >> 1; |
| unsigned int i; |
| |
| if (words) /* warning if bytes > 1 */ |
| printk(KERN_WARNING "ata%u: %u bytes trailing data\n", |
| ap->id, bytes); |
| |
| for (i = 0; i < words; i++) |
| ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write); |
| |
| ap->hsm_task_state = HSM_ST_LAST; |
| return; |
| } |
| |
| sg = &qc->__sg[qc->cursg]; |
| |
| page = sg->page; |
| offset = sg->offset + qc->cursg_ofs; |
| |
| /* get the current page and offset */ |
| page = nth_page(page, (offset >> PAGE_SHIFT)); |
| offset %= PAGE_SIZE; |
| |
| /* don't overrun current sg */ |
| count = min(sg->length - qc->cursg_ofs, bytes); |
| |
| /* don't cross page boundaries */ |
| count = min(count, (unsigned int)PAGE_SIZE - offset); |
| |
| buf = kmap(page) + offset; |
| |
| bytes -= count; |
| qc->curbytes += count; |
| qc->cursg_ofs += count; |
| |
| if (qc->cursg_ofs == sg->length) { |
| qc->cursg++; |
| qc->cursg_ofs = 0; |
| } |
| |
| DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); |
| |
| /* do the actual data transfer */ |
| ata_data_xfer(ap, buf, count, do_write); |
| |
| kunmap(page); |
| |
| if (bytes) |
| goto next_sg; |
| } |
| |
| /** |
| * atapi_pio_bytes - Transfer data from/to the ATAPI device. |
| * @qc: Command on going |
| * |
| * Transfer Transfer data from/to the ATAPI device. |
| * |
| * LOCKING: |
| * Inherited from caller. |
| */ |
| |
| static void atapi_pio_bytes(struct ata_queued_cmd *qc) |
| { |
| struct ata_port *ap = qc->ap; |
| struct ata_device *dev = qc->dev; |
| unsigned int ireason, bc_lo, bc_hi, bytes; |
| int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; |
| |
| ap->ops->tf_read(ap, &qc->tf); |
| ireason = qc->tf.nsect; |
| bc_lo = qc->tf.lbam; |
| bc_hi = qc->tf.lbah; |
| bytes = (bc_hi << 8) | bc_lo; |
| |
| /* shall be cleared to zero, indicating xfer of data */ |
| if (ireason & (1 << 0)) |
| goto err_out; |
| |
| /* make sure transfer direction matches expected */ |
| i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; |
| if (do_write != i_write) |
| goto err_out; |
| |
| __atapi_pio_bytes(qc, bytes); |
| |
| return; |
| |
| err_out: |
| printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n", |
| ap->id, dev->devno); |
| ap->hsm_task_state = HSM_ST_ERR; |
| } |
| |
| /** |
| * ata_pio_block - start PIO on a block |
| * @ap: the target ata_port |
| * |
| * LOCKING: |
| * None. (executing in kernel thread context) |
| */ |
| |
| static void ata_pio_block(struct ata_port *ap) |
| { |
| struct ata_queued_cmd *qc; |
| u8 status; |
|