arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2018-2019 SiFive, Inc */

#include "fu540-c000.dtsi"
#include <dt-bindings/gpio/gpio.h>

/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
#define RTCCLK_FREQ		1000000

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "SiFive HiFive Unleashed A00";
	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";

	chosen {
		stdout-path = "serial0";
	};

	cpus {
		timebase-frequency = <RTCCLK_FREQ>;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x2 0x00000000>;
	};

	soc {
	};

	hfclk: hfclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <33333333>;
		clock-output-names = "hfclk";
	};

	rtcclk: rtcclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <RTCCLK_FREQ>;
		clock-output-names = "rtcclk";
	};
	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&qspi0 {
	status = "okay";
	flash@0 {
		compatible = "issi,is25wp256", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <50000000>;
		m25p,fast-read;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&qspi2 {
	status = "okay";
	mmc@0 {
		compatible = "mmc-spi-slot";
		reg = <0>;
		spi-max-frequency = <20000000>;
		voltage-ranges = <3300 3300>;
		disable-wp;
	};
};

&eth0 {
	status = "okay";
	phy-mode = "gmii";
	phy-handle = <&phy0>;
	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-id0007.0771";
		reg = <0>;
		reset-gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
	};
};

&pwm0 {
	status = "okay";
};

&pwm1 {
	status = "okay";
};

&gpio {
	status = "okay";
};