| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| */ |
| |
| #ifndef QCOM_PHY_QMP_PCS_V2_H_ |
| #define QCOM_PHY_QMP_PCS_V2_H_ |
| |
| /* Only for QMP V2 PHY - PCS registers */ |
| #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004 |
| #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024 |
| #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028 |
| #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034 |
| #define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038 |
| #define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c |
| #define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040 |
| #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054 |
| #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058 |
| #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060 |
| #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064 |
| #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c |
| #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080 |
| #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084 |
| #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088 |
| #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 |
| #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 |
| #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 |
| #define QPHY_V2_PCS_FLL_CNTRL1 0x0c0 |
| #define QPHY_V2_PCS_FLL_CNTRL2 0x0c4 |
| #define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8 |
| #define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc |
| #define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0 |
| |
| /* UFS only ? */ |
| #define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc |
| #define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c |
| #define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 |
| #define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 |
| #define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 |
| #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 |
| #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac |
| #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 |
| #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc |
| #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 |
| |
| #endif |
