Masahiro Yamada | d9c5252 | 2019-07-25 16:58:31 +0900 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
Jeeja KP | 23db472 | 2015-08-01 19:40:41 +0530 | [diff] [blame] | 2 | /* |
| 3 | * skl-tplg-interface.h - Intel DSP FW private data interface |
| 4 | * |
| 5 | * Copyright (C) 2015 Intel Corp |
| 6 | * Author: Jeeja KP <jeeja.kp@intel.com> |
| 7 | * Nilofer, Samreen <samreen.nilofer@intel.com> |
Jeeja KP | 23db472 | 2015-08-01 19:40:41 +0530 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __HDA_TPLG_INTERFACE_H__ |
| 11 | #define __HDA_TPLG_INTERFACE_H__ |
| 12 | |
Dmitry V. Levin | fb504ca | 2018-08-13 18:50:02 +0300 | [diff] [blame] | 13 | #include <linux/types.h> |
| 14 | |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 15 | /* |
| 16 | * Default types range from 0~12. type can range from 0 to 0xff |
| 17 | * SST types start at higher to avoid any overlapping in future |
| 18 | */ |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 19 | #define SKL_CONTROL_TYPE_BYTE_TLV 0x100 |
Dharageswari R | 7a1b749 | 2017-05-31 10:30:25 +0530 | [diff] [blame] | 20 | #define SKL_CONTROL_TYPE_MIC_SELECT 0x102 |
Mateusz Gorski | 1b45079 | 2020-04-27 15:27:26 +0200 | [diff] [blame] | 21 | #define SKL_CONTROL_TYPE_MULTI_IO_SELECT 0x103 |
Mateusz Gorski | 2d744ec | 2020-04-27 15:27:27 +0200 | [diff] [blame] | 22 | #define SKL_CONTROL_TYPE_MULTI_IO_SELECT_DMIC 0x104 |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 23 | |
| 24 | #define HDA_SST_CFG_MAX 900 /* size of copier cfg*/ |
| 25 | #define MAX_IN_QUEUE 8 |
| 26 | #define MAX_OUT_QUEUE 8 |
| 27 | |
Hardik T Shah | 65aecfa | 2015-10-27 09:22:57 +0900 | [diff] [blame] | 28 | #define SKL_UUID_STR_SZ 40 |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 29 | /* Event types goes here */ |
| 30 | /* Reserve event type 0 for no event handlers */ |
| 31 | enum skl_event_types { |
| 32 | SKL_EVENT_NONE = 0, |
| 33 | SKL_MIXER_EVENT, |
| 34 | SKL_MUX_EVENT, |
| 35 | SKL_VMIXER_EVENT, |
| 36 | SKL_PGA_EVENT |
| 37 | }; |
| 38 | |
Jeeja KP | 23db472 | 2015-08-01 19:40:41 +0530 | [diff] [blame] | 39 | /** |
| 40 | * enum skl_ch_cfg - channel configuration |
| 41 | * |
| 42 | * @SKL_CH_CFG_MONO: One channel only |
| 43 | * @SKL_CH_CFG_STEREO: L & R |
| 44 | * @SKL_CH_CFG_2_1: L, R & LFE |
| 45 | * @SKL_CH_CFG_3_0: L, C & R |
| 46 | * @SKL_CH_CFG_3_1: L, C, R & LFE |
| 47 | * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs |
| 48 | * @SKL_CH_CFG_4_0: L, C, R & Cs |
| 49 | * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs |
| 50 | * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE |
| 51 | * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two |
| 52 | * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ] |
| 53 | * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ] |
| 54 | * @SKL_CH_CFG_INVALID: Invalid |
| 55 | */ |
| 56 | enum skl_ch_cfg { |
| 57 | SKL_CH_CFG_MONO = 0, |
| 58 | SKL_CH_CFG_STEREO = 1, |
| 59 | SKL_CH_CFG_2_1 = 2, |
| 60 | SKL_CH_CFG_3_0 = 3, |
| 61 | SKL_CH_CFG_3_1 = 4, |
| 62 | SKL_CH_CFG_QUATRO = 5, |
| 63 | SKL_CH_CFG_4_0 = 6, |
| 64 | SKL_CH_CFG_5_0 = 7, |
| 65 | SKL_CH_CFG_5_1 = 8, |
| 66 | SKL_CH_CFG_DUAL_MONO = 9, |
| 67 | SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10, |
| 68 | SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11, |
Hardik T Shah | 04afbbb | 2015-10-27 09:22:56 +0900 | [diff] [blame] | 69 | SKL_CH_CFG_4_CHANNEL = 12, |
Jeeja KP | 23db472 | 2015-08-01 19:40:41 +0530 | [diff] [blame] | 70 | SKL_CH_CFG_INVALID |
| 71 | }; |
| 72 | |
| 73 | enum skl_module_type { |
| 74 | SKL_MODULE_TYPE_MIXER = 0, |
| 75 | SKL_MODULE_TYPE_COPIER, |
| 76 | SKL_MODULE_TYPE_UPDWMIX, |
Jeeja KP | 399b210 | 2015-11-28 15:01:48 +0530 | [diff] [blame] | 77 | SKL_MODULE_TYPE_SRCINT, |
Dharageswari R | fd18110 | 2015-12-03 23:29:52 +0530 | [diff] [blame] | 78 | SKL_MODULE_TYPE_ALGO, |
Dharageswari R | 5e8f0ee | 2016-09-22 14:00:40 +0530 | [diff] [blame] | 79 | SKL_MODULE_TYPE_BASE_OUTFMT, |
| 80 | SKL_MODULE_TYPE_KPB, |
Dharageswari R | db6879e | 2017-05-31 10:30:24 +0530 | [diff] [blame] | 81 | SKL_MODULE_TYPE_MIC_SELECT, |
Jeeja KP | 23db472 | 2015-08-01 19:40:41 +0530 | [diff] [blame] | 82 | }; |
| 83 | |
| 84 | enum skl_core_affinity { |
| 85 | SKL_AFFINITY_CORE_0 = 0, |
| 86 | SKL_AFFINITY_CORE_1, |
| 87 | SKL_AFFINITY_CORE_MAX |
| 88 | }; |
| 89 | |
| 90 | enum skl_pipe_conn_type { |
| 91 | SKL_PIPE_CONN_TYPE_NONE = 0, |
| 92 | SKL_PIPE_CONN_TYPE_FE, |
| 93 | SKL_PIPE_CONN_TYPE_BE |
| 94 | }; |
| 95 | |
| 96 | enum skl_hw_conn_type { |
| 97 | SKL_CONN_NONE = 0, |
| 98 | SKL_CONN_SOURCE = 1, |
| 99 | SKL_CONN_SINK = 2 |
| 100 | }; |
| 101 | |
| 102 | enum skl_dev_type { |
| 103 | SKL_DEVICE_BT = 0x0, |
| 104 | SKL_DEVICE_DMIC = 0x1, |
| 105 | SKL_DEVICE_I2S = 0x2, |
| 106 | SKL_DEVICE_SLIMBUS = 0x3, |
| 107 | SKL_DEVICE_HDALINK = 0x4, |
Jeeja KP | bfa764a | 2015-10-22 23:22:41 +0530 | [diff] [blame] | 108 | SKL_DEVICE_HDAHOST = 0x5, |
Jeeja KP | 23db472 | 2015-08-01 19:40:41 +0530 | [diff] [blame] | 109 | SKL_DEVICE_NONE |
| 110 | }; |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 111 | |
Hardik T Shah | 04afbbb | 2015-10-27 09:22:56 +0900 | [diff] [blame] | 112 | /** |
| 113 | * enum skl_interleaving - interleaving style |
| 114 | * |
| 115 | * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN] |
| 116 | * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN] |
| 117 | */ |
| 118 | enum skl_interleaving { |
| 119 | SKL_INTERLEAVING_PER_CHANNEL = 0, |
| 120 | SKL_INTERLEAVING_PER_SAMPLE = 1, |
| 121 | }; |
| 122 | |
| 123 | enum skl_sample_type { |
| 124 | SKL_SAMPLE_TYPE_INT_MSB = 0, |
| 125 | SKL_SAMPLE_TYPE_INT_LSB = 1, |
| 126 | SKL_SAMPLE_TYPE_INT_SIGNED = 2, |
| 127 | SKL_SAMPLE_TYPE_INT_UNSIGNED = 3, |
| 128 | SKL_SAMPLE_TYPE_FLOAT = 4 |
| 129 | }; |
| 130 | |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 131 | enum module_pin_type { |
| 132 | /* All pins of the module takes same PCM inputs or outputs |
| 133 | * e.g. mixout |
| 134 | */ |
| 135 | SKL_PIN_TYPE_HOMOGENEOUS, |
| 136 | /* All pins of the module takes different PCM inputs or outputs |
| 137 | * e.g mux |
| 138 | */ |
| 139 | SKL_PIN_TYPE_HETEROGENEOUS, |
| 140 | }; |
| 141 | |
Jeeja KP | 4ced182 | 2015-12-03 23:29:53 +0530 | [diff] [blame] | 142 | enum skl_module_param_type { |
| 143 | SKL_PARAM_DEFAULT = 0, |
| 144 | SKL_PARAM_INIT, |
Jeeja KP | cc6a404 | 2016-02-05 12:19:08 +0530 | [diff] [blame] | 145 | SKL_PARAM_SET, |
| 146 | SKL_PARAM_BIND |
Jeeja KP | 4ced182 | 2015-12-03 23:29:53 +0530 | [diff] [blame] | 147 | }; |
| 148 | |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 149 | struct skl_dfw_algo_data { |
Dmitry V. Levin | fb504ca | 2018-08-13 18:50:02 +0300 | [diff] [blame] | 150 | __u32 set_params:2; |
| 151 | __u32 rsvd:30; |
| 152 | __u32 param_id; |
| 153 | __u32 max; |
Hardik T Shah | 04afbbb | 2015-10-27 09:22:56 +0900 | [diff] [blame] | 154 | char params[0]; |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 155 | } __packed; |
| 156 | |
Shreyas NC | 6277e83 | 2016-08-12 12:29:51 +0530 | [diff] [blame] | 157 | enum skl_tkn_dir { |
| 158 | SKL_DIR_IN, |
| 159 | SKL_DIR_OUT |
| 160 | }; |
| 161 | |
| 162 | enum skl_tuple_type { |
| 163 | SKL_TYPE_TUPLE, |
| 164 | SKL_TYPE_DATA |
| 165 | }; |
| 166 | |
Guenter Roeck | ac9391d | 2018-05-24 12:49:21 -0700 | [diff] [blame] | 167 | /* v4 configuration data */ |
| 168 | |
| 169 | struct skl_dfw_v4_module_pin { |
Dmitry V. Levin | fb504ca | 2018-08-13 18:50:02 +0300 | [diff] [blame] | 170 | __u16 module_id; |
| 171 | __u16 instance_id; |
Guenter Roeck | ac9391d | 2018-05-24 12:49:21 -0700 | [diff] [blame] | 172 | } __packed; |
| 173 | |
| 174 | struct skl_dfw_v4_module_fmt { |
Dmitry V. Levin | fb504ca | 2018-08-13 18:50:02 +0300 | [diff] [blame] | 175 | __u32 channels; |
| 176 | __u32 freq; |
| 177 | __u32 bit_depth; |
| 178 | __u32 valid_bit_depth; |
| 179 | __u32 ch_cfg; |
| 180 | __u32 interleaving_style; |
| 181 | __u32 sample_type; |
| 182 | __u32 ch_map; |
Guenter Roeck | ac9391d | 2018-05-24 12:49:21 -0700 | [diff] [blame] | 183 | } __packed; |
| 184 | |
| 185 | struct skl_dfw_v4_module_caps { |
Dmitry V. Levin | fb504ca | 2018-08-13 18:50:02 +0300 | [diff] [blame] | 186 | __u32 set_params:2; |
| 187 | __u32 rsvd:30; |
| 188 | __u32 param_id; |
| 189 | __u32 caps_size; |
| 190 | __u32 caps[HDA_SST_CFG_MAX]; |
Guenter Roeck | ac9391d | 2018-05-24 12:49:21 -0700 | [diff] [blame] | 191 | } __packed; |
| 192 | |
| 193 | struct skl_dfw_v4_pipe { |
Dmitry V. Levin | fb504ca | 2018-08-13 18:50:02 +0300 | [diff] [blame] | 194 | __u8 pipe_id; |
| 195 | __u8 pipe_priority; |
| 196 | __u16 conn_type:4; |
| 197 | __u16 rsvd:4; |
| 198 | __u16 memory_pages:8; |
Guenter Roeck | ac9391d | 2018-05-24 12:49:21 -0700 | [diff] [blame] | 199 | } __packed; |
| 200 | |
| 201 | struct skl_dfw_v4_module { |
| 202 | char uuid[SKL_UUID_STR_SZ]; |
| 203 | |
Dmitry V. Levin | fb504ca | 2018-08-13 18:50:02 +0300 | [diff] [blame] | 204 | __u16 module_id; |
| 205 | __u16 instance_id; |
| 206 | __u32 max_mcps; |
| 207 | __u32 mem_pages; |
| 208 | __u32 obs; |
| 209 | __u32 ibs; |
| 210 | __u32 vbus_id; |
Guenter Roeck | ac9391d | 2018-05-24 12:49:21 -0700 | [diff] [blame] | 211 | |
Dmitry V. Levin | fb504ca | 2018-08-13 18:50:02 +0300 | [diff] [blame] | 212 | __u32 max_in_queue:8; |
| 213 | __u32 max_out_queue:8; |
| 214 | __u32 time_slot:8; |
| 215 | __u32 core_id:4; |
| 216 | __u32 rsvd1:4; |
Guenter Roeck | ac9391d | 2018-05-24 12:49:21 -0700 | [diff] [blame] | 217 | |
Dmitry V. Levin | fb504ca | 2018-08-13 18:50:02 +0300 | [diff] [blame] | 218 | __u32 module_type:8; |
| 219 | __u32 conn_type:4; |
| 220 | __u32 dev_type:4; |
| 221 | __u32 hw_conn_type:4; |
| 222 | __u32 rsvd2:12; |
Guenter Roeck | ac9391d | 2018-05-24 12:49:21 -0700 | [diff] [blame] | 223 | |
Dmitry V. Levin | fb504ca | 2018-08-13 18:50:02 +0300 | [diff] [blame] | 224 | __u32 params_fixup:8; |
| 225 | __u32 converter:8; |
| 226 | __u32 input_pin_type:1; |
| 227 | __u32 output_pin_type:1; |
| 228 | __u32 is_dynamic_in_pin:1; |
| 229 | __u32 is_dynamic_out_pin:1; |
| 230 | __u32 is_loadable:1; |
| 231 | __u32 rsvd3:11; |
Guenter Roeck | ac9391d | 2018-05-24 12:49:21 -0700 | [diff] [blame] | 232 | |
| 233 | struct skl_dfw_v4_pipe pipe; |
| 234 | struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE]; |
| 235 | struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE]; |
| 236 | struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE]; |
| 237 | struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE]; |
| 238 | struct skl_dfw_v4_module_caps caps; |
| 239 | } __packed; |
| 240 | |
Jeeja KP | 23db472 | 2015-08-01 19:40:41 +0530 | [diff] [blame] | 241 | #endif |