| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree Source for K2G EVM |
| * |
| * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ |
| */ |
| /dts-v1/; |
| |
| #include "keystone-k2g.dtsi" |
| |
| / { |
| compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone"; |
| model = "Texas Instruments K2G General Purpose EVM"; |
| |
| memory@800000000 { |
| device_type = "memory"; |
| reg = <0x00000008 0x00000000 0x00000000 0x80000000>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| dsp_common_memory: dsp-common-memory@81f800000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00000008 0x1f800000 0x00000000 0x800000>; |
| reusable; |
| status = "okay"; |
| }; |
| }; |
| |
| vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin { |
| compatible = "regulator-fixed"; |
| regulator-name = "mmc0_fixed"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 { |
| compatible = "regulator-fixed"; |
| regulator-name = "ldo1"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| }; |
| }; |
| |
| &k2g_pinctrl { |
| uart0_pins: pinmux_uart0_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
| K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
| >; |
| }; |
| |
| mmc0_pins: pinmux_mmc0_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */ |
| K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */ |
| K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */ |
| K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */ |
| K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */ |
| K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */ |
| K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */ |
| >; |
| }; |
| |
| mmc1_pins: pinmux_mmc1_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */ |
| K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */ |
| K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */ |
| K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */ |
| K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ |
| K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ |
| K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ |
| K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ |
| K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ |
| K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ |
| >; |
| }; |
| |
| i2c0_pins: pinmux_i2c0_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
| K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| >; |
| }; |
| |
| ecap0_pins: ecap0_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ |
| >; |
| }; |
| |
| spi1_pins: pinmux_spi1_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ |
| K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ |
| K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */ |
| K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */ |
| >; |
| }; |
| |
| qspi_pins: pinmux_qspi_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ |
| K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ |
| K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ |
| K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ |
| K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ |
| K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ |
| K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ |
| >; |
| }; |
| |
| uart2_pins: pinmux_uart2_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */ |
| K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */ |
| >; |
| }; |
| |
| dcan0_pins: pinmux_dcan0_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */ |
| K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */ |
| >; |
| }; |
| |
| dcan1_pins: pinmux_dcan1_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */ |
| K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ |
| >; |
| }; |
| |
| emac_pins: pinmux_emac_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ |
| K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ |
| K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ |
| K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ |
| K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ |
| K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ |
| K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ |
| K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ |
| K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ |
| K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ |
| K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ |
| K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ |
| >; |
| }; |
| |
| mdio_pins: pinmux_mdio_pins { |
| pinctrl-single,pins = < |
| K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ |
| K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ |
| >; |
| }; |
| }; |
| |
| &uart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart0_pins>; |
| status = "okay"; |
| }; |
| |
| &gpio1 { |
| status = "okay"; |
| }; |
| |
| &mmc0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc0_pins>; |
| vmmc-supply = <&vcc3v3_dcin_reg>; |
| vqmmc-supply = <&vcc3v3_dcin_reg>; |
| cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &mmc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc1_pins>; |
| vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */ |
| vqmmc-supply = <&vcc1v8_ldo1_reg>; |
| ti,non-removable; |
| status = "okay"; |
| }; |
| |
| &dsp0 { |
| memory-region = <&dsp_common_memory>; |
| status = "okay"; |
| }; |
| |
| &i2c0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_pins>; |
| status = "okay"; |
| |
| eeprom@50 { |
| compatible = "atmel,24c1024"; |
| reg = <0x50>; |
| }; |
| }; |
| |
| &keystone_usb0 { |
| status = "okay"; |
| }; |
| |
| &usb0_phy { |
| status = "okay"; |
| }; |
| |
| &usb0 { |
| dr_mode = "host"; |
| status = "okay"; |
| }; |
| |
| &keystone_usb1 { |
| status = "okay"; |
| }; |
| |
| &usb1_phy { |
| status = "okay"; |
| }; |
| |
| &usb1 { |
| dr_mode = "peripheral"; |
| status = "okay"; |
| }; |
| |
| &ecap0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&ecap0_pins>; |
| }; |
| |
| &spi1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi1_pins>; |
| status = "okay"; |
| |
| spi_nor: flash@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "jedec,spi-nor"; |
| spi-max-frequency = <5000000>; |
| m25p,fast-read; |
| reg = <0>; |
| |
| partition@0 { |
| label = "u-boot-spl"; |
| reg = <0x0 0x100000>; |
| read-only; |
| }; |
| |
| partition@1 { |
| label = "misc"; |
| reg = <0x100000 0xf00000>; |
| }; |
| }; |
| }; |
| |
| &qspi { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qspi_pins>; |
| cdns,rclk-en; |
| |
| flash0: m25p80@0 { |
| compatible = "s25fl512s", "jedec,spi-nor"; |
| reg = <0>; |
| spi-tx-bus-width = <1>; |
| spi-rx-bus-width = <4>; |
| spi-max-frequency = <96000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| cdns,read-delay = <5>; |
| cdns,tshsl-ns = <500>; |
| cdns,tsd2d-ns = <500>; |
| cdns,tchsh-ns = <119>; |
| cdns,tslch-ns = <119>; |
| |
| partition@0 { |
| label = "QSPI.u-boot-spl-os"; |
| reg = <0x00000000 0x00100000>; |
| }; |
| partition@1 { |
| label = "QSPI.u-boot-env"; |
| reg = <0x00100000 0x00040000>; |
| }; |
| partition@2 { |
| label = "QSPI.skern"; |
| reg = <0x00140000 0x0040000>; |
| }; |
| partition@3 { |
| label = "QSPI.pmmc-firmware"; |
| reg = <0x00180000 0x0040000>; |
| }; |
| partition@4 { |
| label = "QSPI.kernel"; |
| reg = <0x001C0000 0x0800000>; |
| }; |
| partition@5 { |
| label = "QSPI.file-system"; |
| reg = <0x009C0000 0x3640000>; |
| }; |
| }; |
| }; |
| |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pins>; |
| status = "okay"; |
| }; |
| |
| &dcan0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&dcan0_pins>; |
| status = "okay"; |
| }; |
| |
| &dcan1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&dcan1_pins>; |
| status = "okay"; |
| }; |
| |
| &qmss { |
| status = "okay"; |
| }; |
| |
| &knav_dmas { |
| status = "okay"; |
| }; |
| |
| &mdio { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mdio_pins>; |
| status = "okay"; |
| ethphy0: ethernet-phy@0 { |
| reg = <0>; |
| }; |
| }; |
| |
| &gbe0 { |
| phy-handle = <ðphy0>; |
| phy-mode = "rgmii-id"; |
| status = "okay"; |
| }; |
| |
| &netcp { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&emac_pins>; |
| status = "okay"; |
| }; |
