| /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
| /* |
| * Copyright (c) 2021 MediaTek Inc. |
| * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
| */ |
| |
| #ifndef _DT_BINDINGS_POWER_MT8195_POWER_H |
| #define _DT_BINDINGS_POWER_MT8195_POWER_H |
| |
| #define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0 |
| #define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1 |
| #define MT8195_POWER_DOMAIN_PCIE_PHY 2 |
| #define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3 |
| #define MT8195_POWER_DOMAIN_CSI_RX_TOP 4 |
| #define MT8195_POWER_DOMAIN_ETHER 5 |
| #define MT8195_POWER_DOMAIN_ADSP 6 |
| #define MT8195_POWER_DOMAIN_AUDIO 7 |
| #define MT8195_POWER_DOMAIN_MFG0 8 |
| #define MT8195_POWER_DOMAIN_MFG1 9 |
| #define MT8195_POWER_DOMAIN_MFG2 10 |
| #define MT8195_POWER_DOMAIN_MFG3 11 |
| #define MT8195_POWER_DOMAIN_MFG4 12 |
| #define MT8195_POWER_DOMAIN_MFG5 13 |
| #define MT8195_POWER_DOMAIN_MFG6 14 |
| #define MT8195_POWER_DOMAIN_VPPSYS0 15 |
| #define MT8195_POWER_DOMAIN_VDOSYS0 16 |
| #define MT8195_POWER_DOMAIN_VPPSYS1 17 |
| #define MT8195_POWER_DOMAIN_VDOSYS1 18 |
| #define MT8195_POWER_DOMAIN_DP_TX 19 |
| #define MT8195_POWER_DOMAIN_EPD_TX 20 |
| #define MT8195_POWER_DOMAIN_HDMI_TX 21 |
| #define MT8195_POWER_DOMAIN_WPESYS 22 |
| #define MT8195_POWER_DOMAIN_VDEC0 23 |
| #define MT8195_POWER_DOMAIN_VDEC1 24 |
| #define MT8195_POWER_DOMAIN_VDEC2 25 |
| #define MT8195_POWER_DOMAIN_VENC 26 |
| #define MT8195_POWER_DOMAIN_VENC_CORE1 27 |
| #define MT8195_POWER_DOMAIN_IMG 28 |
| #define MT8195_POWER_DOMAIN_DIP 29 |
| #define MT8195_POWER_DOMAIN_IPE 30 |
| #define MT8195_POWER_DOMAIN_CAM 31 |
| #define MT8195_POWER_DOMAIN_CAM_RAWA 32 |
| #define MT8195_POWER_DOMAIN_CAM_RAWB 33 |
| #define MT8195_POWER_DOMAIN_CAM_MRAW 34 |
| |
| #endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */ |
